CN101252405B - Clock detection and auto switching method and system - Google Patents
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Abstract
The invention discloses a method of clock detection and automatic switching, a system and a detection circuit which belong to the electronic device technical field. The method includes that the clock signal is received; the clock signal is processed with blocking/band-pass processing and then the AC signal after the processing of blocking/band-pass is obtained; the AC signal processed with the blocking/band-pass processing is rectified or processed with rectification and amplification processing to obtain the pulsation DC signal; the control information is generated according to the pulsation DC signal; a multiple selector is controlled to output a normal clock signal according to the control information. The system comprises a clock source device, a detection-control circuit and a multiple selector; the clock detection circuit comprises a filter circuit, a rectification circuit and a smoothing processing circuit. The technical proposal of the method of clock detection and automatic switching, the system and the detection circuit adopts the simple electronic device to simplify the system clock, reduce the cost of the clock system and improve the stability of the clock system.
Description
Technical Field
The present invention relates to the field of electronic device technologies, and in particular, to a method, a system, and a detection circuit for clock detection and automatic switching.
Background
As is well known, the reliability of a communication system is determined by the availability and redundancy design of each device in the system, and generally, the reliability of the devices in the communication system is targeted to 5 to 9, i.e., the availability requirement is up to 99.999%, and the higher level system reliability requirement is up to 6 to 9.
With the rapid development of the industries such as communication, electronics and the like, the design of devices tends to be more and more complex, the operation rate is faster and faster, the types and the number of the devices carried on a single board are more and more, and the reliability problem of the devices caused by the types and the number is more and more prominent.
In many kinds of devices of a single board, a clock source device is one of core working devices, most other devices operate according to the beat of a clock signal sent by the clock source device, and the influence of the failure of the clock source device on the single board is fatal, so that the reliability of the clock source device is the key influencing the reliability of a system. However, the crystal, crystal oscillator, etc. in the clock source device are often high in failure rate, and the failure rate of the common crystal oscillator is even as high as 50FIT (fitt). Although some vendors are striving to improve the quality of the clock source device, the failure rate is still above 20 FIT. Therefore, how to improve the reliability of the system under the condition that the failure rate of the clock source device is high becomes a problem to be solved urgently. The key to improve the reliability of the system is to improve the reliability of the clock system, the key to improve the reliability of the clock system is to design a clock detection and automatic switching system, and the common method for designing the clock detection and automatic switching system is a bypass redundancy design method.
The prior art provides the following two clock detection and automatic switching systems designed by adopting a side-standby redundancy method:
first, a programmable logic chip is used to perform clock detection and automatic switching, as shown in fig. 1. Clock signals sent by two or more paths of clock source devices are input to the programmable logic chip; the programmable logic chip detects the input clock signal, the general detection method is to count the detected clock signal by the working clock of the programmable logic chip, if the detected clock signal generates the jump of the specified times in the specified time, the circuit clock signal is considered to have no fault; otherwise, the path of clock signal is considered to be in failure. When the clock signal fails, the programmable logic chip switches the clock signal and outputs the clock signal without failure.
Secondly, a phase-locked loop and a Central Processing Unit (CPU) are used to perform clock detection and automatic inversion, as shown in fig. 2. Clock signals sent by two or more paths of clock source devices are respectively input into respective phase-locked loop circuits; the phase-locked loop circuit is used for phase-locking the clock signal, if the clock signal is not locked, the fault of the clock signal is judged, and the CPU outputs a control signal to the multi-path selector and switches to the other normal path of clock signal; the multiplexer outputs a clock signal which works normally according to the control signal.
In the process of implementing the invention, the inventor finds that at least the following problems exist in the prior art:
first, the design of the existing clock detection and automatic switching system is too complex, and the price of the adopted devices is higher, resulting in higher cost of the whole clock system.
Secondly, devices adopted by the existing clock detection and automatic switching system, such as a phase-locked loop, a programmable logic device or a CPU, have high failure rate, and the reliability of the clock system is reduced.
Third, some devices, such as programmable logic devices or CPUs, require their own operating clock, and their clock sources also have reliability problems, which also results in a reduced reliability of the clock system.
Disclosure of Invention
In order to simplify a clock system and improve reliability of the clock system, embodiments of the present invention provide a method, a system, and a detection circuit for clock detection and automatic switching. The technical scheme is as follows:
a method of clock detection and automatic switching, the method comprising:
receiving a clock signal, and performing blocking processing on the clock signal to obtain an alternating current signal subjected to blocking processing;
rectifying the alternating current signal subjected to the blocking processing, or rectifying and amplifying the alternating current signal to obtain a pulsating direct current signal;
generating control information according to the pulsating direct current signal;
controlling a multiplexer to output a normal clock signal according to the control information;
the generating of the control information according to the pulsating direct current signal and the controlling of the multiplexer to output a normal clock signal according to the control information specifically include:
smoothing the pulsating direct current signal to generate a constant and stable direct current signal, and controlling the multiplexer to output a normal clock signal according to the constant and stable direct current signal; or,
smoothing the pulsating direct current signal to generate a constant and stable direct current signal, performing level conditioning on the constant and stable direct current signal to generate a digital logic level signal, and controlling the multiplexer to output a normal clock signal according to the digital logic level signal; or,
and smoothing the pulsating direct current signal to generate a constant and stable direct current signal, performing level conditioning on the constant and stable direct current signal to generate the digital logic level signal, encoding the digital logic level signal to generate encoding information, and controlling the multiplexer to output a normal clock signal according to the encoding information.
A system for clock detection and automatic switching, the system comprising:
the clock source device is used for generating and outputting a clock signal;
the detection and control circuit is used for receiving the clock signal and carrying out blocking processing on the clock signal to obtain an alternating current signal subjected to blocking processing; rectifying the alternating current signal subjected to the blocking processing, or rectifying and amplifying the alternating current signal to obtain a pulsating direct current signal; generating control information according to the pulsating direct current signal;
the multiplexer is used for outputting a normal clock signal according to the control information;
wherein, the detection and control circuit specifically includes: a filter circuit, a rectifier circuit and a smoothing circuit; or specifically comprises the following steps: the device comprises a filter circuit, a rectifying circuit, a smoothing processing circuit and a level conditioning circuit; or specifically comprises the following steps: the device comprises a filter circuit, a rectifying circuit, a smoothing processing circuit, a level conditioning circuit and a digital coding circuit;
the filter circuit is used for carrying out blocking or band-pass processing on the input clock signal to obtain an alternating current signal subjected to blocking or band-pass processing;
the rectification circuit is used for rectifying the alternating current signals subjected to the blocking or band-pass processing or rectifying and amplifying the alternating current signals to obtain pulsating direct current signals;
the smoothing circuit is used for smoothing the pulsating direct current signal to generate a constant and stable direct current signal;
the level conditioning circuit is used for performing level conditioning on the constant and stable direct current signal to generate the digital logic level signal;
the digital coding circuit is used for coding the digital logic level signal to generate coding information;
when the detection and control circuit comprises the filter circuit, the rectifying circuit and the smoothing circuit, the multiplexer is used for outputting a normal clock signal according to the constant and stable direct current signal; or,
when the detection and control circuit comprises the filter circuit, the rectifying circuit, the smoothing processing circuit and the level conditioning circuit, the multiplexer is used for outputting a normal clock signal according to the digital logic level signal; or,
when the detection and control circuit comprises the filter circuit, the rectifying circuit, the smoothing processing circuit, the level conditioning circuit and the digital coding circuit, the multiplexer is used for outputting a normal clock signal according to the coding information.
The embodiment of the invention simplifies the clock system and reduces the cost of the clock system by adopting a small number of simple and low-cost electronic devices; by adopting a simplified design, the high reliability characteristic of a simple electronic device is fully utilized, and the reliability of the clock system is improved.
Drawings
FIG. 1 is a schematic diagram of a prior art system for clock detection and automatic switching using programmable logic chips;
FIG. 2 is a schematic diagram of a prior art clock detection and automatic switching system using a phase locked loop plus a CPU;
fig. 3 is a schematic diagram of a clock detection and automatic switching circuit according to an embodiment of the present invention;
fig. 4 is a flowchart of a method for clock detection and automatic switching according to an embodiment of the present invention;
FIG. 5 is a schematic diagram of a clock detection circuit according to an embodiment of the present invention;
FIG. 6 is a flow chart of a method for detecting a clock signal according to an embodiment of the present invention;
FIG. 7 is a schematic diagram of another clock detection circuit according to an embodiment of the present invention;
fig. 8 is a schematic diagram of a complete clock detection and automatic switching circuit provided in an embodiment of the present invention;
fig. 9 is a schematic diagram of a system for clock detection and automatic switching according to an embodiment of the present invention;
fig. 10 is a schematic diagram of a clock detection circuit according to an embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, embodiments of the present invention will be described in detail with reference to the accompanying drawings.
The embodiment of the invention provides a method for detecting and automatically switching a clock, which simplifies a clock system and reduces the cost of the clock system by adopting simple and low-cost electronic devices, fully utilizes the high reliability of the simple electronic devices and improves the reliability of the clock system. Referring to fig. 3 and 4, the specific steps of this embodiment are as follows:
step 101: the clock source device sends out a clock signal to provide a working clock for the clock system.
In fig. 3, there are n (n is an integer greater than 1) clock signals, and each clock signal corresponds to one clock source device and one clock detection circuit. The clock source devices used by different clock systems may be different, and common clock source devices include crystal oscillators, crystals, oscillators, and the like. The clock source devices can be two or more, the more the backup clock source devices are, the higher the reliability of the clock system is. According to the relevant knowledge of probability theory, the probability that two small-probability events occur simultaneously is zero, so that the reliability of two paths of clock source devices is high, and the contribution of the multipath clock source devices to the reliability of a clock system is very small, so that the system with two paths of clock source devices is mainly explained in the embodiment.
Step 102: the clock detection circuit detects the clock signal and outputs a digital logic level signal identifying a clock fault.
In this embodiment, the clock signal output by the clock source device conforms to the TTL (Transistor-Transistor Logic) level standard. Referring to fig. 5 and 6, the specific steps of the clock detection circuit for detecting the clock signal are as follows:
step 102A: the input clock signal is subjected to direct current blocking processing by a capacitor C1, a direct current component in the clock signal is removed, an alternating current signal subjected to direct current blocking processing is obtained, and the obtained alternating current signal is input to a base electrode of an NPN (Negative-Positive-Negative) transistor Q1 through a resistor R1.
Typically, the failure of a clock source device is manifested by the output of a normally high or a normally low signal. The dc blocking process is to remove the dc component in the clock signal, so that the normally high or low level signal outputted by the clock source device when failing cannot pass through the dc blocking circuit, and therefore the invalid clock signal cannot be detected and identified. Instead, the valid clock signal can be detected and identified by the dc blocking circuit. In addition, in rare cases, the failure of the clock source device is represented by a change in the frequency of the output clock signal, which is higher or lower than the expected frequency, and the energy higher or lower than the expected frequency can be removed by the band-pass filter circuit. Since this is usually rare, a general band-pass filter circuit can be used as an optional circuit of the clock detection circuit.
In addition, since the collector current of the transistor Q1 is greatly changed due to the slight change of the base current, the resistor R1 is used for restraining the base current; the resistor R2 mainly functions to keep the transistor Q1 stable and in an off state when no clock signal is input, and prevent false detection due to interference.
Step 102B: the transistor Q1 rectifies and amplifies the dc-blocked ac signal to obtain a pulsating dc signal, and inputs the pulsating dc signal to the pi-type filter.
The emitter of the transistor Q1 is saturated and turned on under the action of the positive half cycle of the base signal, the negative half cycle is turned off in reverse phase, the current turned on at the transistor Q1 builds up voltage on the resistor R3, and a pulsating direct current signal with only the positive half cycle is obtained.
Step 102C: the pi filter smoothes the pulsating direct current signal to obtain a constant direct current signal, and then inputs the constant direct current signal to a Metal Oxide Semiconductor (MOS) transistor Q2.
The pulsating direct current signal is further smoothed by a pi-type filter consisting of a resistor R4 and capacitors C3 and C4, and the output signal is a constant and stable direct current signal.
In practical applications, besides pi-type filter, other filters may be used for smoothing, such as: passive RC low pass filters, active low pass filters, etc.
Step 102D: the MOS transistor Q2 performs level conditioning on the constant dc signal, and outputs a digital logic level signal for identifying a clock fault.
In step 102C, if the amplification factor of the transistor Q1 and the power supply voltage used are high (for example, 8V), the constant dc signal obtained after the smoothing processing by the pi-type filter reaches the TTL level standard, then no level conditioning may be performed. On the contrary, the steady dc signal needs to be further amplified and conditioned, so the MOS transistor Q2 is adopted as the last stage in step 102D, and the steady dc signal obtained in step 102C is amplified and conditioned to generate a digital logic level signal. The on voltage of the MOS transistor Q2 should be lower than the voltage output by the transistor Q1, so the high and low voltages output by the transistor Q1 respectively control the on and off of the MOS transistor Q2, that is, the transistor Q1 and the MOS transistor Q2 are turned on, and a high level signal is output to indicate that the clock signal has no fault; when no clock signal is input, the transistor Q1 and the MOS transistor Q2 are turned off, and a low level signal is output, which indicates that the clock signal has a fault.
In addition, for the detection of the clock signal, a diode rectification mode can be adopted to rectify the alternating current signal subjected to the blocking processing to obtain a pulsating direct current signal, and then level conditioning is carried out. Because the diode has no amplification function, the MOS tube is used for amplification conditioning. Fig. 7 is an example of diode rectification instead of a transistor. The input clock signal is processed by capacitor blocking, and the DC component in the clock signal is removed to obtain the AC signal processed by blocking. And inputting the AC signal subjected to the DC blocking treatment into a rectifier bridge for rectification treatment to obtain a pulsating DC signal. Since the input clock signal is a differential signal, the rectifier bridge here is a full-wave rectifier bridge, and if the input clock signal is a single-ended input clock signal, a half-wave rectifier bridge may be used. Smoothing the pulsating direct current signal to obtain a constant and stable direct current signal; a steady direct current signal controls the conduction of the MOS tube; the MOS tube amplifies and conditions the constant and stable direct current signal and outputs a high level signal. On the contrary, if no clock signal is input, the rectifier bridge does not output, the MOS tube is cut off, and a low level signal is output. The MOS tube can be replaced by a transistor.
It should be noted that the clock detection circuit may be modified according to the frequency and level of the clock signal. For example, the clock signal output by the clock source device is in a Low-Voltage Positive-Emitter Coupled Logic (LVPECL) level standard case, and since the swing of the LVPECL level signal is small, the minimum swing is 300mV, and the maximum is not more than 1V, if the transistor is not selected properly, the transistor cannot be turned on in the case of the small swing. A simple solution is to convert the clock signal conforming to LVPECL level standard into the clock signal conforming to TTL level standard through a level conversion circuit, and then to detect the clock signal. Then, dc blocking processing, rectification and amplification processing, smoothing processing, and level conditioning are performed on the input clock signal, and the specific steps are similar to the principles adopted in steps 102A to 102D in this embodiment and are not described again. That is, if the clock signal outputted from the clock source device conforms to one level standard (e.g., LVPECL level standard), the clock detection circuit is designed to detect the clock signal conforming to another level standard (e.g., TTL level standard), but a level conversion circuit may be added to convert the inputted clock signal into a clock signal conforming to another level standard (e.g., TTL level standard).
Step 103: the digital coding circuit codes the digital logic level signal output by the clock detection circuit to generate coding information, and controls the multiplexer to select and output a normal clock signal according to the coding information.
For two paths of clock signals, if one path of clock signal has a fault, only the other path of clock signal can be selectively output, so that the digital coding circuit can be omitted. At this time, one path of clock detection circuit can generate a constant direct current signal or a digital logic level signal, and directly control the multiplexer to output a clock signal according to the constant direct current signal or the digital logic level signal, and the other path of clock detection circuit can also perform detection and output a signal alarm, for example, to light a fault indicator lamp or inform a main control system for repair and processing. For the detection output of three or more clock signals, a digital coding circuit is required to perform coding processing to generate coding information, and a multiplexer is controlled to select and output a normal clock signal according to the coding information. For example, the encoding table obtained by encoding the detection outputs of the three clock signals is shown in table 1, where 1 indicates that the detected clock signal is normal, and 0 indicates that the detected clock signal is abnormal or invalid.
TABLE 1
For example, when the a-way clock signal detection output is 1, the B-way clock signal detection output is 0, and the C-way clock signal detection output is 1, the a-way clock signal output is selected. And when the detection output of the clock signal of the A path is 0, the detection output of the clock signal of the B path is 1 and the detection output of the clock signal of the C path is 0, the clock signal of the B path is selected to be output.
Step 104: the multiplexer selects the normal clock signal to output under the control of the digital coding circuit, namely, the automatic switching process is completed.
For the clock signals conforming to different level standards, different multiplexers may be selected, for example, for the multiplexer for the clock signal conforming to the low frequency TTL level standard, an alternative multiplexer such as model 74LS157/74HC157/74LVC157 may be used, or other integrated devices such as single-pole double-throw switches may be used.
An example of a complete clock detection and automatic switching system is shown in fig. 8, in which only one clock detection circuit corresponding to the crystal oscillator 2 is shown, and the other clock detection circuit corresponding to the crystal oscillator 1 is completely the same as the clock detection circuit corresponding to the clock source crystal oscillator 2, and is omitted in the figure and not shown. As can be seen from the figure, the clock detection circuit detects the clock signal output by the crystal oscillator 2, and the crystal oscillator 1 is a backup clock source device. When the clock detection circuit detects that the clock signal output by the crystal oscillator 2 is normal, the clock detection circuit outputs a high-level signal to control the selection end of the multiplexer, and the multiplexer selects and outputs the clock signal output by the crystal oscillator 2. When the clock source crystal oscillator 2 fails, the clock detection circuit outputs a low level signal, and the multiplexer selects and outputs the clock signal of the crystal oscillator 1.
The clock detection circuit in this embodiment is designed in such a way that the clock signal output by the clock source device conforms to the TTL level standard, and in practical applications, the clock detection circuit may also be designed in such a way that the clock signal output by the clock source device conforms to other level standards, and the basic principle of detection of the clock detection circuit in this embodiment is basically the same as the basic principle of detection of the clock signal output by the clock source device conforming to the TTL level standard, and thus, details are not repeated.
The devices used in this embodiment, transistors, resistors and capacitors, are low in cost; and the failure rate of the transistor, the MOS tube and the multiplexer is less than 1FITs, the failure rate of the capacitor and the resistor is lower and can be ignored, so that the total failure rate of the clock detection and automatic switching system can be less than 2 FITs. Therefore, the technical scheme of the embodiment of the invention can simplify the clock system, reduce the cost of the clock system and improve the reliability of the clock system.
An embodiment of the present invention further provides a system for clock detection and automatic switching, referring to fig. 9, where the system includes:
the clock source device is used for generating and outputting a clock signal;
the detection and control circuit is used for receiving a clock signal and carrying out blocking/band-pass processing on the clock signal to obtain an alternating current signal subjected to blocking/band-pass processing;
rectifying the alternating current signal subjected to the blocking/band-pass processing or rectifying and amplifying the alternating current signal to obtain a pulsating direct current signal;
generating control information according to the pulsating direct current signal;
and the multiplexer is used for outputting a normal clock signal according to the control information.
Wherein, detection and control circuit specifically includes:
the filter circuit is used for carrying out blocking/band-pass processing on an input clock signal to obtain an alternating current signal subjected to the blocking/band-pass processing;
the rectification circuit is used for rectifying the alternating current signals subjected to the blocking/band-pass processing or rectifying and amplifying the alternating current signals to obtain pulsating direct current signals;
and the smoothing circuit is used for smoothing the pulsating direct current signal to generate a constant and stable direct current signal. The constant and stable direct current signal is control information, and the multi-path selector is used for outputting a normal clock signal according to the constant and stable direct current signal.
Further, the detection and control circuit further comprises:
and the level conditioning circuit is used for carrying out level conditioning on the constant and stable direct current signal to generate a digital logic level signal. The digital logic level signal is control information, and the multiplexer is used for outputting a normal clock signal according to the digital logic level signal.
Still further, the detection circuit further comprises:
and the digital coding circuit is used for coding the digital logic level signal to generate coding information. The coding information is control information, and the multiplexer is used for outputting a normal clock signal according to the coding information.
It should be noted that the system further includes:
and the level conversion circuit is used for performing level conversion on the clock signal output by the clock source device before the detection and control circuit receives the clock signal so as to enable the clock signal to meet the detection parameter requirement.
An embodiment of the present invention further provides a clock detection circuit, referring to fig. 10, where the clock detection circuit includes:
the filter circuit is used for carrying out blocking/band-pass processing on the clock signal to obtain an alternating current signal subjected to the blocking/band-pass processing;
the rectification circuit is used for rectifying the alternating current signals subjected to the blocking/band-pass processing or rectifying and amplifying the alternating current signals to obtain pulsating direct current signals;
and the smoothing circuit is used for smoothing the pulsating direct current signal to generate a constant and stable direct current signal.
Further, the clock detection circuit further includes:
and the level conditioning circuit is used for carrying out level conditioning on the constant and stable direct current signal to generate a digital logic level signal.
According to the technical scheme of the embodiment of the invention, the clock system is simplified, the cost of the clock system is reduced and the reliability of the clock system is improved by adopting the simple and reliable electronic device.
The above description is only for the purpose of illustrating the preferred embodiments of the present invention and is not to be construed as limiting the invention, and any modifications, equivalents, improvements and the like that fall within the spirit and principle of the present invention are intended to be included therein.
Claims (4)
1. A method for clock detection and automatic switching is characterized in that the method comprises the following steps:
receiving a clock signal, and performing blocking processing on the clock signal to obtain an alternating current signal subjected to blocking processing;
rectifying the alternating current signal subjected to the blocking processing, or rectifying and amplifying the alternating current signal to obtain a pulsating direct current signal;
generating control information according to the pulsating direct current signal;
controlling a multiplexer to output a normal clock signal according to the control information;
the generating of the control information according to the pulsating direct current signal and the controlling of the multiplexer to output a normal clock signal according to the control information specifically include:
smoothing the pulsating direct current signal to generate a constant and stable direct current signal, and controlling the multiplexer to output a normal clock signal according to the constant and stable direct current signal; or,
smoothing the pulsating direct current signal to generate a constant and stable direct current signal, performing level conditioning on the constant and stable direct current signal to generate a digital logic level signal, and controlling the multiplexer to output a normal clock signal according to the digital logic level signal; or,
and smoothing the pulsating direct current signal to generate a constant and stable direct current signal, performing level conditioning on the constant and stable direct current signal to generate the digital logic level signal, encoding the digital logic level signal to generate encoding information, and controlling the multiplexer to output a normal clock signal according to the encoding information.
2. The method of clock signal detection and automatic switching as claimed in claim 1, wherein before said step of receiving a clock signal, said method further comprises:
and carrying out level conversion on a clock signal to be detected output by a clock source device, and converting the clock signal to be detected into the clock signal meeting the detection parameter requirement.
3. A system for clock detection and automatic switching, the system comprising:
the clock source device is used for generating and outputting a clock signal;
the detection and control circuit is used for receiving the clock signal and carrying out blocking processing on the clock signal to obtain an alternating current signal subjected to blocking processing; rectifying the alternating current signal subjected to the blocking processing, or rectifying and amplifying the alternating current signal to obtain a pulsating direct current signal; generating control information according to the pulsating direct current signal;
the multiplexer is used for outputting a normal clock signal according to the control information;
wherein, the detection and control circuit specifically includes: a filter circuit, a rectifier circuit and a smoothing circuit; or specifically comprises the following steps: the device comprises a filter circuit, a rectifying circuit, a smoothing processing circuit and a level conditioning circuit; or specifically comprises the following steps: the device comprises a filter circuit, a rectifying circuit, a smoothing processing circuit, a level conditioning circuit and a digital coding circuit;
the filter circuit is used for carrying out blocking or band-pass processing on the input clock signal to obtain an alternating current signal subjected to blocking or band-pass processing;
the rectification circuit is used for rectifying the alternating current signals subjected to the blocking or band-pass processing or rectifying and amplifying the alternating current signals to obtain pulsating direct current signals;
the smoothing circuit is used for smoothing the pulsating direct current signal to generate a constant and stable direct current signal;
the level conditioning circuit is used for performing level conditioning on the constant and stable direct current signal to generate the digital logic level signal;
the digital coding circuit is used for coding the digital logic level signal to generate coding information;
when the detection and control circuit comprises the filter circuit, the rectifying circuit and the smoothing circuit, the multiplexer is used for outputting a normal clock signal according to the constant and stable direct current signal; or,
when the detection and control circuit comprises the filter circuit, the rectifying circuit, the smoothing processing circuit and the level conditioning circuit, the multiplexer is used for outputting a normal clock signal according to the digital logic level signal; or,
when the detection and control circuit comprises the filter circuit, the rectifying circuit, the smoothing processing circuit, the level conditioning circuit and the digital coding circuit, the multiplexer is used for outputting a normal clock signal according to the coding information.
4. The clock detection circuit and automatic switching system of claim 3, wherein the system further comprises:
and the level conversion circuit is used for carrying out level conversion on the clock signal output by the clock source device.
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| CN102694616B (en) * | 2012-06-11 | 2014-11-26 | 福建星网锐捷网络有限公司 | Clock detection circuit, clock circuit and clock exception detection method |
| CN105790873B (en) * | 2014-12-26 | 2019-06-21 | 中兴通讯股份有限公司 | Keep the clockwork and method of clock |
| CN106301744B (en) * | 2015-05-14 | 2020-04-28 | 中兴通讯股份有限公司 | Clock protection switching method and device for clock board |
| CN111418158B (en) * | 2017-12-08 | 2024-04-09 | 深圳开阳电子股份有限公司 | Clock system, electronic device and processing method |
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| CN1302121A (en) * | 1999-12-29 | 2001-07-04 | 上海贝尔有限公司 | Clock signal switching and selecting method in synchronous clock supply system and its device |
| CN1428965A (en) * | 2001-12-25 | 2003-07-09 | 深圳市中兴通讯股份有限公司上海第二研究所 | Method for correcting clock ageing of telecommunication equipment |
| CN1925329A (en) * | 2006-08-08 | 2007-03-07 | 华为技术有限公司 | Method and device for clock detection |
| CN1960180A (en) * | 2005-10-31 | 2007-05-09 | 中兴通讯股份有限公司 | Clock signal detection circuit |
| CN101018052A (en) * | 2006-02-10 | 2007-08-15 | 凌阳科技股份有限公司 | A clock frequency detection and conversion device |
| CN101106388A (en) * | 2006-07-12 | 2008-01-16 | 精工爱普生株式会社 | Reception circuit, radio-controlled timepiece, and reception circuit control method |
-
2008
- 2008-03-27 CN CN200810084161A patent/CN101252405B/en not_active Expired - Fee Related
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1302121A (en) * | 1999-12-29 | 2001-07-04 | 上海贝尔有限公司 | Clock signal switching and selecting method in synchronous clock supply system and its device |
| CN1428965A (en) * | 2001-12-25 | 2003-07-09 | 深圳市中兴通讯股份有限公司上海第二研究所 | Method for correcting clock ageing of telecommunication equipment |
| CN1960180A (en) * | 2005-10-31 | 2007-05-09 | 中兴通讯股份有限公司 | Clock signal detection circuit |
| CN101018052A (en) * | 2006-02-10 | 2007-08-15 | 凌阳科技股份有限公司 | A clock frequency detection and conversion device |
| CN101106388A (en) * | 2006-07-12 | 2008-01-16 | 精工爱普生株式会社 | Reception circuit, radio-controlled timepiece, and reception circuit control method |
| CN1925329A (en) * | 2006-08-08 | 2007-03-07 | 华为技术有限公司 | Method and device for clock detection |
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| CN101252405A (en) | 2008-08-27 |
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