CN101207403A - Broadband RF front-end with high dynamic range in the medium and short wave bands - Google Patents
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Abstract
中短波频段高动态范围宽带射频前端,本发明涉及中短波频段扩频信号接收系统的宽带射频前端。它克服了现有结构的射频前端噪声系数高、动态范围小和镜像抑制低的缺点。该射频前端采用两级变频、低中频输出结构,射频信号经过预选放大模块、变频模块、可变增益放大模块以及中频放大模块后进入到中频基带信号处理部分,中频基带信号处理部分在时钟信号的驱动下做数字解调。其中可变增益放大模块采用数字方式实现,由三路数字可变增益放大模块来保证系统的动态要求。变频模块的两路本振信号和提供给数字基带处理部分的时钟信号采用DDS+PLL方式产生,由PLL将晶振输出信号倍频,经缓冲驱动后输入到三路DDS,实现信号输出。
The invention relates to a wideband radio frequency front end with a high dynamic range in the middle and short wave bands, and the invention relates to a wide band radio frequency front end of a spread spectrum signal receiving system in the middle and short wave bands. It overcomes the disadvantages of high noise figure, small dynamic range and low image suppression of the existing radio frequency front end. The RF front-end adopts a two-stage frequency conversion and low intermediate frequency output structure. The RF signal enters the intermediate frequency baseband signal processing part after passing through the preselected amplifier module, frequency conversion module, variable gain amplifier module and intermediate frequency amplifier module. The intermediate frequency baseband signal processing part is in the clock signal Driven to do digital demodulation. Among them, the variable gain amplifier module is implemented in a digital way, and the dynamic requirements of the system are guaranteed by the three-way digital variable gain amplifier module. The two-way local oscillator signal of the frequency conversion module and the clock signal provided to the digital baseband processing part are generated by DDS+PLL. The PLL multiplies the frequency of the output signal of the crystal oscillator. After being buffered and driven, it is input to the three-way DDS to realize the signal output.
Description
技术领域technical field
本发明涉及中短波频段扩频信号接收系统的宽带射频前端。The invention relates to a wideband radio frequency front end of a medium and short wave band spread spectrum signal receiving system.
背景技术Background technique
中短波频段一般指0.5MHz-30MHz的频段,中短波通信利用电离层作为传输媒质,传输距离可达到数千公里。由于中短波通信具有抗毁性强,传输距离远的特点,所以其应用十分广泛。目前,中短波频段没有被高动态范围的通信系统(如移动通信)所应用。扩频通信系统是指待传输信息的频谱用某个特定的扩频函数扩展后成为宽频带信号,送入信道中传输,再利用相应手段将其压缩从而得到传输信息的通信系统。由于扩频信号的频谱远远大于原始信息的带宽,所以经过扩展频谱后的信号往往淹没在了信道噪声以下,很难被监测。并且扩频函数或扩频序列一般具有伪随机特性,所以扩频通信系统具有极强的保密性。而射频前端是中短波扩频系统的一个重要环节,直接影响到扩频系统的作用距离、抗干扰能力和系统带宽。The medium and short wave frequency band generally refers to the frequency band of 0.5MHz-30MHz. The medium and short wave communication uses the ionosphere as the transmission medium, and the transmission distance can reach thousands of kilometers. Because medium and short wave communication has the characteristics of strong invulnerability and long transmission distance, it is widely used. Currently, medium and short wave frequency bands are not used by high dynamic range communication systems (such as mobile communication). The spread spectrum communication system refers to the communication system in which the spectrum of the information to be transmitted is expanded by a specific spread spectrum function to become a broadband signal, sent to the channel for transmission, and then compressed by corresponding means to obtain the transmitted information. Since the spectrum of the spread spectrum signal is much larger than the bandwidth of the original information, the signal after the spread spectrum is often submerged under the channel noise, making it difficult to be monitored. Moreover, the spread spectrum function or spread spectrum sequence generally has pseudo-random characteristics, so the spread spectrum communication system has extremely strong confidentiality. The radio frequency front-end is an important part of the medium and short wave spread spectrum system, which directly affects the operating distance, anti-interference ability and system bandwidth of the spread spectrum system.
现代接收机体系结构一般包括:镜像抑制接收机结构、零中频接收机结构、低中频接收机结构以及基于软件无线电的数字中频接收机结构。以上几种结构都有各自的优缺点:镜像抑制接收机结构包括Hartley镜像抑制结构和Weaver镜像抑制结构,理论上都可以完全消除镜像响应与镜像噪声,但是由于Hartley镜像抑制结构需要采用固定移相器,而宽带的固定移相器是很难实现的,因此不适合应用于宽带接收机。而Weaver镜像抑制结构相对复杂,两路信道的增益与相位失配度相对较大,实际使用中随着失配增大,镜像抑制度会降低。零中频接收机结构是抑制镜像干扰的另一种有效结构,它将射频信号直接变换为基带信号,因此可以完全消除镜像干扰。但也正是由于这种结构的特点,直流漂移和低频噪声的影响是不可避免的,而且本振泄漏或者低噪声放大器的辐射和泄漏都正好被下变频到有用信号上,从而影响系统的整体性能。为了消除零中频接收机结构的各种不利影响,可以将中频选择在较低但非零的频率上,这就是低中频接收机结构。但这种结构又会带来镜像干扰,所以一般的低中频接收机结构采用正交的镜像抑制混频器和多相滤波器,这两者都是利用信号和镜像干扰经过混频之后存在的相位差异来区分信号和干扰的,但这种结构较为复杂,实现有一定难度。Modern receiver architecture generally includes: image suppression receiver structure, zero-IF receiver structure, low-IF receiver structure and digital IF receiver structure based on software radio. The above structures have their own advantages and disadvantages: the image suppression receiver structure includes the Hartley image suppression structure and the Weaver image suppression structure, which can completely eliminate the image response and image noise in theory, but because the Hartley image suppression structure requires a fixed phase shift device, and a broadband fixed phase shifter is difficult to implement, so it is not suitable for wideband receivers. The Weaver image suppression structure is relatively complex, and the gain and phase mismatch of the two channels is relatively large. In actual use, the image suppression will decrease as the mismatch increases. The zero-IF receiver structure is another effective structure for suppressing image interference, which directly converts radio frequency signals into baseband signals, so image interference can be completely eliminated. But it is precisely because of the characteristics of this structure that the influence of DC drift and low-frequency noise is inevitable, and the leakage of the local oscillator or the radiation and leakage of the low-noise amplifier are just down-converted to the useful signal, thus affecting the overall system performance. In order to eliminate various adverse effects of the zero-IF receiver structure, the IF can be selected at a lower but non-zero frequency, which is the low-IF receiver structure. However, this structure will bring image interference, so the general low-IF receiver structure uses an orthogonal image rejection mixer and polyphase filter, both of which exist after mixing the signal and image interference. The phase difference is used to distinguish the signal from the interference, but this kind of structure is relatively complicated and difficult to realize.
随着数字信号处理技术的不断发展,基于软件无线电的数字中频接收机结构应运而生,一般的软件无线电的数字中频接收机结构在A/D变换之前完成滤波、放大、增益控制及变频等功能,将射频信号变换到中频。A/D变换后经过专用的数字信号处理器件进行数字下变频处理,降低数据流速率,将IF(中频)数字信号变换成基带数字信号,再送到通用DSP进行处理,实现对各种数据率相对较低的数字基带信号处理,完成各种抗干扰、抗多径、自适应均衡算法等的实现;以及纠错FEC、反交织、解密等功能。虽然这种结构具有良好的通用性和开放性,但对于射频前端的要求很高:要求低噪声系数、高动态范围、高镜像抑制及高线性度等等。目前结构的射频前端难以达到上述要求。With the continuous development of digital signal processing technology, the structure of digital IF receiver based on software radio came into being. The structure of digital IF receiver of general software radio completes the functions of filtering, amplification, gain control and frequency conversion before A/D conversion. , to convert the RF signal to an intermediate frequency. After A/D conversion, digital down-conversion processing is performed by a dedicated digital signal processing device to reduce the data flow rate, convert the IF (intermediate frequency) digital signal into a baseband digital signal, and then send it to a general-purpose DSP for processing, so as to achieve relative data rates for various data rates. Low digital baseband signal processing, complete the realization of various anti-interference, anti-multipath, adaptive equalization algorithms, etc.; and functions such as error correction FEC, anti-interleaving, and decryption. Although this structure has good versatility and openness, it has high requirements for the RF front-end: low noise figure, high dynamic range, high image rejection and high linearity, etc. The RF front end of the current structure is difficult to meet the above requirements.
发明内容Contents of the invention
本发明的目的是提供一种中短波频段高动态范围宽带射频前端,以克服现有结构的射频前端噪声系数高、动态范围小和镜像抑制低的缺点。它由预选放大模块3、第一级数字可变增益放大模块4、第一级变频模块5、第二级数字可变增益放大模块6、第二级变频模块7、第三级数字可变增益放大模块8和中频放大模块9组成,预选放大模块3的信号输出端连接第一级数字可变增益放大模块4的信号输入端,第一级数字可变增益放大模块4的信号输出端连接第一级变频模块5的信号输入端,第一级变频模块5的信号输出端连接第二级数字可变增益放大模块6的信号输入端,第二级数字可变增益放大模块6的信号输出端连接第二级变频模块7的信号输入端,第二级变频模块7的信号输出端连接第三级数字可变增益放大模块8的信号输入端,第三级数字可变增益放大模块8的信号输出端连接中频放大模块9的信号输入端。The purpose of the present invention is to provide a wideband radio frequency front-end with high dynamic range in medium and short wave bands, so as to overcome the shortcomings of high noise figure, small dynamic range and low image rejection in the radio frequency front-end of the existing structure. It consists of a
工作时,预选放大模块3的输入端通过其内部的低噪声放大器3-1连接到天线1上,以接收射频信号。中频放大模块9的输出端连接基带信号处理模块10的输入端。射频信号从天线1进入到射频前端,依次经过预选放大模块3、第一级可变增益放大模块4和第一级变频模块5后输出高中频信号,高中频信号再经过第二级可变增益放大模块6和第二级变频模块7后输出低中频信号,再经过第三级可变增益放大模块8和中频放大模块9后进入到基带处理部分。射频前端通过两级变频将射频信号下变频为中频信号。能实现100dB以上的动态范围;预选放大模块的前置低噪声放大器具有高增益和低噪声系数,可以有效地降低前端的噪声系数;两级变频可以实现较高的镜像抑制,同时可以满足弱信号输入时对增益的要求。本发明克服了现有结构的射频前端噪声系数高、动态范围小和镜像抑制低的缺点,具有较大推广价值。When working, the input terminal of the
附图说明Description of drawings
图1是本发明的结构示意图,图2是实施方式二的结构示意图,图3是第一级数字可变增益放大模块4的结构示意图,图4是基于DDS+PLL模式的本振信号发生器及基带数字时钟信号发生装置的结构示意图。Fig. 1 is a structural schematic diagram of the present invention, Fig. 2 is a structural schematic diagram of Embodiment 2, Fig. 3 is a structural schematic diagram of a first stage digital variable
具体实施方式Detailed ways
具体实施方式一:下面结合图1具体说明本实施方式。本实施方式由预选放大模块3、第一级数字可变增益放大模块4、第一级变频模块5、第二级数字可变增益放大模块6、第二级变频模块7、第三级数字可变增益放大模块8和中频放大模块9组成,预选放大模块3的信号输出端连接第一级数字可变增益放大模块4的信号输入端,第一级数字可变增益放大模块4的信号输出端连接第一级变频模块5的信号输入端,第一级变频模块5的信号输出端连接第二级数字可变增益放大模块6的信号输入端,第二级数字可变增益放大模块6的信号输出端连接第二级变频模块7的信号输入端,第二级变频模块7的信号输出端连接第三级数字可变增益放大模块8的信号输入端,第三级数字可变增益放大模块8的信号输出端连接中频放大模块9的信号输入端。Specific Embodiment 1: The present embodiment will be specifically described below with reference to FIG. 1 . This embodiment consists of a preselected
具体实施方式二:下面结合图1、2、3和4具体说明本实施方式。本实施方式与实施方式一的不同点是:预选放大模块3包括低噪声放大器3-1、预选滤波器3-2和射频放大器3-3,低噪声放大器3-1的输出端连接预选滤波器3-2的输入端,预选滤波器3-2的输出端连接射频放大器3-3的输入端。预选放大模块3是射频信号进入前端的第一级,起到了滤除干扰、降低系统噪声系数、放大微弱信号的作用。预选放大模块3的增益为18dB左右。根据级联网络噪声系数计算公式,设级联网络第n级的放大倍数为Gn,噪声系数为Fn,级联网络的噪声系数为FΣ,由公式(1)可知,网络中前级的放大倍数和噪声系数是影响系统噪声系Specific Embodiment 2: The present embodiment will be specifically described below in conjunction with FIGS. 1 , 2 , 3 and 4 . The difference between this embodiment and Embodiment 1 is that the
数的关键因素,即前级放大倍数越大、噪声系数越小则系统的噪声系数越小。因此预选放大模块的参数设计直接影响到整个系统的性能。低噪声放大器3-1有着较低的噪声系数和较高的放大倍数,符合级联网络的设计原则。预选滤波器的插入损耗也是影响射频前端噪声系数的关键因素,所以可以适当地放宽带宽来减小滤波器的插损。但是预选滤波器又起着抑制镜像频率的作用,所以其带宽又不可以过宽,需要采取适中的方式来同时满足两者的要求。本实施方式采用5阶契比雪夫LC带通滤波器,带宽放宽到信号带宽的1.5倍,可以实现插损小于1.5dB,镜像抑制达到80dB。The key factor of the number, that is, the larger the preamplification factor and the smaller the noise figure, the smaller the noise figure of the system. Therefore, the parameter design of the preselection amplifier module directly affects the performance of the whole system. Low noise amplifier 3-1 has a lower noise figure and a higher amplification factor, which is in line with the design principles of cascaded networks. The insertion loss of the preselection filter is also a key factor affecting the noise figure of the RF front-end, so the bandwidth can be appropriately widened to reduce the insertion loss of the filter. However, the pre-selection filter plays a role in suppressing the image frequency, so its bandwidth cannot be too wide, and a moderate method needs to be adopted to meet the requirements of both. This embodiment adopts a 5th-order Chebyshev LC bandpass filter, and the bandwidth is widened to 1.5 times of the signal bandwidth, so that the insertion loss can be less than 1.5dB, and the image suppression can reach 80dB.
第一级数字可变增益放大模块4包括数字衰减器4-1、固定增益放大器4-2、数据采样模块4-3、由FPGA实现的控制模块4-4和π衰减器4-5,数字衰减器4-1的输入端连接预选放大模块3的输出端,数字衰减器4-1的输出端连接π衰减器4-5的输入端,π衰减器4-5的输出端连接固定增益放大器4-2的输入端,固定增益放大器4-2的输出端连接第一级变频模块5的输入端和数据采样模块4-3的输入端,数据采样模块4-3的输出端连接由FPGA实现的控制模块4-4的输入端,由FPGA实现的控制模块4-4的输出端连接数字衰减器4-1的反馈信号输入端。固定增益放大器4-2保证通道内信号的全增益,而数字衰减器4-1根据信号功率大小调节衰减量从而实现数字自动增益控制。信号的功率大小由FPGA控制数据采样模块4-3采样中频输出信号来确定,数据采样模块4-3采样到的信号在FPGA内部进行缓冲存储并做取模运算,取模输出的数据经过峰值检测的判断得到被采样信号的最大值,进而推算出信号的功率,信号的功率值与预先设置的阈值做比较得到增大衰减或减小衰减的控制量信号,从而控制衰减量的滑动。本实施方式采用逐次比较的方式,利用载波信号的周期性,在较少的比较次数中实现了一定精度的峰值比较。由于数据采样模块4-3采样的初始相位是随机的,在以固定频率采样时,不同的初始相位不可能都采样到峰值,但在一定的精度要求下可以在有限次的采样中得到精度允许的最大值。系统实际的采样率为信号频率的6.1倍,当比较次数为54次时,精度误差为0.037dBm,完全可以满足系统的要求。在实际工作中当功率在调节衰减的临界状态时,由于峰值检测的波动性和滞后性,所以其输出值可能会在某一点上下波动,使得第一级数字可变增益放大模块4的放大倍数不断地调整,无法保证稳定地工作;同时也为了避免放大器的饱和,本实施方式采用了多门限判决的方式:不同的门限对应不同的衰减滑动量,同时还要设定需要增大衰减时的门限值低,需要减小衰减时的门限值高。通过这种方式可以有效地控制超调量,减小波动。在实际的应用中接收到的扩频信号动态范围很大,所以系统采用三级自动增益控制,分别位于系统的射频段、一中频段和二中频段,这也是考虑到信号在一个频段一般只能保证40dB左右的增益,而将动态增益分配到不同的频段。第一级数字可变增益放大模块4的增益在0至30dB左右。第二级数字可变增益放大模块6和第三级数字可变增益放大模块8与第一级数字可变增益放大模块4的结构、增益倍数和工作原理相同。The first stage digital variable
第一级变频模块5包括混频器5-1、本振信号发生器5-2、低通滤波器5-3和放大器5-4,混频器5-1的两个输入端分别连接第一级数字可变增益放大模块4的输出端和本振信号发生器5-2的输出端,混频器5-1的输出端连接低通滤波器5-3的输入端,低通滤波器5-3的输出端连接放大器5-4的输入端。所述低通滤波器5-3选用晶体滤波器。放大器5-4的增益为22dB左右,第一级变频模块5的输出频率10.7MHz左右。The first stage
本振信号发生器5-2由晶体振荡器5-2-1、锁相环5-2-2、缓冲驱动器5-2-3、一路直接数字频率合成器5-2-4和一路低通滤波器5-2-5组成,晶体振荡器5-2-1的输出端连接锁相环5-2-2的输入端,锁相环5-2-2的输出端连接缓冲驱动器5-2-3的输入端,缓冲驱动器5-2-3的一个输出端连接一路直接数字频率合成器5-2-4的输入端,一路直接数字频率合成器5-2-4的输出端连接一路低通滤波器5-2-5的输入端。晶体振荡器5-2-1的频率10MHz,锁相环5-2-2的型号为ADF4001。一路直接数字频率合成器5-2-4的型号为AD9850,此二者都是美国AD公司的产品。本振信号发生器5-2的输出频率为13.5MHZ左右。The local oscillator signal generator 5-2 is composed of a crystal oscillator 5-2-1, a phase-locked loop 5-2-2, a buffer driver 5-2-3, a direct digital frequency synthesizer 5-2-4 and a low pass The filter 5-2-5 is composed, the output end of the crystal oscillator 5-2-1 is connected to the input end of the phase-locked loop 5-2-2, and the output end of the phase-locked loop 5-2-2 is connected to the buffer driver 5-2 -3 input, an output of the buffer driver 5-2-3 is connected to the input of a direct digital frequency synthesizer 5-2-4, and an output of the direct digital frequency synthesizer 5-2-4 is connected to a low Input to pass filter 5-2-5. The frequency of the crystal oscillator 5-2-1 is 10MHz, and the model of the phase-locked loop 5-2-2 is ADF4001. The model of one-way direct digital frequency synthesizer 5-2-4 is AD9850, both of which are products of American AD Company. The output frequency of the local oscillator signal generator 5-2 is about 13.5MHZ.
第二级变频模块7中用于混频的本振信号可以从本振信号发生器5-2的缓冲驱动器5-2-3的第二路输出端获得,即通过二路直接数字频率合成器7-16和二路低通滤波器7-17取得第二级变频模块7中用于混频的本振信号,该本振信号的频率11.5MHZ左右。还可以从缓冲驱动器5-2-3的第三路输出端,通过三路直接数字频率合成器16、三路低通滤波器17和电平驱动电路18获得后续基带信号的时钟信号。The local oscillator signal used for frequency mixing in the second-stage
由于系统要求频率的精度和稳定度都很高,因此本振信号发生器在器件选取上要求所选取的晶体振荡器有着与系统一致或更高的标准。而晶体振荡器输出频率的精度和稳定度越高则其输出频率就越低,为保证精度和稳定度的要求本实施方式所选取的晶体振荡器需要倍频才能达到本振信号的频率,所以本振信号发生器采用DDS+PLL(即直接数字频率合成+锁相环)模式。由于本振信号并不需要有很快的频率建立时间和很宽的频率输出范围,因此与传统的DDS+PLL模式即采用DDS信号激励PLL模式和DDS信号内插PLL模式不同,本发明采用PLL的输出信号作为DDS系统的参考时钟,DDS根据频率控制字输出本振信号。这种方式虽然并不能改善PLL所带来的相位噪声和DDS所带来的杂散,但是其结构简单,能够满足本振信号对频率和频率分辨率的要求,同时也不会恶化频率的精度和稳定度。本实施方式的射频前端采用两级变频,第一级变频模块实现上变频输出高中频信号,第二级变频模块将信号下变频到低中频输出。这种结构比抑制镜像干扰的Hartley结构和Weaver结构更简单,同时镜像干扰也完全可以满足系统要求。第一级变频模块5中的低通滤波器5-3采用晶体滤波器,由于预选放大模块3把带宽适当的增大了,因此变频后的信号必须严格保证带宽,否则会影响扩频增益。而晶体滤波器与普通的LC滤波器相比虽然有较大的插损,但有着更好的矩形系数和带外抑制,完全可以满足带宽和抑制干扰的要求。为了给数字基带处理部分提供一路稳定并且精确的时钟,与本振信号一样,时钟输出要求有较高的频率准确度和稳定度,因此可以利用本振信号源PLL的输出来驱动时钟模块的DDS,可以得到与本振信号一样的精度和稳定度。由于基带信号处理部分要求时钟具有CMOS电平,因此时钟的输出需要经过驱动电路以满足电平要求。Since the system requires high frequency accuracy and stability, the local oscillator signal generator requires the selected crystal oscillator to have the same or higher standard as the system. The higher the accuracy and stability of the crystal oscillator output frequency, the lower its output frequency. In order to ensure the accuracy and stability requirements, the crystal oscillator selected in this embodiment needs frequency multiplication to reach the frequency of the local oscillator signal, so The local oscillator signal generator adopts DDS+PLL (that is, direct digital frequency synthesis + phase-locked loop) mode. Since the local oscillator signal does not need to have a fast frequency settling time and a very wide frequency output range, it is different from the traditional DDS+PLL mode that uses DDS signal excitation PLL mode and DDS signal interpolation PLL mode. The output signal of the DDS is used as the reference clock of the DDS system, and the DDS outputs the local oscillator signal according to the frequency control word. Although this method cannot improve the phase noise brought by the PLL and the spurs brought by the DDS, its structure is simple and can meet the frequency and frequency resolution requirements of the local oscillator signal without deteriorating the frequency accuracy. and stability. The radio frequency front end of this embodiment adopts two-stage frequency conversion, the first-stage frequency conversion module implements up-conversion to output high-medium frequency signals, and the second-stage frequency conversion module down-converts signals to low-intermediate frequency output. This structure is simpler than the Hartley structure and Weaver structure that suppress the image interference, and the image interference can fully meet the system requirements. The low-pass filter 5-3 in the first-stage
中频放大模块9包括中频放大器9-1和抗混叠滤波器9-2,中频放大器9-1的输入端连接第三级数字可变增益放大模块8的输出端,中频放大器9-1的输出端连接抗混叠滤波器9-2的输入端。由于在第一级混频后的滤波器采用的是矩形系数较好的晶体滤波器,已经较好的保证了信号带宽,因此在末级抗混叠滤波器的参数设置上可以适当放宽,也能满足要求。中频放大模块9的增益为22dB左右。The intermediate
本发明的中短波频段高动态范围宽带射频前端采用了宽带中频采样软件无线电结构,射频信号经过预选放大模块、变频模块、可变增益放大模块以及中频放大模块后进入到中频基带信号处理部分,中频基带信号处理部分在时钟模块的驱动下做数字解调。这种结构的优点在于:(1)预选放大模块的低噪声放大器具有高增益和低噪声系数,可以有效地降低前端的噪声系数;(2)两级变频可以实现较高的镜像抑制,同时可以满足弱信号输入时对增益的要求;(3)本振信号和提供给数字信号处理部分的时钟采用DDS(直接数字频率合成)+PLL(锁相环)模式可以得到较高的频率分辨率和稳定度;(4)晶体滤波器比普通的LC滤波器有更好的矩形系数能够更好地满足带宽的要求;(5)三级自动增益控制可以有效地分配动态范围,而且数字式的自动增益控制与模拟的方式相比具有控制灵活、准确的特点。The high dynamic range broadband radio frequency front end of the medium and short wave frequency band of the present invention adopts a broadband intermediate frequency sampling software radio structure. The baseband signal processing part performs digital demodulation driven by the clock module. The advantages of this structure are: (1) the low noise amplifier of the pre-selected amplifier module has high gain and low noise figure, which can effectively reduce the noise figure of the front end; (2) two-stage frequency conversion can achieve higher image rejection, and can simultaneously Satisfy the gain requirements for weak signal input; (3) The local oscillator signal and the clock provided to the digital signal processing part adopt DDS (direct digital frequency synthesis) + PLL (phase-locked loop) mode to obtain higher frequency resolution and Stability; (4) The crystal filter has a better square coefficient than the ordinary LC filter, which can better meet the bandwidth requirements; (5) The three-stage automatic gain control can effectively distribute the dynamic range, and the digital automatic Compared with the analog method, the gain control has the characteristics of flexible and accurate control.
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