CN101197320B

CN101197320B - CMOS image sensor and its production method

Info

Publication number: CN101197320B
Application number: CN200610119171A
Authority: CN
Inventors: 卢普生; 杨建平
Original assignee: Semiconductor Manufacturing International Shanghai Corp
Current assignee: Semiconductor Manufacturing International Shanghai Corp; Semiconductor Manufacturing International Beijing Corp
Priority date: 2006-12-05
Filing date: 2006-12-05
Publication date: 2010-05-12
Anticipated expiration: 2026-12-05
Also published as: CN101197320A

Abstract

A CMOS image sensor comprises a silicon substrate, an insulation layer and an etching stop layer which are arranged on the silicon substrate and have dual-damascene structures, an insulation layer and an etching stop layer which are arranged on the insulation layer and the etching stop layer with dual-damascene structures and have no dual-damascene structures, a silicon dioxide layer arranged on the etching stop layer with the dual-damascene structure, a silicon oxynitride layer arranged on the silicon dioxide layer, openings which run through the silicon oxynitride layer, the silicon dioxide layer, the etching stop layer and the insulation layer with no dual-damascene structures, an euphotic zone which is formed on the silicon oxynitride layer and is filled in the openings and a lenticule formed on the euphotic zone of the openings. Through the procedures, a plurality of insulation layers and etching stop layers which are not communicated with metal are removed; resin material with good light transmission is filled in order to reduce the amount of the reflected and absorbed light, increase light energy received by photodiodes and improve photosensitivity, further the CMOS image sensor can achieve no limitation of lighting environment and can image clearly in a dim environmental condition.

Description

The manufacture method of cmos image sensor and cmos image sensor

Technical field

The present invention relates to imageing sensor, and relate more specifically to have the cmos image sensor of sensitivity of improvement and the manufacture method of cmos image sensor.

Background technology

Imageing sensor is converted into the signal of telecommunication from the object receiving optical signals and with light signal, then the signal of telecommunication can be transmitted and be used for further processing, such as digitlization, in memory device, store then, or be used for demonstration, printing etc. on display such as memory, CD or disk.Imageing sensor is generally used for such as devices such as digital camera, video camera, scanner, facsimile machines.

Imageing sensor is generally two types, CCD (CCD) transducer and cmos image sensor (CIS).CCD is called photoelectric coupled device, collects electric charge by photoelectric effect, and the electric charge of every capable pixel is sent on the simulation shift register with the clock signal, and serial conversion is a voltage then.CCD has very low readout noise and dark current noise, has high photon conversion efficiency simultaneously, so both improved signal to noise ratio, has improved sensitivity again, and the incident light of very low luminosity also can detect, and its signal can not covered.CCD also has high dynamic range, improves the scope of application of system environments, does not cause the signal contrast phenomenon greatly because of luminance difference.Compare with CCD, CIS is relatively poor relatively to the sensitivity and the signal to noise ratio of light, causes it to be difficult to contend with CCD on image quality, so mainly to apply in the past image quality is required be not very high low-end market.But new CMOS technology is also constantly being improved, and CIS also more and more has the strength that contends with CCD aspect image quality.The remarkable advantages of CMOS is that integrated level height, power consumption are little, has the condition that height system is integrated, the CMOS chip almost can the function that all images transducer is required be integrated on the chip piece, for example vertical displacement, horizontal displacement register, sequencing control and analog digital conversion etc., even picture processing chip, fast flash memory bank etc. also can be able to be integrated into single-chip, reduce system complexity greatly, reduced cost.The application of CCD then needs the support of peripheral chip, and the multivoltage supply, so specific volume is littler mutually with CCD to adopt the CIS sensor module.Owing to adopt CMOS technology, CIS is power saving more also in addition, and is therefore more competitive on some battery powered portable products, as the application of camera mobile phone.Compare with the CCD product, the production cost of CIS is also more cheap, because CMOS is the standard technology processing procedure, can utilize conventional semiconductor equipment, does not need extra investment goods, and quality can improve with the lifting of work semiconductor technology; Simultaneously, the CMOS production line of global wafer factory is more, also help the reduction of cost during volume production, and production relative complex and the costliness of CCD needs special production line production in the future.

Prior art is made the method for cmos image sensor, shown in Figure 1A, forms peripheral circuit region 101 and image sensing district 100 in silicon substrate 10, and wherein image sensing district 100 comprises photodiode 102, is used to receive light and produces photoelectron; Transistor 103, connect photodiode 102, the output of control photosignal. peripheral circuit region 101 be to the signal of telecommunication that image sensing district 100 transistors 103 obtain read, the logical circuit of conversion, calculation process etc. at silicon substrate 10 surface chemistry vapour deposition processes first insulating barrier 104, be used for the metal level of isolated transistor 103 grids 105 and subsequent deposition; Forming patterning photoresistance (not shown) with spin-coating method on first insulating barrier 104, is mask with the photoresistance, and etching first insulating barrier 104 forms contact hole 107 to grid 105 surfaces of transistor 103; Remove photoresistance, form the first diffusion barrier adhesion layer 106 on first insulating barrier 104 and in the contact hole 107 with chemical vapour deposition technique, prevent to produce diffusion between the metal level of subsequent deposition and the silicon substrate 10, and make the grid 105 formation good electrical contact of metal level with the transistor 103 of subsequent deposition; On the first diffusion barrier adhesion layer 106, form the first metal layer 108 with chemical vapour deposition technique, and the first metal layer 108 is filled full contact hole 107, the first metal layer 108 in the contact hole 107 and grid 105 conductings of transistor 103.

Shown in Figure 1B, grind the first metal layer 108 and the first diffusion barrier adhesion layer 106 to exposing first insulating barrier, 104 surfaces with chemical mechanical milling method; On first insulating barrier 104, form first etching stopping layer 110, prevent to produce in the follow-up heat treatment process etch stop in metal diffusing and the subsequent etch process with chemical vapour deposition technique.

Shown in Fig. 1 C, on first etching stopping layer 110, form second insulating barrier 111 with chemical vapour deposition technique; Forming patterning photoresistance (not shown) with spin-coating method on second insulating barrier 111, is mask with the photoresistance, and etching second insulating barrier 111 and first etching stopping layer 110 form groove 113 and are communicated with contact hole 107 to exposing first insulating barrier 104; Remove photoresistance, form the second diffusion barrier adhesion layer 112 on second insulating barrier 111 and in the groove 113, prevent that the metal level of subsequent deposition from producing diffusion and making the metal level of subsequent deposition produce good adhering to physical vaporous deposition; On the second diffusion barrier adhesion layer 112, form second metal level 114 with chemical vapour deposition technique, and the full groove 113 of second metal level, 114 fillings, second metal level 114 in the groove 113 is communicated with metal in the contact hole 107.

Shown in Fig. 1 D, grind second metal level 114 and the second diffusion barrier adhesion layer 112 to exposing second insulating barrier 111 with chemical mechanical milling method; On second insulating barrier 111, form second etching stopping layer 116, prevent to produce in the follow-up heat treatment process etch stop in metal diffusing and the subsequent etch process with chemical vapour deposition technique; On second etching stopping layer 116, form the 3rd insulating barrier 118 with chemical vapour deposition technique; Etching the 3rd insulating barrier 118 and second etching stopping layer 116 form first dual-damascene structure 120 and are communicated with groove 113 to exposing second insulating barrier, 111 surfaces, and described dual-damascene structure 120 comprises the second contact hole 120a and the second groove 120b; Form the 3rd diffusion barrier adhesion layer 119 with physical vaporous deposition on the 3rd insulating barrier 118 and in first dual-damascene structure 120, prevent in metal diffusing to the three insulating barriers 118 of subsequent deposition; On the 3rd diffusion barrier adhesion layer 119, form the 3rd metal level 122 with galvanoplastic, and the 3rd metal level 122 that the 3rd metal level 122 is filled in full first dual-damascene structure, 120, the first dual-damascene structures 120 is communicated with the metal in the groove 113; According to above-mentioned steps and method, grind the 3rd metal level 120 and the 3rd diffusion barrier adhesion layer 119 to exposing the 3rd insulating barrier 118, on the 3rd insulating barrier 118, form the 3rd etching stopping layer 124, on the 3rd etching stopping layer 124, form the 4th insulating barrier 126, in the 4th insulating barrier 126 of peripheral circuit region 101 and the 3rd etching stopping layer 124, form second dual-damascene structure 128, be communicated with first dual-damascene structure 120 of peripheral circuit region 101, be formed with the 4th diffusion barrier adhesion layer 130 at second dual-damascene structure, 128 sidewalls and bottom, in second dual-damascene structure 128, fill full metal; Again with formation the 4th etching stopping layer 132 on the 4th insulating barrier 126, on the 4th etching stopping layer 132, form the 5th insulating barrier 134, in the 5th insulating barrier 134 of peripheral circuit region 101 and the 4th etching stopping layer 132, form the 3rd dual-damascene structure 136, be communicated with second dual-damascene structure 128 of peripheral circuit region 101, be formed with the 5th diffusion barrier adhesion layer 138 at the 3rd dual-damascene structure 136 sidewalls and bottom, in the 3rd dual-damascene structure 136, fill full metal.

Shown in Fig. 1 E, on the 5th insulating barrier 134, form the 5th etching stopping layer 139 with chemical vapour deposition technique; On the 5th etching stopping layer 139, form silicon oxide layer 140 with chemical vapour deposition technique, as stress-buffer layer; Form silicon oxynitride layer 142 with chemical vapour deposition technique on silicon oxide layer 140, silicon oxynitride layer 142 is chip cover curtain layers, is used for stopping that moisture and the ion in the chip exterior environment enters into chip internal; On silicon oxynitride layer 142, form resin bed (not shown), form lenticule 144 in the zone of photodiode 102 correspondences in image sensing district 100 by exposure technology.

The manufacture method application reference of existing cmos image sensor number is the disclosed technical schemes of 200510084649 Chinese patent application.

Prior art is made the method for cmos image sensor, owing to have multilayer dielectric layer and etching stopping layer in the cmos image sensor, cause light to be reflected in a large number and absorb, the light energy that photodiode is received reduces, light sensitivity is descended, and then the photoenvironment that causes cmos image sensor to use is restricted, and imaging is unintelligible under than the dark situation condition.

Summary of the invention

The problem that the present invention solves provides a kind of manufacture method of cmos image sensor, prevent owing to have multilayer dielectric layer and etching stopping layer in the cmos image sensor, cause light to be reflected in a large number and absorb, the light energy that photodiode is received reduces, light sensitivity is descended, and then the photoenvironment that causes cmos image sensor to use is restricted, and imaging is unintelligible under than the dark situation condition.

For addressing the above problem, the invention provides a kind of manufacture method of cmos image sensor, comprise: on silicon substrate, form some etching stopping layer and insulating barrier combinations successively with dual-damascene structure, in the end one deck has on the insulating barrier of dual-damascene structure and has formed the etching stopping layer that does not contain dual-damascene structure, form silicon oxide layer and silicon oxynitride layer again, the image sensing district forms and comprises the following steps:

A. on silicon oxynitride layer, form the patterning photoresistance;

B. be mask with the photoresistance, etching silicon oxynitride layer, silicon oxide layer, do not contain dual-damascene structure etching stopping layer to exposing the etching stopping layer that comprises dual-damascene structure, form opening;

C. on silicon oxynitride layer, form photic zone, and photic zone is filled the full gate mouth;

D. on opening iuuminting layer, form and the corresponding lenticule of image sensing area photoelectric diode.

With dry etching method etching silicon oxynitride layer, silicon oxide layer, do not contain dual-damascene structure etching stopping layer to exposing the etching stopping layer that comprises dual-damascene structure, form opening.

On silicon oxynitride layer, form photic zone with spin-coating method, and photic zone filling full gate mouth, the thickness of described photic zone on silicon oxynitride layer is 0.3um to 0.8um, euphotic material is an acrylic resin.

Described lenticular thickness is 0.8um to 1.2um.

Steps d comprises: form resin bed on photic zone; Through overexposure and development, on the resin bed above the opening iuuminting layer, form and the corresponding microlens pattern of image sensing area photoelectric diode; The heating resin bed.

Form resin bed with spin-coating method.

The temperature of heating resin bed is 200 ℃ to 300 ℃.

The invention provides a kind of manufacture method of cmos image sensor, comprise: form some etching stopping layers with dual-damascene structure and insulating barriers combination on the silicon substrate successively, in the end one deck has on the insulating barrier of dual-damascene structure and has formed the etching stopping layer that does not contain dual-damascene structure, forming silicon oxide layer and silicon oxynitride layer, the image sensing district forms and comprises the following steps:

A. on silicon oxynitride layer, form the patterning photoresistance;

C. on silicon oxynitride layer, form photic zone with the opening inwall;

D. on the open bottom photic zone, form and the corresponding lenticule of image sensing area photoelectric diode.

The etching stopping layer and the insulating barrier that do not contain dual-damascene structure with dry etching method etching silicon oxynitride layer, silicon oxide layer, image sensing district part fully make up to exposing the etching stopping layer and the insulating barrier that comprise dual-damascene structure, form opening.

On silicon oxynitride layer, reach the opening inwall with spin-coating method and form photic zone.The photic zone uniform thickness of photic zone on the silicon oxynitride layer and opening inwall, described euphotic thickness is 0.3um to 0.8um.Euphotic material is an acrylic resin.

Described lenticular thickness is 0.8um to 1.2um.

Step D comprises: form resin bed on the photic zone of open bottom; Through overexposure and development, on resin bed, form and the corresponding microlens pattern of image sensing area photoelectric diode; The heating resin bed.

Form resin bed with spin-coating method.

The temperature of heating resin bed is 200 ℃ to 300 ℃.

The invention provides a kind of cmos image sensor, comprise silicon substrate, be positioned at some etching stopping layer and insulating barrier combinations on the silicon substrate with dual-damascene structure, be positioned at the etching stopping layer that does not contain dual-damascene structure on the insulating barrier that last one deck has dual-damascene structure, be positioned at the silicon oxide layer on the etching stopping layer that does not contain dual-damascene structure and be positioned at silicon oxynitride layer on the silicon oxide layer, also comprise: opening, run through silicon oxynitride layer, silicon oxide layer, do not contain the etching stopping layer of dual-damascene structure; Photic zone is formed on the silicon oxynitride layer and the opening inwall; Lenticule is formed on the open bottom photic zone and corresponding with the image sensing area photoelectric diode.

Form photic zone with spin-coating method on silicon oxynitride layer and in the opening, the thickness of described photic zone on silicon oxynitride layer is 0.3um to 0.8um, and euphotic material is an acrylic resin.

Described lenticular thickness is 0.8um to 1.2um

The invention provides a kind of manufacture method of cmos image sensor, comprise: form some etching stopping layers with dual-damascene structure and insulating barriers combination on the silicon substrate successively, in the end one deck has on the insulating barrier of dual-damascene structure and has formed the etching stopping layer that does not contain dual-damascene structure, form silicon oxide layer and silicon oxynitride layer again, the image sensing district forms and comprise the following steps: to form photoresist layer on silicon oxynitride layer; Through overexposure, development and heat treatment, on photoresist layer, form the lenticule figure; With the photoresist layer is mask, etching silicon oxynitride layer, silicon oxide layer, do not contain dual-damascene structure etching stopping layer to exposing the etching stopping layer that comprises dual-damascene structure, form opening; The etching stopping layer and the insulating barrier that comprise dual-damascene structure in open bottom make up formation and the corresponding lenticule of image sensing area photoelectric diode.

Etching silicon oxynitride layer, silicon oxide layer, the method that does not contain the etching stopping layer of dual-damascene structure are the dry etching method.

Described lenticular thickness is 0.8um to 1.2um.

The invention provides a kind of cmos image sensor, comprise silicon substrate, be positioned at some etching stopping layer and insulating barrier combinations on the silicon substrate with dual-damascene structure, be positioned at the etching stopping layer that does not contain dual-damascene structure on the insulating barrier that last one deck has dual-damascene structure, be positioned at the silicon oxide layer on the etching stopping layer that does not contain dual-damascene structure and be positioned at silicon oxynitride layer on the silicon oxide layer, also comprise: opening, run through silicon oxynitride layer, silicon oxide layer, do not contain the etching stopping layer of dual-damascene structure; Lenticule, be formed at etching stopping layer that open bottom comprises dual-damascene structure with insulating barrier combination go up and be corresponding with the image sensing area photoelectric diode.

Described lenticular thickness is 0.8um to 1.2um.

Compared with prior art, the present invention has the following advantages: the multilayer dielectric layer that does not carry out the metal connection and the etching stopping layer in image sensing district are removed, fill the good resin material of printing opacity or directly multilayer dielectric layer and etching stopping layer are etched into lenticule, the amount that light is reflected and absorbs reduces, the light energy that photodiode is received increases, light sensitivity improves, and then realizes that the photoenvironment that cmos image sensor uses is unrestricted, and imaging is clear under than the dark situation condition.

Description of drawings

Figure 1A to Fig. 1 E is the process schematic diagram that prior art is made cmos image sensor;

Fig. 2 A to Fig. 2 E is that first embodiment of the invention is made cmos image sensor process schematic diagram;

Fig. 3 A to Fig. 3 E is that second embodiment of the invention is made cmos image sensor process schematic diagram;

Fig. 4 A to Fig. 4 E is that third embodiment of the invention is made cmos image sensor process schematic diagram.

Embodiment

Cmos image sensor is to receive light and convert light signal to the signal of telecommunication by photodiode, in order to strengthen the light energy that photodiode receives, improve light sensitivity, can the loss of light in communication process be reduced by optimizing the membrane structure of light channel.The present invention removes the multilayer dielectric layer that does not carry out the metal connection and the etching stopping layer in image sensing district, fill the good resin material of printing opacity or directly multilayer dielectric layer and etching stopping layer are etched into lenticule, the amount that light is reflected and absorbs reduces, the light energy that photodiode is received increases, light sensitivity improves, and then realizing that the photoenvironment that cmos image sensor uses is unrestricted, imaging is clear under than the dark situation condition.For above-mentioned purpose of the present invention, feature and advantage can be become apparent more, the specific embodiment of the present invention is described in detail below in conjunction with accompanying drawing.

The manufacture method of cmos image sensor of the present invention, comprise: on silicon substrate, form some etching stopping layer and insulating barrier combinations successively with dual-damascene structure, in the end one deck has on the insulating barrier of dual-damascene structure and has formed the etching stopping layer that does not contain dual-damascene structure, form silicon oxide layer and silicon oxynitride layer again, the image sensing district forms and comprises the following steps:

A. on silicon oxynitride layer, form the patterning photoresistance;

Fig. 2 A to Fig. 2 E is that first embodiment of the invention is made cmos image sensor process schematic diagram.Shown in Fig. 2 A, in silicon substrate 20, form peripheral circuit region 201 and image sensing district 200, wherein image sensing district 200 comprises photodiode 202, be used to receive light and produce photoelectron, transistor 203 connects photodiode 202, the output of control photosignal, peripheral circuit region 201 be to the signal of telecommunication that image sensing district 200 obtains read, the logical circuit of conversion, calculation process etc.; Forming thickness on silicon substrate 20 surfaces with chemical vapour deposition technique is first insulating barrier 204 of 0.5um to 1um, is used for the metal level of isolated transistor 203 grids and subsequent deposition; Forming patterning photoresistance (not shown) with spin-coating method on first insulating barrier 204, is mask with the photoresistance, and etching first insulating barrier 204 forms contact hole 207 to grid 205 surfaces of transistor 203; Remove photoresistance, with chemical vapour deposition technique on first insulating barrier 204 and contact hole 207 in formation thickness be the first diffusion barrier adhesion layer 206 of 150 dust to 250 dusts, prevent to produce diffusion between the metal level of subsequent deposition and the silicon substrate 20, and make the grid 205 formation good electrical contact of metal level with the transistor 203 of subsequent deposition; Form the first metal layer 208 with chemical vapour deposition technique on the first diffusion barrier adhesion layer 206, and the first metal layer 208 is filled full contact hole 207, the grid 205 that is used for allomeric pipe 203 is communicated with.

Shown in Fig. 2 B, grind the first metal layer 208 and the first diffusion barrier adhesion layer 206 to exposing first insulating barrier, 204 surfaces with chemical mechanical milling method; Forming thickness with chemical vapour deposition technique on first insulating barrier 204 is first etching stopping layer 210 of 300 dust to 500 dusts, prevents to produce in the follow-up heat treatment process etch stop in metal diffusing and the subsequent etch process; On first etching stopping layer 210, form second insulating barrier 211 that thickness is 2000 dust to 4000 dusts with chemical vapour deposition technique; Forming patterning photoresistance (not shown) with spin-coating method on second insulating barrier 211, is mask with the photoresistance, and etching second insulating barrier 211 forms groove 213 and is communicated with contact hole 207 to exposing first insulating barrier 204; Remove photoresistance, forming thickness with physical vaporous deposition on second insulating barrier 211 and in the groove 213 is the second diffusion barrier adhesion layer 212 of 200 dust to 300 dusts, prevents good the adhering to of metal level generation that the metal level of subsequent deposition produces diffusion and makes subsequent deposition; On second diffusion impervious layer 212, form second metal level 214 with chemical vapour deposition technique, and second metal level 214 filled full groove 213, be used for being communicated with contact hole 207 metals.

Shown in Fig. 2 C, grind second metal level 214 and the second diffusion barrier adhesion layer 212 to exposing second insulating barrier 211 with chemical mechanical milling method; Forming thickness with chemical vapour deposition technique on second insulating barrier 211 is second etching stopping layer 216 of 300 dust to 500 dusts, prevents to produce in the follow-up heat treatment process etch stop in metal diffusing and the subsequent etch process; On second etching stopping layer 216, form the 3rd insulating barrier 218 that thickness is 6000 dust to 8000 dusts with chemical vapour deposition technique; Etching the 3rd insulating barrier 218 to second insulating barriers 211 surfaces form first dual-damascene structure 220 and are communicated with groove 213, and described dual-damascene structure 220 comprises the second contact hole 220a and the second groove 220b; With physical vaporous deposition on the 3rd insulating barrier 218 and first dual-damascene structure 220 in formation thickness be the 3rd diffusion barrier adhesion layer 219 of 200 dust to 300 dusts, prevent in metal diffusing to the three insulating barriers 218 of subsequent deposition; On the 3rd diffusion barrier adhesion layer 219, form the 3rd metal level 222 with galvanoplastic, and the 3rd metal level 222 is filled full first dual-damascene structure 220, be used for being communicated with the metal of groove 213; According to above-mentioned steps and method, grind the 3rd metal level 220 and the 3rd diffusion barrier adhesion layer 219 to exposing the 3rd insulating barrier 218, on the 3rd insulating barrier 218, form the 3rd etching stopping layer 224, on the 3rd etching stopping layer 224, form the 4th insulating barrier 226, in the 4th insulating barrier 226 of peripheral circuit region 201, form second dual-damascene structure 228, be communicated with first dual-damascene structure 220 of peripheral circuit region 201, be formed with the 4th diffusion barrier adhesion layer 230 at second dual-damascene structure, 228 sidewalls and bottom, in second dual-damascene structure 228, fill full copper; Again with formation the 4th etching stopping layer 232 on the 4th insulating barrier 226, on the 4th etching stopping layer 232, form the 5th insulating barrier 234, in the 5th insulating barrier 234 of peripheral circuit region 201, form the 3rd dual-damascene structure 236, be communicated with second dual-damascene structure 228 of peripheral circuit region 201, be formed with the 5th diffusion barrier adhesion layer 238 at the 3rd dual-damascene structure 236 sidewalls and bottom, in the 3rd dual-damascene structure 236, fill full copper.

Shown in Fig. 2 D, on the 5th insulating barrier 234, form the 5th etching stopping layer 239 that thickness is 500 dust to 700 dusts with chemical vapour deposition technique; Forming thickness with chemical vapour deposition technique on the 5th etching stopping layer 239 is the silicon oxide layer 240 of 2000 dust to 4000 dusts, as stress-buffer layer; Form the silicon oxynitride layer 242 that thickness is 2000 dust to 4000 dusts with chemical vapour deposition technique on silicon oxide layer 240, silicon oxynitride layer 242 is chip cover curtain layers, is used for stopping that moisture and the ion in the chip exterior environment enters into chip internal; On silicon oxynitride layer 242, form patterning photoresistance (not shown), with the photoresistance is mask, to exposing the 3rd etching stopping layer 224, form opening 243 with silicon oxynitride layer 242, silicon oxide layer 240, the 5th etching stopping layer 239, the 5th insulating barrier 234, the 4th etching stopping layer 232 and the 4th insulating barrier 226 of dry etching method etching pattern sensing unit 200.

Shown in Fig. 2 E, form continuous photic zone 244 on silicon oxynitride layer 242 and in the opening 243 with spin-coating method, as the usefulness of the antireflection of light, the thickness of photic zone 244 on silicon oxynitride layer 242 is 0.3 micron to 0.8 micron, and photic zone 244 is filled full gate mouths 243; Spin coating one deck resin bed (not shown) on photic zone 244 then, through overexposure and be developed in photodiode 202 corresponding resin beds on form microlens pattern, heat under 200 ℃ to 300 ℃ temperature, making resin bed abutment surface tension force form thickness is 0.8um to 1.2um lenticule 246.

In the present embodiment, the material of first insulating barrier 204, second insulating barrier 211, the 3rd insulating barrier 218, the 4th insulating barrier 226 and the 5th insulating barrier 234 is phosphorosilicate glass (PSG), fluorine silex glass (FSG) or undoped silicon glass (USG).The thickness concrete example of first insulating barrier 204 such as 0.5um, 0.6um, 0.7um, 0.8um, 0.9um or 1um; The thickness concrete example of second insulating barrier 211 is as 2000 dusts, 2500 dusts, 3000 dusts, 3500 dusts or 4000 dusts; The thickness concrete example of the 3rd insulating barrier 218, the 4th insulating barrier 226 and the 5th insulating barrier 234 is as 6000 dusts, 6500 dusts, 7000 dusts, 7500 dusts or 8000 dusts.

In the present embodiment, the material of the first diffusion barrier adhesion layer 206 is titanium and titanium nitride; The material of the second diffusion barrier adhesion layer 212, the 3rd diffusion barrier adhesion layer 219, the 4th diffusion barrier adhesion layer 230 and the 5th diffusion barrier adhesion layer 238 is tantalum and tantalum nitride. the thickness concrete example of the first diffusion barrier adhesion layer 206 is as 150 dusts, 170 dusts, 190 dusts, 200 dusts, 210 dusts, 230 dusts or 250 dusts; The thickness concrete example of the second diffusion barrier adhesion layer 212, the 3rd diffusion barrier adhesion layer 219, the 4th diffusion barrier adhesion layer 230 and the 5th diffusion barrier adhesion layer 238 is as 200 dusts, 220 dusts, 250 dusts, 280 dusts or 300 dusts.

In the present embodiment, the material of the first metal layer 208 is a tungsten; The material of second metal level 214 and the 3rd metal level 222 is a copper.

In the present embodiment, the material of first etching stopping layer 210, second etching stopping layer 216, the 3rd etching stopping layer 224 and the 4th etching stopping layer 232 is silicon nitrides.The thickness concrete example of first etching stopping layer 210, second etching stopping layer 216, the 3rd etching stopping layer 224 and the 4th etching stopping layer 232 is as 300 dusts, 350 dusts, 400 dusts, 450 dusts or 500 dusts; The thickness concrete example of the 5th etching stopping layer 239 is as 500 dusts, 550 dusts, 600 dusts, 650 dusts or 700 dusts.

In the present embodiment, the thickness concrete example of silicon oxide layer 240 is as 2000 dusts, 2500 dusts, 3000 dusts, 3500 dusts or 4000 dusts.

In the present embodiment, the thickness concrete example of silicon oxynitride layer 242 is as 2000 dusts, 2500 dusts, 3000 dusts, 3500 dusts or 4000 dusts.

In the present embodiment, thickness concrete example such as 0.3um, 0.4um, 0.5um, 0.6um, 0.7um or the 0.8um of photic zone 244 on silicon oxynitride layer 242.The material of photic zone 244 is acrylic resins.

In the present embodiment, the thickness concrete example of lenticule 246 such as 0.8um, 0.9um, 1um, 1.1um or 1.2um.

Continue with reference to shown in figure 2A to Fig. 2 E, cmos image sensor comprises: silicon substrate 20; Peripheral circuit region 201 and image sensing district 200 are arranged in silicon substrate 20, and 200 both sides, image sensing district are peripheral circuit region 201, comprise photodiode 202 and the transistor 203 that is connected with photodiode in the image sensing district 200; First insulating barrier 204 is formed on the silicon substrate 20, and contact hole 207 runs through first insulating barrier 204, and contact hole 207 sidewalls and bottom are coated with the first diffusion barrier adhesion layer 206; First etching stopping layer 210 is covered on first insulating barrier 204, second insulating barrier 211 is formed on first etching stopping layer 210, groove 213 runs through second insulating barrier 211 and first etching stopping layer 210, be communicated with contact hole 207, groove 213 sidewalls and bottom are coated with the second diffusion barrier adhesion layer 212; Second etching stopping layer 216 is covered on second insulating barrier 211, the 3rd insulating barrier 218 is formed on second etching stopping layer 216, first dual-damascene structure 220 runs through the 3rd insulating barrier 218 and second etching stopping layer 216, be communicated with groove 213, first dual-damascene structure, 220 sidewalls and bottom are coated with the 3rd diffusion barrier adhesion layer 219; The 3rd etching stopping layer 224 is covered on the 3rd insulating barrier 218, the 4th insulating barrier 226 is formed on the 3rd etching stopping layer 224,228 of second dual-damascene structures are positioned at peripheral circuit region 201 and run through the 4th insulating barrier 226 and the 3rd etching stopping layer 224, be communicated with first dual-damascene structure 220, second dual-damascene structure, 228 sidewalls and bottom are coated with the 4th diffusion barrier adhesion layer 230; The 4th etching stopping layer 232 is covered on the 4th insulating barrier 226, the 5th insulating barrier 234 is formed on the 4th etching stopping layer 232,236 of the 3rd dual-damascene structures are positioned at peripheral circuit region 201 and run through the 5th insulating barrier 234 and the 4th etching stopping layer 232, be communicated with second dual-damascene structure 228, the 3rd dual-damascene structure 236 sidewalls and bottom are coated with the 5th diffusion barrier adhesion layer 238; The 5th etching stopping layer 239 is covered on the 5th insulating barrier 234; Silicon oxide layer 240 is positioned on the 5th etching stopping layer 239; Silicon oxynitride 242 is positioned on the silicon oxide layer 240; Opening 243 is positioned at image sensing district 200 and runs through silicon oxynitride layer 242, silicon oxide layer 240, the 5th etching stopping layer 239, the 5th insulating barrier 234, the 4th etching stopping layer 232 and the 4th insulating barrier 226 to exposing the 3rd etching stopping layer 224; Photic zone 244 is positioned on the silicon oxynitride layer 242 and is filled in opening 243; Lenticule 246 is positioned on the photic zone and is corresponding with photodiode 202.

A. on silicon oxynitride layer, form the patterning photoresistance;

C. on silicon oxynitride layer, form photic zone with the opening inwall;

Fig. 3 A to Fig. 3 E is that second embodiment of the invention is made cmos image sensor process schematic diagram.As shown in Figure 3A, in silicon substrate 30, form peripheral circuit region 301 and image sensing district 300, wherein image sensing district 300 comprises photodiode 302, be used to receive light and produce photoelectron, transistor 303 connects photodiode 302, the output of control photosignal, peripheral circuit region 301 be to the signal of telecommunication that image sensing district 300 obtains read, the logical circuit of conversion, calculation process etc.; Forming thickness on silicon substrate 30 surfaces with chemical vapour deposition technique is first insulating barrier 304 of 0.5um to 1um, is used for the metal level of isolated transistor 303 grids and subsequent deposition; Forming patterning photoresistance (not shown) with spin-coating method on first insulating barrier 304, is mask with the photoresistance, and etching first insulating barrier 304 forms contact hole 307 to grid 305 surfaces of transistor 303; Remove photoresistance, with chemical vapour deposition technique on first insulating barrier 304 and contact hole 307 in formation thickness be the first diffusion barrier adhesion layer 306 of 150 dust to 250 dusts, prevent to produce diffusion between the metal level of subsequent deposition and the silicon substrate 30, and make the grid 305 formation good electrical contact of metal level with the transistor 303 of subsequent deposition; Form the first metal layer 308 with chemical vapour deposition technique on the first diffusion barrier adhesion layer 306, and the first metal layer 308 is filled full contact hole 307, the grid 305 that is used for allomeric pipe 303 is communicated with.

Shown in Fig. 3 B, grind the first metal layer 308 and the first diffusion barrier adhesion layer 306 to exposing first insulating barrier, 304 surfaces with chemical mechanical milling method; Forming thickness with chemical vapour deposition technique on first insulating barrier 304 is first etching stopping layer 310 of 300 dust to 500 dusts, prevents to produce in the follow-up heat treatment process etch stop in metal diffusing and the subsequent etch process; On first etching stopping layer 310, form second insulating barrier 311 that thickness is 2000 dust to 4000 dusts with chemical vapour deposition technique; Forming patterning photoresistance (not shown) with spin-coating method on second insulating barrier 311, is mask with the photoresistance, and etching second insulating barrier 311 forms groove 313 and is communicated with contact hole 307 to exposing first insulating barrier 304; Remove photoresistance, forming thickness with physical vaporous deposition on second insulating barrier 311 and in the groove 313 is the second diffusion barrier adhesion layer 312 of 200 dust to 300 dusts, prevents good the adhering to of metal level generation that the metal level of subsequent deposition produces diffusion and makes subsequent deposition; On second diffusion impervious layer 312, form second metal level 314 with chemical vapour deposition technique, and second metal level 314 is filled full groove 313, be used for being communicated with contact hole 307 metals.

Shown in Fig. 3 C, grind second metal level 314 and the second diffusion barrier adhesion layer 312 to exposing second insulating barrier 311 with chemical mechanical milling method; Forming thickness with chemical vapour deposition technique on second insulating barrier 311 is second etching stopping layer 316 of 300 dust to 500 dusts, prevents to produce in the follow-up heat treatment process etch stop in metal diffusing and the subsequent etch process; On second etching stopping layer 316, form the 3rd insulating barrier 318 that thickness is 6000 dust to 8000 dusts with chemical vapour deposition technique; Etching the 3rd insulating barrier 318 to second insulating barriers 311 surfaces form first dual-damascene structure 320 and are communicated with groove 313, and described dual-damascene structure 320 comprises the second contact hole 320a and the second groove 320b; With physical vaporous deposition on the 3rd insulating barrier 318 and first dual-damascene structure 320 in formation thickness be the 3rd diffusion barrier adhesion layer 319 of 200 dust to 300 dusts, prevent in metal diffusing to the three insulating barriers 318 of subsequent deposition; On the 3rd diffusion barrier adhesion layer 319, form the 3rd metal level 322 with galvanoplastic, and the 3rd metal level 322 is filled full first dual-damascene structure 320, be used for being communicated with the metal of groove 313; According to above-mentioned steps and method, grind the 3rd metal level 320 and the 3rd diffusion barrier adhesion layer 319 to exposing the 3rd insulating barrier 318, on the 3rd insulating barrier 318, form the 3rd etching stopping layer 324, on the 3rd etching stopping layer 324, form the 4th insulating barrier 326, in the 4th insulating barrier 326 of peripheral circuit region 301, form second dual-damascene structure 328, be communicated with first dual-damascene structure 320 of peripheral circuit region 301, be formed with the 4th diffusion barrier adhesion layer 330 at second dual-damascene structure, 328 sidewalls and bottom, in second dual-damascene structure 328, fill full copper; Again with formation the 4th etching stopping layer 332 on the 4th insulating barrier 326, on the 4th etching stopping layer 332, form the 5th insulating barrier 334, in the 5th insulating barrier 334 of peripheral circuit region 301, form the 3rd dual-damascene structure 336, be communicated with second dual-damascene structure 328 of peripheral circuit region 301, be formed with the 5th diffusion barrier adhesion layer 338 at the 3rd dual-damascene structure 336 sidewalls and bottom, in the 3rd dual-damascene structure 336, fill full copper.

Shown in Fig. 3 D, on the 5th insulating barrier 334, form the 5th etching stopping layer 339 that thickness is 500 dust to 700 dusts with chemical vapour deposition technique; Forming thickness with chemical vapour deposition technique on the 5th etching stopping layer 339 is the silicon oxide layer 340 of 2000 dust to 4000 dusts, as stress-buffer layer; Form the silicon oxynitride layer 342 that thickness is 2000 dust to 4000 dusts with chemical vapour deposition technique on silicon oxide layer 340, silicon oxynitride layer 342 is chip cover curtain layers, is used for stopping that moisture and the ion in the chip exterior environment enters into chip internal; On silicon oxynitride layer 342, form patterning photoresistance (not shown), with the photoresistance is mask, to exposing the 3rd etching stopping layer 324, form opening 343 with silicon oxynitride layer 342, silicon oxide layer 340, the 5th etching stopping layer 339, the 5th insulating barrier 334, the 4th etching stopping layer 332 and the 4th insulating barrier 326 of dry etching method etching pattern sensing unit 300.

Shown in Fig. 3 E, with spin-coating method on silicon oxynitride layer 342 and the inwall (described inwall is sidewall and bottom) of opening 343 to form thickness be 0.3um to 0.8um photic zone 344, as the usefulness of the antireflection of light; Spin coating one deck resin bed (not shown) on the photic zone 344 of opening 343 bottoms then, be specially acrylic resin, through overexposure and be developed in photodiode 302 corresponding resin beds on form microlens pattern, through heating, making resin bed abutment surface tension force form thickness is 0.8um to 1.2um lenticule 346.

In the present embodiment, the material of first insulating barrier 304, second insulating barrier 311, the 3rd insulating barrier 318, the 4th insulating barrier 326 and the 5th insulating barrier 334 is phosphorosilicate glass (PSG), fluorine silex glass (FSG) or undoped silicon glass (USG).The thickness concrete example of first insulating barrier 304 such as 0.5um, 0.6um, 0.7um, 0.8um, 0.9um or 1um; The thickness concrete example of second insulating barrier 311 is as 2000 dusts, 2500 dusts, 3000 dusts, 3500 dusts or 4000 dusts; The thickness concrete example of the 3rd insulating barrier 318, the 4th insulating barrier 326 and the 5th insulating barrier 334 is as 6000 dusts, 6500 dusts, 7000 dusts, 7500 dusts or 8000 dusts.

In the present embodiment, the material of the first diffusion barrier adhesion layer 306 is titanium and titanium nitride; The material of the second diffusion barrier adhesion layer 312, the 3rd diffusion barrier adhesion layer 319, the 4th diffusion barrier adhesion layer 330 and the 5th diffusion barrier adhesion layer 338 is tantalum and tantalum nitride.The thickness concrete example of the first diffusion barrier adhesion layer 306 is as 150 dusts, 170 dusts, 190 dusts, 200 dusts, 210 dusts, 230 dusts or 250 dusts; The thickness concrete example of the second diffusion barrier adhesion layer 312, the 3rd diffusion barrier adhesion layer 319, the 4th diffusion barrier adhesion layer 330 and the 5th diffusion barrier adhesion layer 338 is as 200 dusts, 220 dusts, 250 dusts, 280 dusts or 300 dusts.

In the present embodiment, the material of the first metal layer 308 is a tungsten; The material of second metal level 314 and the 3rd metal level 322 is a copper.

In the present embodiment, the material of first etching stopping layer 310, second etching stopping layer 316, the 3rd etching stopping layer 324 and the 4th etching stopping layer 332 is silicon nitrides.The thickness concrete example of first etching stopping layer 310, second etching stopping layer 316, the 3rd etching stopping layer 324 and the 4th etching stopping layer 332 is as 300 dusts, 350 dusts, 400 dusts, 450 dusts or 500 dusts; The thickness concrete example of the 5th etching stopping layer 339 is as 500 dusts, 550 dusts, 600 dusts, 650 dusts or 700 dusts.

In the present embodiment, the thickness concrete example of silicon oxide layer 340 is as 2000 dusts, 2500 dusts, 3000 dusts, 3500 dusts or 4000 dusts.

In the present embodiment, the thickness concrete example of silicon oxynitride layer 342 is as 2000 dusts, 2500 dusts, 3000 dusts, 3500 dusts or 4000 dusts.

In the present embodiment, thickness concrete example such as 0.3um, 0.4um, 0.5um, 0.6um, 0.7um or the 0.8um of photic zone 344 on silicon oxynitride layer 342.The material of photic zone 344 is acrylic resins.

In the present embodiment, the thickness concrete example of lenticule 346 such as 0.8um, 0.9um, 1um, 1.1um or 1.2um.

Cmos image sensor of the present invention, comprise silicon substrate, be positioned at some etching stopping layer and insulating barrier combinations on the silicon substrate with dual-damascene structure, be positioned at the etching stopping layer that does not contain dual-damascene structure on the insulating barrier that last one deck has dual-damascene structure, be positioned at the silicon oxide layer on the etching stopping layer that does not contain dual-damascene structure and be positioned at silicon oxynitride layer on the silicon oxide layer, also comprise: opening, run through silicon oxynitride layer, silicon oxide layer, do not contain the etching stopping layer of dual-damascene structure; Photic zone is formed on the silicon oxynitride layer and the opening inwall; Lenticule is formed on the open bottom photic zone and corresponding with the image sensing area photoelectric diode.

Continue with reference to figure 3A to Fig. 3 E, cmos image sensor comprises: silicon substrate 30; Peripheral circuit region 301 and image sensing district 300 are arranged in silicon substrate 30, and 300 both sides, image sensing district are peripheral circuit region 301, comprise photodiode 302 and the transistor 303 that is connected with photodiode in the image sensing district 300; First insulating barrier 304 is formed on the silicon substrate 30, and contact hole 307 runs through first insulating barrier 304, and contact hole 307 sidewalls and bottom are coated with the first diffusion barrier adhesion layer 306; First etching stopping layer 310 is covered on first insulating barrier 304, second insulating barrier 311 is formed on first etching stopping layer 310, groove 313 runs through second insulating barrier 311 and first etching stopping layer 310, be communicated with contact hole 307, groove 313 sidewalls and bottom are coated with the second diffusion barrier adhesion layer 312; Second etching stopping layer 316 is covered on second insulating barrier 311, the 3rd insulating barrier 318 is formed on second etching stopping layer 316, first dual-damascene structure 320 runs through the 3rd insulating barrier 318 and second etching stopping layer 316, be communicated with groove 313, first dual-damascene structure, 320 sidewalls and bottom are coated with the 3rd diffusion barrier adhesion layer 319; The 3rd etching stopping layer 324 is covered on the 3rd insulating barrier 318, the 4th insulating barrier 326 is formed on the 3rd etching stopping layer 324,328 of second dual-damascene structures are positioned at peripheral circuit region 301 and run through the 4th insulating barrier 326 and the 3rd etching stopping layer 324, be communicated with first dual-damascene structure 320, second dual-damascene structure, 328 sidewalls and bottom are coated with the 4th diffusion barrier adhesion layer 330; The 4th etching stopping layer 332 is covered on the 4th insulating barrier 326, the 5th insulating barrier 334 is formed on the 4th etching stopping layer 332,336 of the 3rd dual-damascene structures are positioned at peripheral circuit region 301 and run through the 5th insulating barrier 334 and the 4th etching stopping layer 332, be communicated with second dual-damascene structure 328, the 3rd dual-damascene structure 336 sidewalls and bottom are coated with the 5th diffusion barrier adhesion layer 338; The 5th etching stopping layer 339 is covered on the 5th insulating barrier 334; Silicon oxide layer 340 is positioned on the 5th etching stopping layer 339; Silicon oxynitride 342 is positioned on the silicon oxide layer 340; Opening 343 is positioned at image sensing district 300 and runs through silicon oxynitride layer 342, silicon oxide layer 340, the 5th etching stopping layer 339, the 5th insulating barrier 334, the 4th etching stopping layer 332 and the 4th insulating barrier 326 to exposing the 3rd etching stopping layer 324; Photic zone 344 is positioned at silicon oxynitride layer 342 and opening 343 inwalls; Lenticule 346 is positioned on the photic zone and is corresponding with photodiode 302.

The manufacture method of cmos image sensor of the present invention, comprise: some successively formation have the etching stopping layer and the insulating barrier combination of dual-damascene structure on silicon substrate, in the end one deck has on the insulating barrier of dual-damascene structure and has formed the etching stopping layer that does not contain dual-damascene structure, form silicon oxide layer and silicon oxynitride layer again,, the image sensing district forms and comprise the following steps: to form photoresist layer on silicon oxynitride layer; Through overexposure and development, on photoresist layer, form the lenticule figure; With the photoresist layer is mask, etching silicon oxynitride layer, silicon oxide layer, do not contain dual-damascene structure etching stopping layer to exposing the etching stopping layer that comprises dual-damascene structure, form opening; The etching stopping layer and the insulating barrier that comprise dual-damascene structure in open bottom make up formation and the corresponding lenticule of image sensing area photoelectric diode.

Fig. 4 A to Fig. 4 E is that third embodiment of the invention is made cmos image sensor process schematic diagram.Shown in Fig. 4 A, in silicon substrate 40, form peripheral circuit region 401 and image sensing district 400, wherein image sensing district 400 comprises photodiode 402, be used to receive light and produce photoelectron, transistor 403 connects photodiode 402, the output of control photosignal, peripheral circuit region 401 be to the signal of telecommunication that image sensing district 400 obtains read, the logical circuit of conversion, calculation process etc.; Forming thickness on silicon substrate 40 surfaces with chemical vapour deposition technique is first insulating barrier 404 of 0.5um to 1um, is used for the metal level of isolated transistor 403 grids and subsequent deposition; Forming patterning photoresistance (not shown) with spin-coating method on first insulating barrier 404, is mask with the photoresistance, and etching first insulating barrier 404 forms contact hole 407 to grid 405 surfaces of transistor 403; Remove photoresistance, with chemical vapour deposition technique on first insulating barrier 404 and contact hole 407 in formation thickness be the first diffusion barrier adhesion layer 406 of 150 dust to 250 dusts, prevent to produce diffusion between the metal level of subsequent deposition and the silicon substrate 40, and make the grid 405 formation good electrical contact of metal level with the transistor 403 of subsequent deposition; Form the first metal layer 408 with chemical vapour deposition technique on the first diffusion barrier adhesion layer 406, and the first metal layer 408 is filled full contact hole 407, the grid 405 that is used for allomeric pipe 403 is communicated with.

Shown in Fig. 4 B, grind the first metal layer 408 and the first diffusion barrier adhesion layer 406 to exposing first insulating barrier, 404 surfaces with chemical mechanical milling method; Forming thickness with chemical vapour deposition technique on first insulating barrier 404 is first etching stopping layer 410 of 300 dust to 500 dusts, prevents to produce in the follow-up heat treatment process etch stop in metal diffusing and the subsequent etch process; On first etching stopping layer 410, form second insulating barrier 411 that thickness is 2000 dust to 4000 dusts with chemical vapour deposition technique; Forming patterning photoresistance (not shown) with spin-coating method on second insulating barrier 411, is mask with the photoresistance, and etching second insulating barrier 411 forms groove 413 and is communicated with contact hole 407 to exposing first insulating barrier 404; Remove photoresistance, forming thickness with physical vaporous deposition on second insulating barrier 411 and in the groove 413 is the second diffusion barrier adhesion layer 412 of 200 dust to 300 dusts, prevents good the adhering to of metal level generation that the metal level of subsequent deposition produces diffusion and makes subsequent deposition; On second diffusion impervious layer 412, form second metal level 414 with chemical vapour deposition technique, and second metal level 414 is filled full groove 413, be used for being communicated with contact hole 407 metals.

Shown in Fig. 4 C, grind second metal level 414 and the second diffusion barrier adhesion layer 412 to exposing second insulating barrier 411 with chemical mechanical milling method; Forming thickness with chemical vapour deposition technique on second insulating barrier 411 is second etching stopping layer 416 of 300 dust to 500 dusts, prevents to produce in the follow-up heat treatment process etch stop in metal diffusing and the subsequent etch process; On second etching stopping layer 416, form the 3rd insulating barrier 418 that thickness is 6000 dust to 8000 dusts with chemical vapour deposition technique; Etching the 3rd insulating barrier 418 to second insulating barriers 411 surfaces form first dual-damascene structure 420 and are communicated with groove 413, and described dual-damascene structure 420 comprises the second contact hole 420a and the second groove 420b; With physical vaporous deposition on the 3rd insulating barrier 418 and first dual-damascene structure 420 in formation thickness be the 3rd diffusion barrier adhesion layer 419 of 200 dust to 300 dusts, prevent in metal diffusing to the three insulating barriers 418 of subsequent deposition; On the 3rd diffusion barrier adhesion layer 419, form the 3rd metal level 422 with galvanoplastic, and the 3rd metal level 422 is filled full first dual-damascene structure 420, be used for being communicated with the metal of groove 413; According to above-mentioned steps and method, grind the 3rd metal level 420 and the 3rd diffusion barrier adhesion layer 419 to exposing the 3rd insulating barrier 418, on the 3rd insulating barrier 418, form the 3rd etching stopping layer 424, on the 3rd etching stopping layer 424, form the 4th insulating barrier 426, in the 4th insulating barrier 426 of peripheral circuit region 401, form second dual-damascene structure 428, be communicated with first dual-damascene structure 420 of peripheral circuit region 401, be formed with the 4th diffusion barrier adhesion layer 430 at second dual-damascene structure, 428 sidewalls and bottom, in second dual-damascene structure 428, fill full copper; Again with formation the 4th etching stopping layer 432 on the 4th insulating barrier 426, on the 4th etching stopping layer 432, form the 5th insulating barrier 434, in the 5th insulating barrier 434 of peripheral circuit region 401, form the 3rd dual-damascene structure 436, be communicated with second dual-damascene structure 428 of peripheral circuit region 401, be formed with the 5th diffusion barrier adhesion layer 438 at the 3rd dual-damascene structure 436 sidewalls and bottom, in the 3rd dual-damascene structure 436, fill full copper.

Shown in Fig. 4 D, on the 5th insulating barrier 434, form the 5th etching stopping layer 439 that thickness is 500 dust to 700 dusts with chemical vapour deposition technique; Forming thickness with chemical vapour deposition technique on the 5th etching stopping layer 439 is the silicon oxide layer 440 of 2000 dust to 4000 dusts, as stress-buffer layer; Form the silicon oxynitride layer 442 that thickness is 2000 dust to 4000 dusts with chemical vapour deposition technique on silicon oxide layer 440, silicon oxynitride layer 442 is chip cover curtain layers, is used for stopping that moisture and the ion in the chip exterior environment enters into chip internal; On silicon oxynitride layer 442, form hard mask layer 443 with chemical vapour deposition technique, as etching stopping layer; Spin coating one deck patterning photoresist layer (not shown) on hard mask layer 443, the hard mask layer 443 that with the patterning photoresist layer is mask etching pattern sensing unit 400 is to exposing silicon oxynitride layer 442; On the silicon oxynitride layer 442 on the hard mask layer 443 of peripheral circuit region 401 and image sensing district 400, form photoresist layer 444, through on photoresist layer 444, forming lenticule figure 445 after overexposure, development and the heat treatment.

Shown in Fig. 4 E, with dry etching method etching photoresist layer 444, silicon oxynitride layer 442, silicon oxide layer 440, the 5th etching stopping layer 439, the 5th insulating barrier 434, the 4th etching stopping layer 432 and the 4th insulating barrier 426 to exposing hard mask layer 443 and the 3rd etching stopping layer 424, image sensing region 400 form openings 447 and with image sensing district 400 photodiodes, 402 corresponding the 3rd etching stopping layers 424 on to form thickness be 0.8um to 1.2um lenticule 446; Remove hard mask layer 443.

In the present embodiment, the material of first insulating barrier 404, second insulating barrier 411, the 3rd insulating barrier 418, the 4th insulating barrier 426 and the 5th insulating barrier 434 is phosphorosilicate glass (PSG), fluorine silex glass (FSG) or undoped silicon glass (USG).The thickness concrete example of first insulating barrier 404 such as 0.5um, 0.6um, 0.7um, 0.8um, 0.9um or 1um; The thickness concrete example of second insulating barrier 411 is as 2000 dusts, 2500 dusts, 3000 dusts, 3500 dusts or 4000 dusts; The thickness concrete example of the 3rd insulating barrier 418, the 4th insulating barrier 426 and the 5th insulating barrier 434 is as 6000 dusts, 6500 dusts, 7000 dusts, 7500 dusts or 8000 dusts.

In the present embodiment, the material of the first diffusion barrier adhesion layer 406 is titanium and titanium nitride; The material of the second diffusion barrier adhesion layer 412, the 3rd diffusion barrier adhesion layer 419, the 4th diffusion barrier adhesion layer 430 and the 5th diffusion barrier adhesion layer 438 is tantalum and tantalum nitride.The thickness concrete example of the first diffusion barrier adhesion layer 406 is as 150 dusts, 170 dusts, 190 dusts, 200 dusts, 210 dusts, 230 dusts or 250 dusts; The thickness concrete example of the second diffusion barrier adhesion layer 412, the 3rd diffusion barrier adhesion layer 419, the 4th diffusion barrier adhesion layer 430 and the 5th diffusion barrier adhesion layer 438 is as 200 dusts, 220 dusts, 250 dusts, 280 dusts or 300 dusts.

In the present embodiment, the material of the first metal layer 408 is a tungsten; The material of second metal level 414 and the 3rd metal level 422 is a copper.

In the present embodiment, the material of first etching stopping layer 410, second etching stopping layer 416, the 3rd etching stopping layer 424 and the 4th etching stopping layer 432 is silicon nitrides.The thickness concrete example of first etching stopping layer 410, second etching stopping layer 416, the 3rd etching stopping layer 424 and the 4th etching stopping layer 432 is as 300 dusts, 350 dusts, 400 dusts, 450 dusts or 500 dusts; The thickness concrete example of the 5th etching stopping layer 339 is as 500 dusts, 550 dusts, 600 dusts, 650 dusts or 700 dusts.

In the present embodiment, the thickness concrete example of silicon oxide layer 440 is as 2000 dusts, 2500 dusts, 3000 dusts, 3500 dusts or 4000 dusts.

In the present embodiment, the thickness concrete example of silicon oxynitride layer 442 is as 2000 dusts, 2500 dusts, 3000 dusts, 3500 dusts or 4000 dusts.

In the present embodiment, the thickness of hard mask 443 is 4000 dust to 5000 dusts, and concrete thickness is 4000 dusts, 4200 dusts, 4400 dusts, 4600 dusts, 4800 dusts or 5000 dusts for example.

In the present embodiment, the temperature of photoresist layer 444 is 200 ℃ to 300 ℃ after the heat treatment, and actual temp is 200 ℃, 250 ℃ or 300 ℃.

Cmos image sensor, comprise silicon substrate, be positioned at some etching stopping layer and insulating barrier combinations on the silicon substrate with dual-damascene structure, be positioned at the etching stopping layer that does not contain dual-damascene structure on the insulating barrier that last one deck has dual-damascene structure, be positioned at the silicon oxide layer on the etching stopping layer that does not contain dual-damascene structure and be positioned at silicon oxynitride layer on the silicon oxide layer, also comprise: opening, run through silicon oxynitride layer, silicon oxide layer, the etching stopping layer that does not contain dual-damascene structure and insulating barrier combination; Lenticule, be formed at etching stopping layer that open bottom comprises dual-damascene structure with insulating barrier combination go up and be corresponding with the image sensing area photoelectric diode.

Continue with reference to figure 4E, cmos image sensor comprises: silicon substrate 40; Peripheral circuit region 401 and image sensing district 400 are arranged in silicon substrate 40, and 400 both sides, image sensing district are peripheral circuit region 401, comprise photodiode 402 and the transistor 403 that is connected with photodiode in the image sensing district 400; First insulating barrier 404 is formed on the silicon substrate 40, and contact hole 407 runs through first insulating barrier 404, and contact hole 407 sidewalls and bottom are coated with the first diffusion barrier adhesion layer 406; First etching stopping layer 410 is covered on first insulating barrier 404, second insulating barrier 411 is formed on first etching stopping layer 410, groove 413 runs through second insulating barrier 411 and first etching stopping layer 410, be communicated with contact hole 407, groove 413 sidewalls and bottom are coated with the second diffusion barrier adhesion layer 412; Second etching stopping layer 416 is covered on second insulating barrier 411, the 3rd insulating barrier 418 is formed on second etching stopping layer 416, first dual-damascene structure 420 runs through the 3rd insulating barrier 418 and second etching stopping layer 416, be communicated with groove 413, first dual-damascene structure, 420 sidewalls and bottom are coated with the 3rd diffusion barrier adhesion layer 419; The 3rd etching stopping layer 424 is covered on the 3rd insulating barrier 418, the 4th insulating barrier 426 is formed on the 3rd etching stopping layer 424,428 of second dual-damascene structures are positioned at peripheral circuit region 401 and run through the 4th insulating barrier 426 and the 3rd etching stopping layer 424, be communicated with first dual-damascene structure 420, second dual-damascene structure, 428 sidewalls and bottom are coated with the 4th diffusion barrier adhesion layer 430; The 4th etching stopping layer 432 is covered on the 4th insulating barrier 426, the 5th insulating barrier 434 is formed on the 4th etching stopping layer 432,436 of the 3rd dual-damascene structures are positioned at peripheral circuit region 401 and run through the 5th insulating barrier 434 and the 4th etching stopping layer 432, be communicated with second dual-damascene structure 428, the 3rd dual-damascene structure 436 sidewalls and bottom are coated with the 5th diffusion barrier adhesion layer 438; The 5th etching stopping layer 439 is covered on the 5th insulating barrier 434; Silicon oxide layer 440 is positioned on the 5th etching stopping layer 439; Silicon oxynitride 442 is positioned on the silicon oxide layer 440; Opening 443 is positioned at image sensing district 400 and runs through silicon oxynitride layer 442, silicon oxide layer 440, the 5th etching stopping layer 439, the 5th insulating barrier 434, the 4th etching stopping layer 432 and the 4th insulating barrier 426 to exposing the 3rd etching stopping layer 424; Lenticule 446 is positioned at the 3rd etching stopping layer 424 and corresponding with photodiode 302.

Though the present invention with preferred embodiment openly as above; but it is not to be used for limiting the present invention; any those skilled in the art without departing from the spirit and scope of the present invention; can make possible change and modification, so protection scope of the present invention should be as the criterion with the scope that claim of the present invention was defined.

Claims

1. the manufacture method of a cmos image sensor, comprise: on silicon substrate, form some etching stopping layer and insulating barrier combinations successively with dual-damascene structure, in the end one deck has on the insulating barrier of dual-damascene structure and has formed the etching stopping layer that does not contain dual-damascene structure, form silicon oxide layer and silicon oxynitride layer again, it is characterized in that the image sensing district forms and comprises the following steps:

A. on silicon oxynitride layer, form the patterning photoresistance;

2. the manufacture method of cmos image sensor according to claim 1, it is characterized in that: with dry etching method etching silicon oxynitride layer, silicon oxide layer, do not contain dual-damascene structure etching stopping layer to exposing the etching stopping layer that comprises dual-damascene structure, form opening.

3. the manufacture method of cmos image sensor according to claim 2 is characterized in that: form photic zone with spin-coating method on silicon oxynitride layer, and photic zone is filled the full gate mouth.

4. the manufacture method of cmos image sensor according to claim 3, it is characterized in that: the thickness of described photic zone on silicon oxynitride layer is 0.3um to 0.8um.

5. the manufacture method of cmos image sensor according to claim 4, it is characterized in that: euphotic material is an acrylic resin.

6. according to the manufacture method of each described cmos image sensor of claim 1 to 5, it is characterized in that: described lenticular thickness is 0.8um to 1.2um.

7. the manufacture method of cmos image sensor according to claim 1, it is characterized in that: steps d comprises: form resin bed on photic zone;

Through overexposure and development, on the resin bed above the opening iuuminting layer, form and the corresponding microlens pattern of image sensing area photoelectric diode;

The heating resin bed.

8. the manufacture method of cmos image sensor according to claim 7 is characterized in that: form resin bed with spin-coating method.

9. the manufacture method of cmos image sensor according to claim 8 is characterized in that: the temperature of heating resin bed is 200 ℃ to 300 ℃.

10. the manufacture method of a cmos image sensor, comprise: on silicon substrate, form some etching stopping layer and insulating barrier combinations successively with dual-damascene structure, in the end one deck has on the insulating barrier of dual-damascene structure and has formed the etching stopping layer that does not contain dual-damascene structure, form silicon oxide layer and silicon oxynitride layer again, it is characterized in that the image sensing district forms and comprises the following steps:

A. on silicon oxynitride layer, form the patterning photoresistance;

C. on silicon oxynitride layer, form photic zone with the opening inwall;

11. the manufacture method of cmos image sensor according to claim 10, it is characterized in that: with dry etching method etching silicon oxynitride layer, silicon oxide layer, do not contain dual-damascene structure etching stopping layer to exposing the etching stopping layer that comprises dual-damascene structure, form opening.

12. the manufacture method of cmos image sensor according to claim 11 is characterized in that: on silicon oxynitride layer, reach the opening inwall with spin-coating method and form photic zone.

13. the manufacture method of cmos image sensor according to claim 12 is characterized in that: the photic zone uniform thickness of photic zone on the silicon oxynitride layer and opening inwall.

14. the manufacture method of cmos image sensor according to claim 13 is characterized in that: described euphotic thickness is 0.3um to 0.8um.

15. the manufacture method of cmos image sensor according to claim 14 is characterized in that: euphotic material is an acrylic resin.

16. the manufacture method according to each described cmos image sensor of claim 10 to 15 is characterized in that: described lenticular thickness is 0.8um to 1.2um.

17. the manufacture method of cmos image sensor according to claim 10 is characterized in that: step D comprises: on the photic zone of open bottom, form resin bed;

Through overexposure and development, on resin bed, form and the corresponding microlens pattern of image sensing area photoelectric diode;

The heating resin bed.

18. the manufacture method of cmos image sensor according to claim 17 is characterized in that: form resin bed with spin-coating method.

19. the manufacture method of cmos image sensor according to claim 18 is characterized in that: the temperature of heating resin bed is 200 ℃ to 300 ℃.

20. cmos image sensor that forms by the manufacture method of claim 10, comprise silicon substrate, be positioned at some etching stopping layers with dual-damascene structure and insulating barriers combination on the silicon substrate, be positioned at the etching stopping layer that does not contain dual-damascene structure on the insulating barrier that last one deck has dual-damascene structure, be positioned at the silicon oxide layer on the etching stopping layer that does not contain dual-damascene structure and be positioned at silicon oxynitride layer on the silicon oxide layer, it is characterized in that, also comprise:

Opening runs through silicon oxynitride layer, silicon oxide layer, does not contain the etching stopping layer of dual-damascene structure;

Photic zone is formed on the silicon oxynitride layer and the opening inwall;

Lenticule is formed on the open bottom photic zone and corresponding with the image sensing area photoelectric diode.

21. cmos image sensor according to claim 20 is characterized in that: on silicon oxynitride layer, reach the opening inwall with spin-coating method and form photic zone.

22. cmos image sensor according to claim 21 is characterized in that: the photic zone uniform thickness of photic zone on the silicon oxynitride layer and opening inwall.

23. cmos image sensor according to claim 22 is characterized in that: described euphotic thickness is 0.3um to 0.8um.

24. cmos image sensor according to claim 23 is characterized in that: euphotic material is an acrylic resin.

25. according to each described cmos image sensor of claim 20 to 24, it is characterized in that: described lenticular thickness is 0.8um to 1.2um.

26. the manufacture method of a cmos image sensor, comprise: on silicon substrate, form some etching stopping layer and insulating barrier combinations successively with dual-damascene structure, in the end one deck has on the insulating barrier of dual-damascene structure and has formed the etching stopping layer that does not contain dual-damascene structure, form silicon oxide layer and silicon oxynitride layer again, it is characterized in that the image sensing district forms and comprises the following steps:

On silicon oxynitride layer, form photoresist layer;

Through overexposure, development and heat treatment, on photoresist layer, form the lenticule figure;

Etching photoresist layer, silicon oxynitride layer, silicon oxide layer, do not contain dual-damascene structure etching stopping layer to exposing etching stopping layer and the insulating barrier combination that comprises dual-damascene structure, form opening;

The etching stopping layer and the insulating barrier that comprise dual-damascene structure in open bottom make up formation and the corresponding lenticule of image sensing area photoelectric diode.

27. the manufacture method of cmos image sensor according to claim 26 is characterized in that: etching silicon oxynitride layer, silicon oxide layer, the method that does not contain the etching stopping layer of dual-damascene structure are the dry etching method.

28. the manufacture method according to claim 26 or 27 described cmos image sensors is characterized in that: described lenticular thickness is 0.8um to 1.2um.

29. cmos image sensor that forms by the manufacture method of claim 26, comprise silicon substrate, be positioned at some etching stopping layer and insulating barrier combinations on the silicon substrate with dual-damascene structure, be positioned at the etching stopping layer that does not contain dual-damascene structure on the insulating barrier that last one deck has dual-damascene structure, be positioned at the silicon oxide layer on the etching stopping layer that does not contain dual-damascene structure and be positioned at silicon oxynitride layer on the silicon oxide layer, it is characterized in that, also comprise:

Lenticule, be formed at etching stopping layer that open bottom comprises dual-damascene structure with insulating barrier combination go up and be corresponding with the image sensing area photoelectric diode.

30. cmos image sensor according to claim 29 is characterized in that: described lenticular thickness is 0.8um to 1.2um.