CN101162715A - Substrates bar, substrate structure and manufacturing method thereof - Google Patents
Substrates bar, substrate structure and manufacturing method thereof Download PDFInfo
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- CN101162715A CN101162715A CNA200610135913XA CN200610135913A CN101162715A CN 101162715 A CN101162715 A CN 101162715A CN A200610135913X A CNA200610135913X A CN A200610135913XA CN 200610135913 A CN200610135913 A CN 200610135913A CN 101162715 A CN101162715 A CN 101162715A
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Abstract
The invention discloses a baseplate structure and a manufacturing method of the same. The baseplate structure at least comprises a kernel baseplate, a layer adding part and a solder mask, wherein, the kernel baseplate comprises a top surface and a bottom surface corresponding to the top surface, the top surface is provided with a circuitry pattern, the layer adding part is arranged on the top surface, wherein, the layer adding surface at least comprises a surface dielectric layer and a surface circuitry layer positioned on the surface circuitry layer, the surface circuitry layer is electrically connected to the circuitry pattern, the solder mask is arranged on the layer adding part, wherein, the solder mask is provided with at least one hole for identifying the baseplate structure.
Description
[technical field]
The present invention relates to a kind of substrate strip and board structure with and manufacture method, particularly relevant for a kind of substrate strip with identification sign and board structure with and manufacture method.
[background technology]
In today of social informatization high development, be the many-sided requirements such as high speed processingization, multifunction, productive setization and miniaturization and that meet electronic installation, the manufacture of semiconductor technology is also constantly towards microminiaturization and densification development.In order to dwindle encapsulation volume, improve the functional of potted element, such as covering crystalline substance (Flip chip, FC) encapsulation, ball pin trellis array (Ball Grid Array, BGA) encapsulation and chip size packages (ChipScalePackage, CSP) etc. advanced encapsulation technology now widely industrial circle utilize, wherein base plate type carrier (substrate type carrier) is the packaging element that often uses in the above-mentioned advanced encapsulation technology owing to have advantages such as wiring is fine and closely woven, assembling is compact and functional.
Please refer to shown in Figure 1ly, it has drawn the plan structure schematic diagram of existing a kind of base plate for packaging bar.Base plate for packaging bar 100 can be a multi-layer sheet, and it comprises several base board units 110 and a substrate frame 120 that disposes around base board unit 110.Wherein, each base board unit 110 is defined as encapsulation region, and it can engage with chip (not shown) via encapsulation procedure and form encapsulating structure (not shown).Relatively, substrate frame 120 is defined as non-encapsulation region, and be to have several long and narrow seams 130 between base board unit 110 and the substrate frame 120,, partly be linked to substrate frame 120 and make base board unit 110 only have so that base board unit 110 and substrate frame 120 are separated.After encapsulation procedure is finished, can carry out a separable programming, make base board unit 110 separate, and form the encapsulating structure (not shown) of several independent with substrate frame 120.Generally speaking, on the substrate frame 120 of base plate for packaging bar 100, has an identification sign 140, in order to the manufacturing lot number and relevant processing procedure data of discerning this base plate for packaging bar 100, so when the quality of base plate for packaging bar 100 has problem, can find out the historical summary of all manufacture processes of this base plate for packaging bar 100 by this identification sign 140, so just can differentiate the reason of problem generation and fault is got rid of (Trouble shooting).Yet, in case this base plate for packaging bar 100 is with chip join and after finishing encapsulation procedure, owing to can carry out separable programming so that base board unit 110 is separated with substrate frame 120, when the quality of the encapsulating structure of the several independent after if separate this moment has problem, just have no way of learning these independently the employed base plate for packaging bar 100 of encapsulating structure be which makes lot number, the problem that degree of difficulty increases and the product yield descends that causes processing procedure monitoring and fault to get rid of easily.
Therefore, be starved of a kind of improved base plate for packaging bar, solve the problem that in existing processing procedure, is difficult to process variation monitor and fault eliminating, to reach the purpose that promotes product quality and process rate.
[summary of the invention]
One of purpose of the present invention is to provide a kind of board structure, by directly being made in identification sign on the board structure, discern each board structure, so just can both carry out the processing procedure monitoring and get rid of, and improve the product yield with fault to each board structure.
Two of purpose of the present invention is to provide a kind of substrate strip, by identification sign directly being made on the base board unit of substrate strip, discern each base board unit, so just can be after finishing encapsulation procedure, can also monitor the quality of each base board unit, and in time fix a breakdown, thereby improve the product yield.
Three of purpose of the present invention is to provide a kind of manufacture method of board structure, and it forms at least one hole by increasing by a boring step on welding resisting layer, thereby can produce the board structure with identification sign.
For reaching one of above-mentioned purpose, the present invention adopts following technical scheme: a kind of board structure, it includes a core substrate, one first at least and increases layer portion and one first welding resisting layer, wherein core substrate comprises that at least a top surface reaches the basal surface with respect to this top surface, has one first line pattern on this top surface; First increases on the top surface that layer portion be arranged on core substrate, this first increases the first surface line layer that layer portion comprises a first surface dielectric layer at least and be positioned at this first surface dielectric layer top, and the first surface line layer is to be electrically connected to first line pattern; First welding resisting layer is to be arranged at this first to increase in layer portion, has at least one hole in order to the identification board structure on first welding resisting layer.
For reaching two of above-mentioned purpose, the present invention adopts following technical scheme: a kind of substrate strip, this substrate strip includes the periphery that several base board units and are surrounded on these base board units at least and is used for fixing the frame that supports these base board units, each base board unit all includes a core substrate, one first at least and increases layer portion and one first welding resisting layer, wherein core substrate comprises that at least a top surface reaches the basal surface with respect to top surface, has one first line pattern on top surface; One first increases layer portion is arranged on the top surface of core substrate, this first increases the first surface line layer that layer portion comprises a first surface dielectric layer at least and be positioned at first surface dielectric layer top, and the first surface line layer is to be electrically connected to first line pattern; First welding resisting layer is to be arranged at first to increase in layer portion, has at least one hole in order to the identification board structure on first welding resisting layer.
For reaching three of above-mentioned purpose, the present invention adopts following technical scheme: a kind of manufacture method of board structure, its manufacturing step includes at least: step (a) provides a core substrate, and this core substrate comprises that at least a top surface reaches the basal surface with respect to top surface, has one first line pattern on top surface; Step (b) is to form one first to increase a layer portion on the top surface of core substrate, forms this first step that increases layer portion and will comprise at least: form a first surface dielectric layer on first line pattern; And form a first surface line layer on the first surface dielectric layer, and the first surface line layer is to be electrically connected to first line pattern; Step (c) is to increase first to form one first welding resisting layer in layer portion; And step (d) is to form at least one hole on first welding resisting layer.
According to preferred embodiment of the present invention, above-mentioned hole is the top that is positioned at the first surface line layer, and exposed portions serve first surface line layer, and the shape of hole can be numeral, literal or pattern, is used for discerning board structure.
Compared to prior art, because the present invention directly is produced on identification sign on the base board unit, can guarantee like this when encapsulation procedure is finished, still can discern the manufacturing lot number of the base board unit in the encapsulating structure, with processing procedure monitoring that solves encapsulating structure and the problem that degree of difficulty increases and the product yield descends that fault is got rid of.In addition, owing to be under the prerequisite of the main manufacturing process that does not change existing board structure, by increasing by a boring step, thereby on welding resisting layer, form at least one hole, be used as discerning the mark of board structure by this hole.So the present invention compares with manufacture method with other existing board structure, the disclosed board structure of the present invention not only can carry out the processing procedure monitoring to be got rid of with fault, improves the product yield, more can significantly reduce the time and the cost of manufacturing.In addition, use manufacture of substrates of the present invention more can produce board structure not needing to change existing main processing procedure framework with identification sign.
[description of drawings]
Fig. 1 is a plan structure schematic diagram of having drawn existing a kind of base plate for packaging bar.
Fig. 2 A to Fig. 2 J is the manufacturing process of the preferred embodiment of board structure according to the present invention and the substrate cross-sectional view of drawing.
Fig. 3 is the preferred embodiment of the substrate strip according to the present invention and its plan structure schematic diagram of drawing.
[embodiment]
See also shown in Fig. 2 A to Fig. 2 J, it mainly is the manufacturing process of the preferred embodiment of board structure according to the present invention and the generalized section of drawing.
At first, shown in Fig. 2 A, one core substrate 200 is provided, and it has top surface 200a and with respect to the basal surface 200b of top surface 200a, wherein respectively has a line pattern 210,212 (i.e. first line pattern and second line pattern) on top surface 200a and the basal surface 200b.Have at least one via (not indicating) in the core substrate 200, be provided with a conductive layer 202 in the via, be used for electrically connecting line pattern 210 and 212, and be provided with a megohmite insulant 204 in order to clog this via.
Then, shown in Fig. 2 B, on top surface 200a and basal surface 200b, form inner layer dielectric layer 220,222 (i.e. first inner layer dielectric layer and second inner layer dielectric layer) respectively, to cover line pattern 210,212.In the present embodiment, inner layer dielectric layer 220 and 222 is to use the pressing method to form, and the material of inner layer dielectric layer 220 and 222 is ABF, and also not subject to the limits certainly, other dielectric material and formation method also can be used.
Then, shown in Fig. 2 C, on inner layer dielectric layer 220 and 222, form several interlayer holes 220a, 222a respectively, with the line pattern 210,212 of exposed portions serve.In the present embodiment, be to adopt the Laser drill method to form interlayer hole 220a, 222a, be not limited to this certainly, for example also can use other methods such as lithography or machine drilling.
Then, shown in Fig. 2 D, on inner layer dielectric layer 220 and 222, form internal layer circuit layer 230 and 232 (i.e. the first internal layer circuit layer and the second internal layer circuit layer) respectively, and fill up these interlayer holes 220a, 222a, in order to be electrically connected to line pattern 210,212.In the present embodiment, this internal layer circuit layer 230 and 232 formation method can include steps such as coating electric conducting material, coating photoresist and lithography.
Then, shown in Fig. 2 E, on internal layer circuit layer 230 and 232, form surface dielectric layer 240 and 242 (being first surface dielectric layer and second surface dielectric layer) respectively.In the present embodiment, surface dielectric layer 240 and 242 is to use ABF and forms in the mode of pressing, yet is not limited to this, and other dielectric material and formation method also can be used.
Then, shown in Fig. 2 F, on surface dielectric layer 240 and 242, form several interlayer holes 240a and 242a respectively.In the present embodiment, interlayer hole 240a, 242a are to use the Laser drill method to form, and are not limited to this equally, and other methods such as lithography or machine drilling also can be used.
Then, shown in Fig. 2 G, on surface dielectric layer 240 and 242, form surface lines layer 250 and 252 (being first surface line layer and second surface line layer) respectively, and fill up interlayer hole 240a, 242a.In the present embodiment, this surface lines layer 250 is to comprise actual have the line layer 250b of circuit interconnect function and the vacant figure 250a of any circuit interconnect function of tool (dummy pattern) not, so be not limited thereto, this surface lines layer 250 also can all be all actual line layer 250b with circuit interconnect function.The another kind of selection is, this vacant figure 250a also can be the armour metal layer that additionally is formed on any circuit interconnect function of not tool on the surface dielectric layer 240 with other method, can be used to guarantee the welding resisting layer 270 of follow-up covering on it when boring, the situation that does not have excessive boring takes place.What deserves to be mentioned is, inner layer dielectric layer 220 and 222, internal layer circuit layer 230 and 232, surface dielectric layer 240 and 242 and surface lines layer 250 and 252 can be layer portion 260,262 that increase that adopt existing Layer increasing method made (promptly first increase layer portion and second increase a layer portion), do not increase the interior line layer of layer portion 260,262 and the number of plies number of dielectric layer yet the present invention does not limit this.
Then, shown in Fig. 2 H, on surface lines layer 250 and 252, form welding resisting layer 270 and 272 (i.e. first welding resisting layer and second welding resisting layer) respectively, with protection surface lines layer 250 and 252.
Then, shown in Fig. 2 I, form at least one hole 270a on welding resisting layer 270, with the mark as the identification substrate, wherein this hole 270a is the top that is positioned at vacant figure 250a.In the present embodiment, utilize laser 280 to form hole 270a, be not limited thereto certainly, other methods such as lithography or machine drilling also can be used.What deserves to be mentioned is that this hole 270a can run through the vacant figure 250a of welding resisting layer 270 with exposing surface line layer 250, or armour metal layer, the another kind of selection be, this hole 270a also can be shown in Fig. 2 I does not run through welding resisting layer 270.
In the present embodiment, the shape of this hole 270a can be numeral, literal or pattern etc., shown in Fig. 2 J, in order to discern this substrate.
See also shown in Figure 3ly, it is the plan structure schematic diagram of the preferred embodiment of the substrate strip according to the present invention.This substrate strip 300 for example is a multi-layer sheet, and it comprises several base board units 310 and a frame 320, and this frame 320 is the peripheries that are surrounded on these base board units 310, and in order to these base board units 310 of fixed support.Wherein, each base board unit 310 is defined as encapsulation region, and it can engage with chip (not shown) via encapsulation procedure and form encapsulating structure (not shown).In the present embodiment, the structure of this base board unit 310 can be the board structure that is illustrated as Fig. 2 I.Relatively, frame 320 is defined as non-encapsulation region, and is to have several long and narrow seams 330 between base board unit 310 and the frame 320, so that base board unit 310 and frame 320 are separated, partly is linked to frame 320 thereby make base board unit 310 only have.The architectural feature of substrate strip 300 of the present invention is to be except have an identification sign 340 on frame 320, also has an identification sign 312 in addition on base board unit 310.In the present embodiment, this identification sign 312 is the hole 270a as shown in Fig. 2 I.Therefore, after encapsulation procedure is finished, use in the encapsulating structure of the several independent that substrate strip 300 of the present invention still can be after separation, the identification sign 312 of utilization on base board unit 310 found out the manufacturing lot number and relevant process data of the substrate strip 300 of original use, to reduce processing procedure monitoring and the degree of difficulty of fault eliminating and the yield that increases product.
In brief, substrate strip of the present invention, it is characterized in that directly being made in identification sign on the base board unit, can guarantee like this when encapsulation procedure is finished, still can discern the manufacturing lot number of the base board unit in the encapsulating structure, solve the problem that degree of difficulty increases and the product yield descends of processing procedure monitoring with the fault eliminating of encapsulating structure in this way.So compare with existing substrate strip, therefore substrate strip of the present invention monitored identification in arbitrary stage of encapsulation procedure effectively can significantly promote the quality of product and the fraction defective that reduces processing procedure.
By the invention described above preferred embodiment as can be known, use the manufacture method of board structure of the present invention, its advantage is to use same process apparatus, and under the manufacturing process that does not change existing board structure, by increasing by a boring step, and on welding resisting layer, form at least one hole, can produce board structure like this with identification sign.So compare with the manufacture method of existing board structure, the manufacture method of the board structure of the present invention in fact almost manufacture method with existing board structure is identical, under the framework that does not change existing processing procedure, can produce board structure with identification sign.
Claims (10)
1. board structure, it includes a core substrate, one first at least and increases layer portion and one first welding resisting layer, and wherein core substrate comprises a top surface at least and with respect to a basal surface of this top surface, has one first line pattern on this top surface; First increases on the top surface that layer portion be arranged on core substrate, this first increases the first surface line layer that layer portion comprises a first surface dielectric layer at least and be positioned at this first surface dielectric layer top, and the first surface line layer is to be electrically connected to first line pattern; First welding resisting layer is to be arranged at this first to increase in layer portion, it is characterized in that: have at least one hole in order to the identification board structure on first welding resisting layer.
2. board structure as claimed in claim 1 is characterized in that: the hole that is formed on first welding resisting layer is the top that is positioned at the first surface line layer, and exposed portions serve first surface line layer.
3. board structure as claimed in claim 1, it is characterized in that: first increases layer portion comprises that more at least an interlayer hole and is positioned at the armour metal layer of first surface dielectric layer top, the first surface line layer is to be electrically connected to first line pattern via interlayer hole, hole is the top that is positioned at armour metal layer, and can expose armour metal layer.
4. board structure as claimed in claim 1 is characterized in that: the shape of hole can be numeral, literal or pattern, is used for discerning this board structure.
5. board structure as claimed in claim 1 is characterized in that: have one second line pattern on the basal surface of core substrate, and first line pattern and second line pattern are that a via that sees through in the core substrate electrically connects; Increase layer portion and be arranged at second second welding resisting layer that increases in layer portion also being provided with second on the basal surface of core substrate, this second increases the second surface dielectric layer that layer portion comprises a second surface line layer at least and be positioned at the below of second surface line layer, and the second surface line layer is to be electrically connected to this second line pattern.
6. substrate strip, it includes the periphery that several base board units and are surrounded on these base board units at least and is used for fixing the frame that supports these base board units, each base board unit all includes a core substrate, one first at least and increases layer portion and one first welding resisting layer, wherein core substrate comprises that at least a top surface reaches the basal surface with respect to top surface, has one first line pattern on top surface; One first increases layer portion is arranged on the top surface of core substrate, this first increases the first surface line layer that layer portion comprises a first surface dielectric layer at least and be positioned at first surface dielectric layer top, and the first surface line layer is to be electrically connected to first line pattern; First welding resisting layer is to be arranged at first to increase in layer portion, it is characterized in that: have at least one hole in order to the identification board structure on first welding resisting layer.
7. substrate strip as claimed in claim 6 is characterized in that: the hole that is formed on first welding resisting layer is the top that is positioned at the first surface line layer, and exposed portions serve first surface line layer.
8. substrate strip as claimed in claim 6 is characterized in that: the shape of hole can be numeral, literal or pattern, is used for discerning board structure.
9. the manufacture method of a board structure, its manufacturing step includes at least: step (a) provides a core substrate, and this core substrate comprises a top surface at least and with respect to a basal surface of top surface, has one first line pattern on top surface; Step (b) is to form one first to increase a layer portion on the top surface of core substrate, forms this first step that increases layer portion and will comprise at least: form a first surface dielectric layer on first line pattern; And form a first surface line layer on the first surface dielectric layer, and the first surface line layer is to be electrically connected to first line pattern; Step (c) is to increase first to form one first welding resisting layer in layer portion; It is characterized in that: also have a step (d), it is to form at least one hole on first welding resisting layer.
10. the manufacture method of board structure as claimed in claim 9, wherein hole is the top that is positioned at the first surface line layer, the shape of hole can be numeral, literal or pattern, is used for discerning board structure.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB200610135913XA CN100552935C (en) | 2006-10-09 | 2006-10-09 | Substrate strip and board structure with and manufacture method |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB200610135913XA CN100552935C (en) | 2006-10-09 | 2006-10-09 | Substrate strip and board structure with and manufacture method |
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| Publication Number | Publication Date |
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| CN101162715A true CN101162715A (en) | 2008-04-16 |
| CN100552935C CN100552935C (en) | 2009-10-21 |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104900614A (en) * | 2014-03-05 | 2015-09-09 | 旺宏电子股份有限公司 | Semiconductor structure and manufacturing method thereof |
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- 2006-10-09 CN CNB200610135913XA patent/CN100552935C/en active Active
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104900614A (en) * | 2014-03-05 | 2015-09-09 | 旺宏电子股份有限公司 | Semiconductor structure and manufacturing method thereof |
| CN104900614B (en) * | 2014-03-05 | 2017-12-01 | 旺宏电子股份有限公司 | Semiconductor structure and its manufacture method |
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| Publication number | Publication date |
|---|---|
| CN100552935C (en) | 2009-10-21 |
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