CN101154683B - Transistor structure and its manufacturing method - Google Patents
Transistor structure and its manufacturing method Download PDFInfo
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- CN101154683B CN101154683B CN2006101421893A CN200610142189A CN101154683B CN 101154683 B CN101154683 B CN 101154683B CN 2006101421893 A CN2006101421893 A CN 2006101421893A CN 200610142189 A CN200610142189 A CN 200610142189A CN 101154683 B CN101154683 B CN 101154683B
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Abstract
The invention discloses a transistor structure, comprising a substrate, a first well region, a common source region and an anti-fuse structure. The first well region is provided with a first adulterant and is positioned in the substrate. The common source region is positioned in the first well region and comprises a slightly doped common source region and a heavy doped common source region which is positioned in the slightly doped region. The edge of the heavy doped common source region is at a distance form the edge of the slightly doped common source region basically. The anti-fuse structure is position on the common source region.
Description
Technical field
The present invention relates to a kind of transistor arrangement and manufacture method thereof, and particularly relate to a kind of have anti-fuse structures and two-step diffusion (double diffused drain, DDD) metal oxide semiconductor transistor (metal oxide semiconductor, MOS) structure and manufacture method thereof.
Background technology
Along with the progress of semiconductor technology, transistorized size is also constantly dwindled, many problems of therefore having derived.Wherein a problem is hot carrier's effect (hot carrier effect), just when transistorized operating voltage surpasses certain intensity, because powerful electric field accelerated electron impingement of electrons hole to and produce a large amount of charge carriers, make electric current in the transistorized passage heighten and produce electrical breakdown (electricalbreakdown) problem.The electronics that produces is inhaled the size of current that increases drain electrode toward drain electrode usually, and portions of electronics is injected in the grid oxic horizon and changed critical voltage (threshold voltage) and influence operating characteristic.The hole that produces will flow to substrate, and produce substrate current (substrate current), and another hole partly is then collected by source electrode, impels more charge carrier multiplication, and electrical breakdown takes place at last.Excessive electric current can make the easy deterioration of passage and reduce transistorized useful life.
Summary of the invention
In view of this, purpose of the present invention is providing a kind of transistor arrangement and manufacture method thereof exactly, proposes to have the metal oxide semiconductor transistor of two-step diffusion structure and anti-fuse structures, can operate and unlikely generation electrical breakdown by high voltage.
According to purpose of the present invention, a kind of transistor arrangement is proposed, comprise a substrate, one first well region, one source pole district and an anti-fuse structures.First well region has first alloy and is positioned at substrate.Source area is arranged in first well region, comprises a lightly-doped source polar region and a heavy-doped source polar region, and the heavy-doped source polar region is positioned at the lightly-doped source polar region.The edge of the edge of heavy-doped source polar region and lightly-doped source polar region keeps a distance basically.Anti-fuse structures is arranged on the source area.
According to purpose of the present invention, a kind of manufacture method of transistor arrangement is proposed, comprising: a substrate is provided; Form one and have first well region of first alloy in substrate; Form a lightly-doped source polar region and a lightly mixed drain area in substrate; Form one first insulating barrier and one second insulating barrier on substrate; Form a gate conductive structure and an anti-fuse conductive structure, gate conductive structure is positioned on first insulating barrier, and anti-fuse conductive structure is positioned on second insulating barrier; Form a heavy-doped source polar region and a heavily doped drain region, the heavy-doped source polar region is positioned at the lightly-doped source polar region, heavily doped drain region is positioned at lightly mixed drain area, the edge of the edge of heavy-doped source polar region and lightly-doped source polar region keeps one first distance, and the edge of heavily doped drain region and the edge of lightly mixed drain area keep a second distance.
According to purpose of the present invention, the manufacture method of another kind of transistor arrangement is proposed, comprising: a substrate is provided; Form one and have first well region of first alloy in substrate; Form second well region with second alloy in substrate, second well region is in abutting connection with first well region; Form one first insulating barrier and one second insulating barrier on substrate; Form a gate conductive structure and an anti-fuse conductive structure, gate conductive structure is positioned on first insulating barrier, and anti-fuse conductive structure is positioned on second insulating barrier, and second well region is positioned under the anti-fuse conductive structure; Form a lightly-doped source polar region and a lightly mixed drain area in substrate; Form a heavy-doped source polar region and a heavily doped drain region, the heavy-doped source polar region is positioned at the lightly-doped source polar region, heavily doped drain region is positioned at lightly mixed drain area, the edge of the edge of heavy-doped source polar region and lightly-doped source polar region keeps one first distance, and the edge of heavily doped drain region and the edge of lightly mixed drain area keep a second distance.
For above-mentioned purpose of the present invention, feature and advantage can be become apparent, several preferred embodiments cited below particularly, and conjunction with figs. are described in detail below.
Description of drawings
The structural representation of a kind of metal oxide semiconductor transistor of Fig. 1 embodiment of the invention one;
Fig. 2 A～2M illustrates the flow process profile of manufacture method of the metal oxide semiconductor transistor of the embodiment of the invention one;
Fig. 3 illustrates the step of manufacturing flow chart of the metal oxide semiconductor transistor of the embodiment of the invention one;
Fig. 4 illustrates the structural representation of a kind of metal oxide semiconductor transistor of the embodiment of the invention two;
Fig. 5 A～5M illustrates the flow process profile of manufacture method of the metal oxide semiconductor transistor of the embodiment of the invention two; And
Fig. 6 illustrates the step of manufacturing flow chart of the metal oxide semiconductor transistor of the embodiment of the invention two.
The simple symbol explanation
10,20: shielding layer
100,200: transistor arrangement
112: the first well regions
116: source area
118: the drain region
122: the first field oxides
124: the second field oxides
132,232: lightly mixed drain area
134,234: the lightly-doped source polar region
140,140a: first insulating barrier
150: the second insulating barriers
160: grid structure
162,172: polysilicon layer
164,174: metal level
166: the grid separation material
170: anti-fuse structures
176: anti-fuse separation material
180: the separation material material layer
192,292: heavily doped drain region
194,294: the heavy-doped source polar region
Embodiment
The present invention proposes to have the metal-oxide semiconductor (MOS) body transistor of DDD structure and anti-fuse structures, can higher voltage operates and electrical breakdown can not take place.Below elaborate with each embodiment respectively.
Embodiment one
Please refer to Fig. 1, it illustrates the structural representation of a kind of metal oxide semiconductor transistor of the embodiment of the invention one.Transistor arrangement 100 comprises substrate 110, first well region 112, source area 116 and anti-fuse structures 170.First well region 112 has first alloy and is positioned at substrate 110.Substrate 110 is a P type substrate in the present embodiment, and first alloy is a P type alloy, but the invention is not restricted to this.Source area 116 is arranged in first well region 112, comprises a lightly-doped source polar region 134 and a heavy-doped source polar region 194, and heavy-doped source polar region 194 is positioned at lightly-doped source polar region 134.The edge of the edge of heavy-doped source polar region 194 and lightly-doped source polar region 134 keeps a distance basically.
In addition, transistor arrangement 100 also comprises the drain region 118 that is arranged in first well region 112.Drain region 118 comprises lightly mixed drain area 132 and heavily doped drain region 192, and heavily doped drain region 192 is positioned at lightly mixed drain area 132.Transistor arrangement 100 also comprises first field oxide 122 and second field oxide 124, and source area 116 and drain region 118 are between first field oxide 122 and second field oxide 124.
In addition, edge and the edge of lightly-doped source polar region 134, the edge of heavily doped drain region 192 and the edge of lightly mixed drain area 132 of above-mentioned heavy-doped source polar region 194 keep a distance D 1 and a D2 respectively.Say that more carefully this distance refers to be parallel to the horizontal range of the first type surface of substrate 110.This distance is approximately more than or equal to 0.25 μ m, and less than half length of gate conductive structure, just approximates half length of the passage of 118 of source area 116 and drain regions.But in actual process, still must note lightly-doped source polar region 134 and lightly mixed drain area 132 whether too near and cause hot carrier's effect.In addition, the distance of heavy-doped source polar region 194 and heavily doped drain region 192 and second field oxide 124 and first field oxide 122 also preferably is respectively distance D 1 and distance D 2, makes transistor arrangement 100 have preferred operating reliability.
Therefore, heavy-doped source polar region 194 forms two-step diffusion (double diffused drain, DDD) structure with lightly-doped source polar region 134, heavily doped drain region 192 with lightly mixed drain area 132.This kind structure can be operated under high voltage and electrical breakdown can not taken place, and needing to go for the electronic product of high power operation.
In addition, comprise more preferably in the present embodiment that second well region, 114, the second well regions 114 with second alloy are positioned under the anti-fuse structures 170.Second alloy is a N type alloy in the present embodiment, and the alloy of lightly-doped source polar region 134, heavy-doped source polar region 194, lightly mixed drain area 132 and heavily doped drain region 192 is identical with second well region 114, but the invention is not restricted to this.
In addition, because the arrangement of sequence of process steps makes gate conductive structure be positioned on the lightly-doped source polar region 134 and lightly mixed drain area 132 partly of part, below introduce the manufacture method of the transistor arrangement 100 of present embodiment in the present embodiment.Please refer to Fig. 2 A～2M, it illustrates the flow process profile of manufacture method of the metal oxide semiconductor transistor of the embodiment of the invention one.And please be simultaneously with reference to Fig. 3, it illustrates the step of manufacturing flow chart of the metal oxide semiconductor transistor of the embodiment of the invention one.
At first, please refer to Fig. 2 A.Shown in step 301, provide a substrate 110.Then, shown in step 302, formation has first well region 112 of first alloy in substrate 110.Present embodiment forms patterned shielding and cooperates ion to inject with photoetching process, and P type alloy is injected P type substrate.
Then, please refer to Fig. 2 B.Shown in step 303, form second well region 114 with second alloy in substrate 110, second well region 114 is in abutting connection with first well region 112.Present embodiment forms patterned shielding and cooperates ion to inject with photoetching process, and N type alloy is injected P type substrate.
Then.Please refer to Fig. 2 C, form first field oxide 122 and second field oxide 124 on substrate 110.Field oxide for example is that (Tetraethylorthosilicate TEOS) for substrate, carries out the growth of field oxide in the oxidation boiler tube contains the environment of aqueous vapor with tetraethyl orthosilicate salt.
Then, please refer to Fig. 2 D.Shown in step 304, form lightly-doped source polar region 134 and lightly mixed drain area 132 in substrate 110.This step forms patterned shielding and cooperates ion to inject with photoetching process equally, and N type alloy is injected with low concentration.
Then, please refer to Fig. 2 E.Shown in step 305, form first insulating barrier 140 on substrate 110.
Then, please refer to Fig. 2 F.Shown in step 306, remove first insulating barrier 140 of part, to form the first insulating barrier 140a.This step can be carried out by photoetching process collocation etch process.
Then, please refer to Fig. 2 G.Form second insulating barrier 150 on substrate 110, and cover the first insulating barrier 140a, the thickness of second insulating barrier 150 is thin than the thickness of the first insulating barrier 140a.In the present embodiment, the thickness of the first insulating barrier 140a greater than 200 dusts (angstrom,
), the thickness of second insulating barrier 150 is less than 200
Then, please refer to Fig. 2 H.Shown in step 307, form gate conductive structure and anti-fuse conductive structure.Gate conductive structure is positioned on the first insulating barrier 140a and second insulating barrier 150, and anti-fuse conductive structure is positioned on second insulating barrier 150, and second well region 114 is positioned under the anti-fuse conductive structure.In the present embodiment gate conductive structure and anti-fuse conductive structure be respectively have polysilicon layer 162, metal level 164, and the double-decker of polysilicon layer 172, metal level 174.This step behind deposit spathic silicon material, the metal material (for example tungsten silicide), cooperates etching to form gate conductive structure and anti-fuse conductive structure with photoetching process in regular turn.
Then, please refer to Fig. 2 I.Shown in step 308, form the separation material material layer 180 of covered substrate 110, gate conductive structure and anti-fuse conductive structure.Separation material material layer 180 for example be tetraethyl orthosilicate salt (Tetraethylorthosilicate, TEOS).
Then, please refer to Fig. 2 J.Shown in step 309, remove the separation material material layer 180 of part, have the grid structure 160 of grid separation material 166 with formation, and have the anti-fuse structures 170 of anti-fuse separation material 176.
Then, please refer to Fig. 2 K.Shown in step 310, form a shielding layer 10 on first field oxide 122 and second field oxide 124.Shielding layer 10 for example is the formed photoresist layer of photoetching process.
Then, please refer to Fig. 2 L.Shown in step 311, form heavy-doped source polar region 194 and heavily doped drain region 192, to form source area 116 and drain region 118 respectively.Heavy-doped source polar region 194 is positioned at lightly-doped source polar region 134, and heavily doped drain region 192 is positioned at lightly mixed drain area 132.The edge of the edge of heavy-doped source polar region 194 and lightly-doped source polar region 134 keeps a distance D 1, and the edge of the edge of heavily doped drain region 192 and lightly mixed drain area 132 keeps a distance D 2.Distance D 1 and distance D 2 are the distances in the direction of the first type surface that is arranged essentially parallel to substrate 110, respectively approximately more than or equal to half length (just approximating the passage length of half) of 0.25 μ m and little this gate conductive structure.This step is shielding with shielding layer 10, grid structure 160 and anti-fuse structures 170, and the N type alloy that injects high concentration with ion forms heavy-doped source polar region 194 and heavily doped drain region 192.
At last, please refer to Fig. 2 M.Shown in step 312, remove shielding layer 10, finish transistor arrangement 100.
Yet, the those skilled in the art under the present invention, technology of the present invention as can be known is not limited thereto.For example, formed second well region 114 of step 303 can be strengthened the conducting property of source area 116, but this function can be reached by the DDD structure that lightly-doped source polar region 134 and heavy-doped source polar region 194 are formed.Therefore second well region 114 in the present embodiment can not need form.
Embodiment two
Please refer to Fig. 4, it illustrates the structural representation of a kind of metal oxide semiconductor transistor of the embodiment of the invention two.The main difference part of transistor arrangement 200 and the transistor arrangement 100 of embodiment one is the generation type of lightly-doped source polar region 234, heavy-doped source polar region 294, lightly mixed drain area 232 and heavily doped drain region 292.Because technologic sequence of steps difference, the distance D 3 that heavy-doped source polar region 294 and lightly-doped source polar region are 234, and the distance D 4 of 232 of heavily doped drain region 292 and lightly mixed drain areas is about 0.8 μ m between the 3.0 μ m.In addition, the distance of heavy-doped source polar region 294 and heavily doped drain region 292 and second field oxide 124 and first field oxide 122 also preferably is respectively distance D 3 and distance D 4, makes transistor arrangement 200 have preferred operating reliability.All the other components identical continue to continue to use its label, and no longer narrate its function.Below introduce the manufacture method of the transistor arrangement 200 of the embodiment of the invention two.Please refer to Fig. 5 A～5M, it illustrates the flow process profile of manufacture method of the metal oxide semiconductor transistor of the embodiment of the invention two.And please be simultaneously with reference to Fig. 6, it illustrates the step of manufacturing flow chart of the metal oxide semiconductor transistor of the embodiment of the invention two.
At first, please refer to Fig. 5 A.Shown in step 601, provide a substrate 110.Then, shown in step 602, formation has first well region 112 of first alloy in substrate 110.
Then, please refer to Fig. 5 B.Shown in step 603, second well region 114 that formation has second alloy is in substrate 110, and second well region 114 is in abutting connection with first well region 112.
Then, please refer to Fig. 5 C.Form first field oxide 122 and second field oxide 124 on substrate 110.
Then, please refer to Fig. 5 D.Shown in step 604, form first insulating barrier 140 on substrate 110.
Then, please refer to Fig. 5 E.Shown in step 605, remove first insulating barrier 140 of part, to form the first insulating barrier 140a.
Then, please refer to Fig. 5 F.Form second insulating barrier 150 on substrate 110, and cover the first insulating barrier 140a, the thickness of second insulating barrier 150 is thin than the thickness of the first insulating barrier 140a.In the present embodiment, the thickness of the first insulating barrier 140a is greater than 200
, the thickness of second insulating barrier 150 is less than 200
Then, please refer to Fig. 5 G.Shown in step 606, form gate conductive structure and anti-fuse conductive structure.Gate conductive structure is positioned on first insulating barrier on the 140a and second insulating barrier 150, and anti-fuse conductive structure is positioned on second insulating barrier 150, and second well region 114 is positioned under the anti-fuse conductive structure.
Then, please refer to Fig. 5 H.Shown in step 607, form lightly-doped source polar region 234 and lightly mixed drain area 232 in substrate 110.Transistor arrangement 100 differences with embodiment one, be that the below of gate conductive structure and anti-fuse conductive structure can not form the ion doping zone of lightly-doped source polar region 234 and lightly mixed drain area 232 because of the capture-effect of gate conductive structure and anti-fuse conductive structure.
Then, please refer to Fig. 5 I.Shown in step 608, form the separation material material layer 180 of covered substrate 110, gate conductive structure and anti-fuse conductive structure.
Then, please refer to Fig. 5 J.Shown in step 609, remove the separation material material layer 180 of part, to form grid structure 160 and anti-fuse structures 170.
Then, please refer to Fig. 5 K.Shown in step 610, form shielding layer 20 on first field oxide 122, second field oxide 124 and gate structure 160, and the substrate 110 of shielding layer 20 cover parts.
Then, please refer to Fig. 5 L.Shown in step 611, form heavy-doped source polar region 294 and heavily doped drain region 292.Heavy-doped source polar region 294 is positioned at lightly-doped source polar region 234, and heavily doped drain region 292 is positioned at lightly mixed drain area 232.The edge of the edge of heavy-doped source polar region 294 and lightly-doped source polar region 234 keeps a distance D 3, and the edge of the edge of heavily doped drain region 292 and lightly mixed drain area 232 keeps a distance D 4.Distance D 3 and distance D 4 are the distances in the direction of the first type surface that is arranged essentially parallel to substrate 110, and distance D 3 or distance D 4 are about 0.8 μ m between the 3.0 μ m.This step is shielding with shielding layer 20, gate conductive structure, grid separation material 166, anti-fuse conductive structure and anti-fuse separation material 176, injects with ion to form heavy-doped source polar region 294 and heavily doped drain region 292.
Then, please refer to Fig. 5 M.Shown in step 612, remove shielding layer 20, finish transistor arrangement 200.
In the transistor arrangement 200 of embodiment two, have bigger spacing between heavily doped region and the light doping section, therefore go for more high-tension operation.
Disclosed transistor arrangement of the above embodiment of the present invention and manufacture method thereof, proposition has the metal oxide semiconductor transistor of DDD structure and anti-fuse structures, can be used for carrying out the memory storage or the logic control element of high voltage operation.Because the characteristic of DDD structure can not produce electrical breakdown under high voltage operation, can prolong the transistorized life-span and improve reliability.
In sum; though the present invention discloses as above with preferred embodiment; yet it is not in order to limit the present invention; those skilled in the art without departing from the spirit and scope of the present invention; can do a little change and retouching, thus protection scope of the present invention should with accompanying Claim the person of being defined be as the criterion.
Claims (25)
1. transistor arrangement comprises:
Substrate;
Have first well region of first alloy, be positioned at this substrate;
Source area, be arranged in this first well region, this source area comprises lightly-doped source polar region and heavy-doped source polar region, this heavy-doped source polar region is positioned at this lightly-doped source polar region, and the edge of the edge of this heavy-doped source polar region and this lightly-doped source polar region keeps one first distance in the direction of the first type surface that is parallel to substrate; And
Anti-fuse structures is arranged on this source area,
Wherein, this heavy-doped source polar region is arranged at the both sides of this set position of anti-fuse structures at least.
2. transistor arrangement as claimed in claim 1, also comprise the drain region, be arranged in this first well region, this drain region comprises lightly mixed drain area and heavily doped drain region, this heavily doped drain region is positioned at this lightly mixed drain area, and the edge of this heavily doped drain region and the edge of this lightly mixed drain area keep a second distance.
3. transistor arrangement as claimed in claim 2 also comprises first field oxide and second field oxide, and this source area and this drain region are between this first field oxide and this second field oxide.
4. transistor arrangement as claimed in claim 2 also comprises grid structure, is arranged in this substrate and between this source area and this drain region.
5. transistor arrangement as claimed in claim 4, wherein this grid structure comprises gate conductive structure and grid separation material, this grid separation material coat this gate conductive structure around and this gate conductive structure of exposed portions serve.
6. transistor arrangement as claimed in claim 5, wherein this gate conductive structure is positioned on this lightly-doped source polar region and this lightly mixed drain area partly of part.
7. transistor arrangement as claimed in claim 5, wherein this gate conductive structure also comprises polysilicon layer and metal level, this metal level is arranged on this polysilicon layer.
8. transistor arrangement as claimed in claim 5, wherein this first distance or this second distance be approximately more than or equal to 0.25 μ m, and less than half length of this gate conductive structure.
9. transistor arrangement as claimed in claim 4, wherein this anti-fuse structures also comprises anti-fuse conductive structure and anti-fuse separation material, this anti-fuse separation material coat this anti-fuse conductive structure around and this anti-fuse conductive structure of exposed portions serve.
10. transistor arrangement as claimed in claim 9 also comprises first insulating barrier, and this first insulating barrier is between this grid structure and this substrate.
11. transistor arrangement as claimed in claim 10, wherein this anti-fuse structures also comprises second insulating barrier, and this second insulating barrier is between this anti-fuse conductive structure and this substrate, and the thickness of this first insulating barrier is greater than this second insulating barrier.
12. transistor arrangement as claimed in claim 1 also comprises second well region with second alloy, this second well region is positioned under this anti-fuse structures.
13. transistor arrangement as claimed in claim 2, wherein this first distance or this second distance are about 0.8 μ m between the 3.0 μ m.
14. the manufacture method of a transistor arrangement comprises:
(a) provide substrate;
(b) formation has first well region of first alloy in this substrate;
(c) form lightly-doped source polar region and lightly mixed drain area in this substrate;
(d) form first insulating barrier on this substrate, remove this first insulating barrier of part and form one second insulating barrier on this substrate;
(e) form gate conductive structure and anti-fuse conductive structure, this gate conductive structure is positioned on this first insulating barrier and this second insulating barrier, and this anti-fuse conductive structure only is positioned on this second insulating barrier; And
(f) form heavy-doped source polar region and heavily doped drain region, this heavy-doped source polar region is positioned at this lightly-doped source polar region, this heavily doped drain region is positioned at this lightly mixed drain area, the edge of the edge of this heavy-doped source polar region and this lightly-doped source polar region keeps first distance, the edge of this heavily doped drain region and the edge of this lightly mixed drain area keep second distance, and wherein this heavy-doped source polar region is arranged at the both sides of this set position of anti-fuse structures at least.
15. method as claimed in claim 14, in this step (b) and (C), this method also comprises:
(g) form have second alloy second well region in this substrate, this second well region is in abutting connection with this first well region, this second well region is positioned under this anti-fuse conductive structure; And
(h) form first field oxide and second field oxide on this substrate.
16. method as claimed in claim 14, in this step (e) and (f), this method also comprises:
(i1) formation one covers the separation material material layer of this substrate, this gate conductive structure and this anti-fuse conductive structure;
(i2) remove this separation material material layer partly, to form a grid structure and an anti-fuse structures; And
(j) form a shielding layer.
17. method as claimed in claim 16 in the step (f), is shielding with this shielding layer, grid structure and anti-fuse structures wherein, injects with ion to form those heavy-doped source polar regions and this heavily doped drain region.
18. method as claimed in claim 16 wherein also comprises after the step (f):
(k) remove this shielding layer.
19. method as claimed in claim 14, wherein in the step (f) this first distance or this second distance approximately more than or equal to 0.25 μ m, and less than half length of this gate conductive structure.
20. the manufacture method of a transistor arrangement comprises:
(a) provide substrate;
(b) formation has first well region of first alloy in this substrate;
(c) form have second alloy second well region in this substrate, this second well region is in abutting connection with this first well region;
(d) form first insulating barrier on this substrate, remove this first insulating barrier of part and form one second insulating barrier on this substrate;
(e) form gate conductive structure and anti-fuse conductive structure, this gate conductive structure is positioned on this first insulating barrier and this second insulating barrier, and this anti-fuse conductive structure only is positioned on this second insulating barrier, and this second well region is positioned under this anti-fuse conductive structure;
(f) form lightly-doped source polar region and lightly mixed drain area in this substrate; And
(g) form heavy-doped source polar region and heavily doped drain region, this heavy-doped source polar region is positioned at this lightly-doped source polar region, this heavily doped drain region is positioned at this lightly mixed drain area, the edge of the edge of this heavy-doped source polar region and this lightly-doped source polar region keeps one first distance, the edge of this heavily doped drain region and the edge of this lightly mixed drain area keep second distance, and wherein this heavy-doped source polar region is arranged at the both sides of this set position of anti-fuse structures at least.
21. method as claimed in claim 20, in this step (c) with (d), this method also comprises:
(h) form first field oxide and second field oxide on this substrate.
22. method as claimed in claim 20, in this step (f) with (g), this method also comprises:
(i1) form the separation material material layer that covers this substrate, this gate conductive structure and this anti-fuse conductive structure;
(i2) remove separation material material layer partly, to form a grid structure and anti-fuse structures; And
(j) form shielding layer on this first field oxide, this second field oxide and grid structure, and this substrate of this shielding layer cover part.
23. method as claimed in claim 22 in the step (g), is shielding with this shielding layer, this gate conductive structure and this anti-fuse conductive structure wherein, injects with ion to form this heavy-doped source polar region and this heavily doped drain region.
24. method as claimed in claim 22 wherein also comprises after the step (g):
(k) remove this shielding layer.
25. method as claimed in claim 22, wherein this first distance or this second distance are about 0.8 μ m between the 3.0 μ m in the step (g).
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| CN2006101421893A CN101154683B (en) | 2006-09-29 | 2006-09-29 | Transistor structure and its manufacturing method |
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| CN103456710B (en) * | 2012-06-04 | 2016-06-01 | 中芯国际集成电路制造(上海)有限公司 | MOS device and manufacture method thereof |
| US10090027B2 (en) * | 2016-05-25 | 2018-10-02 | Ememory Technology Inc. | Memory system with low read power |
| EP4203037A4 (en) * | 2021-01-22 | 2024-07-03 | Changxin Memory Tech Inc | Semiconductor structure and manufacturing method therefor |
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