CN101119155B

CN101119155B - Synchronous clock calibrating method of TD-SCDMA repeater

Info

Publication number: CN101119155B
Application number: CN200710151935XA
Authority: CN
Inventors: 刘道生; 林巍
Original assignee: Shenzhen hongyuan communication LLC
Current assignee: Shenzhen hongyuan communication LLC
Priority date: 2007-09-21
Filing date: 2007-09-21
Publication date: 2011-02-09
Anticipated expiration: 2027-09-21
Also published as: CN101119155A

Abstract

The present invention provides a method of synchronous clock correction for TD-SCDMA repeater. The method includes the steps as follows: calculating error statistics firstly; conducting even fluctuation processing to the synchronous counter according to error statistics so as to correct the synchronous counter. By adopting the method of synchronous clock correction of the invention, the local clocks will be conducted real-time correction, and the precision demand to crystal is 100ppm. At the same time, the real-time correction also eliminates the influence following the temperature, time and voltage.

Description

The method of a kind of TD-SCDMA repeater synchronous clock calibrating

Technical field

The present invention relates to a kind of clock synchronization Calibration Method, relate in particular to the method for a kind of TD-SCDMA repeater synchronous clock calibrating.

Background technology

TD-SCDMA is one of 3G (Third Generation) Moblie air interface technologies standard of the formal issue of the ITU of International Telecommunications Union.In the construction of TD-SCDMA net, TD-SCDMA is playing the part of the repeater important role.It is a kind of cost low, set up simple, have small base station function, cost-effective equipment.

Switch because of up-downgoing the TD-SCDMA repeater needs to solve stationary problem, and needs to guarantee clock source, repeater and base station clock source precise synchronization.The method for synchronous that adopts mainly contains the envelope detection method of synchronization, the baseband decoding method of synchronization and the GPS method of synchronization at present.The envelope detection and the baseband decoding method of synchronization provide the frame-synchronizing impulse of 5ms, and the GPS method of synchronization provides the lock-out pulse of 1s.

Under the existing situation of not doing clock alignment, the envelope detection method of synchronization, the baseband decoding method of synchronization can be selected for use＜crystal oscillator of 1ppm for guaranteeing synchronization accuracy, and stability (with the influence of temperature, time, voltage) is required also very high, when losing after, lock-out pulse has only the more crystal oscillator of high accuracy and stability of usefulness in order accurately to keep synchro switch a period of time.Must to reach the cost that 0.4ppm realizes bigger and the GPS method of synchronization will will be kept synchronization accuracy (1/2 chip) crystal oscillator precision in 1s.

Summary of the invention

The invention provides the method for a kind of TD-SCDMA repeater synchronous clock calibrating, this method comprises the steps: that (1) device power enters not synchronous regime; (2) after catching the successive frame lock-out pulse, enter presynchronization state, utilize lock-out pulse that local clock is done error statistics first; (3) after the error statistics value is finished first, enter synchronous regime, according to the error statistics value coincidence counter is done even increase and decrease bat processing and calibrate coincidence counter and regular update error statistics value; (4) after lock-out pulse is lost, enter the state of keeping, use the error statistics value of final updating to continue the calibration coincidence counter to keep synchro switch.

Adopt the method for synchronous clock calibrating of the present invention, the local Zhong Yuan (crystal oscillator) of real time calibration, 100ppm gets final product to the crystal oscillator required precision, and real time calibration has also been eliminated the influence with temperature, time, voltage simultaneously, has solved the problems referred to above.

Description of drawings

Fig. 1 is according to synchronous clock calibrating state transition diagram of the present invention;

Fig. 2 is according to error statistics of the present invention and calibration block diagram;

Fig. 3 is that process chart is clapped in even increase and decrease according to the present invention.

Embodiment

By understanding to the crystal oscillator characteristic, so-called precision is meant the accuracy under a certain specific environment, it can not change at short notice, and stability has comprised the variation that produces with temperature, time, voltage, various external environments influences such as aging, and this also is slow change procedure.So it is ageing that the error amount of adding up in several seconds time period has.The time span of specific embodiments of the invention statistic error value is 5.12s (1024 frame).Accurately keep the time span of synchro switch after the selection of the time span of statistic error value has determined lock-out pulse to lose, longer timing statistics length can obtain the longer length of holding time, but the stand-by period can be longer synchronously first, and the ageing of error amount can variation.

Count and just know behind the error amount and need the clock number that increases and decreases in the fixed time length, i.e. increase and decrease is clapped and is handled.Increase and decrease is clapped to handle can not concentrate on certain frame or a few frame and is increased and decreased, and will be evenly distributed in each frame, otherwise bigger shake can appear in synchronised clock and switch.

The TD-SCDMA repeater equipment is because to be subjected in short-term external interference etc. former thereby lose lock-out pulse, and this phenomenon can often take place when being in the complex environment operation in the repeater.After lock-out pulse is lost, the present invention will use last error statistics value to continue that local clock is done even increase and decrease and clap processing to keep synchro switch a period of time (time span of statistical error), during this period of time can guarantee synchronization accuracy.During this period of time, after lock-out pulse recovers, can proceed statistics and upgrade error amount, recover normal operating condition.During this period of time lock-out pulse does not recover then to withdraw from synchronous regime later, closes synchro switch.This lock-out pulse loses that to keep synchro switch a period of time processing method most important for the anti-interference in short-term in TD-SCDMA repeater.

In order to make the solution of the present invention clearer, the present invention is described in more detail below in conjunction with example.Specific embodiments of the invention are used the common active crystal oscillator square wave output of 20.48MHz, adopt the envelope detection method of synchronization, apply to the trunk amplifier in the TD-SCDMA repeater.

Fig. 1 is according to synchronous clock calibrating state transition diagram of the present invention.Whole synchronous clock calibrating flow process is divided into 4 states: 0 is synchronous regime not; 1 is presynchronization state; 2 is synchronous regime; 3 for keeping state.State transition takes place in a certain state under certain trigger condition.

At first the device power initial condition is 0 (promptly not synchronous regime), and 1 (being presynchronization state) gets the hang of after catching the successive frame lock-out pulse.

In presynchronization state, carry out the error statistics of 1024 frame durations first.Lose lock-out pulse during this period, then rebound state 1 (being presynchronization state) restarts.Finish when the error statistics of 1024 frame durations first, jump to state 2 (being synchronous regime) immediately.

Synchronous regime is a synchronous back normal and stable operation state.According to the error statistics value, promptly can evenly increase and decrease to clap and handle coincidence counter.Coincidence counter after obtaining calibrating will be exported synchronous diverter switch.In synchronous regime, proceed the error statistics of 1024 frame durations, simultaneously with regular update error statistics value.3 (promptly keeping state) get the hang of after losing lock-out pulse.

In keeping state,, just can not add up and upgrade the error statistics value owing to there is not lock-out pulse.The error statistics value that adopts final updating in synchronous regime is continued the calibration coincidence counter, keep synchronous diverter switch.For guaranteeing synchronous diverter switch precision, the longest 1024 frame durations that continue of the state of keeping.If during lock-out pulse recover, rebound state 2 (being synchronous regime) then, otherwise the overtime lock-out pulse that do not recover then jumps to state 0 (promptly not synchronous regime), indication equipment has really lost synchronously, gets back to initial condition and restarts.

Fig. 2 is according to error statistics of the present invention and calibration block diagram.It is the hardware block diagram that FPGA or CPLD realize.By 20.48MHz crystal oscillator, 4 frequency dividers, frame counter, error statistics counter, error amount latch, increase and decrease clap to handle, coincidence counter 7 parts form.

20.48MHz crystal oscillator produces the 5.12MHz clock through 4 frequency divisions.5.12MHz clock one tunnel is given the error statistics counter, coincidence counter is given on another road.The outside 5ms frame-synchronizing impulse incoming frame counter that produces carries out 1024 frame lengths counting.The error statistics counter is added up the number of the 5.12MHz clock that 1024 frames are comprised under the indication of frame counter, the standard value of clock is 25600 * 1024=26214400 when error free, and both subtract each other is exactly error amount.Per 1024 frames all upgrade error amount to error amount and latch.Error amount latchs and error amount is offered increase and decrease bat processing section again.Increase and decrease is clapped the processing section and is carried out even increase and decrease bat processing shown in Figure 3 according to error amount, is the calibration of unit with the frame to coincidence counter.

Coincidence counter is operated in the 5.12MHz clock, 25600 clocks of 1 frame count when error free.Increase and decrease is clapped and is handled on 25600 basis, makes the counter increase and decrease to reach calibration.Coincidence counter is exported synchronous diverter switch signal supply equipment and is carried out the up-downgoing switching.

Fig. 3 is that process chart is clapped in even increase and decrease according to the present invention.Error amount removes 1024 as shown in the figure, obtains B and remainder A.If B ≠ 0 represents that every frame all need increase and decrease B and clap.Remainder A is 10bit number, wherein A[9] be expressed as the 10th the bit position of remainder A, and the like, A[0] be expressed as the 1st the bit position of remainder A, A[m] m+1 the bit position of expression remainder A.In order to allow remainder A be evenly distributed on 1024 frames, adopted following algorithm assigns:

IfA[9]=1, per 2 frames add 1 to be clapped, and particular location is at the 2n+1 frame, n=0,1,2 ... 511;

IfA[8]=1, per 4 frames add 1 to be clapped, and particular location is at the 4n+2 frame, n=0,1,2 ... 255;

IfA[7]=1, per 8 frames add 1 to be clapped, and particular location is at the 8n+4 frame, n=0,1,2 ... 127;

IfA[6]=1, per 16 frames add 1 to be clapped, and particular location is at the 16n+8 frame, n=0,1,2 ... 63;

IfA[5]=1, per 32 frames add 1 to be clapped, and particular location is at the 32n+16 frame, n=0,1,2 ... 31;

IfA[4]=1, per 64 frames add 1 to be clapped, and particular location is at the 64n+32 frame, n=0,1,2 ... 15;

IfA[3]=1, per 128 frames add 1 to be clapped, and particular location is at the 128n+64 frame, n=0,1,2 ... 7;

IfA[2]=1, per 256 frames add 1 to be clapped, and particular location is in 256n+128 frame, n=0,1,2,3;

IfA[1]=1, per 512 frames add 1 to be clapped, and particular location is in 512n+256 frame, n=0,1;

IfA[0]=1, per 1024 frames add 1 to be clapped, and particular location is at 1024n+512 frame, n=0;

Above algorithm is summed up:

IfA[m]=1, every K frame adds 1 to be clapped, and particular location is at the K*n+K/2 frame

m＝0，1，2，……，9

K＝2 ^10-m

n＝0，1，……，(1024/K)-1。

Remainder A has guaranteed at most only to differ between frame and the frame 1 according to above-mentioned algorithm assigns and has clapped, and is evenly distributed, and makes synchronised clock and switch from fluttering minimum after the calibration.

Claims

1. the method for a TD-SCDMA repeater synchronous clock calibrating is characterized in that this method comprises the steps:

(1) device power enters not synchronous regime;

(2) after catching the successive frame lock-out pulse, enter presynchronization state, utilize lock-out pulse that local clock is done error statistics first;

(3) after the error statistics value is finished first, enter synchronous regime, according to the error statistics value coincidence counter is done even increase and decrease bat processing and calibrate coincidence counter and regular update error statistics value, described even increase and decrease is clapped and handled is that the remainder of error amount divided by the statistics frame length is assigned in the frame of appointment, it specifically comprises: if A[m]=1, every K frame adds 1 and claps, particular location is at K*n+K/2 frame, wherein A[m] m+1 the bit of expression remainder A; M=0,1,2 ..., 9; K=2 ^10-mN=0,1 ..., (1024/K)-1;

(4) after lock-out pulse is lost, enter the state of keeping, use the error statistics value of final updating to continue the calibration coincidence counter to keep synchro switch.

2. method according to claim 1 is characterized in that: the error statistics value is to add up the number of the clock that 1024 frames are comprised and error free standard time clock number by the error statistics counter under the indication of frame counter to subtract each other and obtain.