CN101090305A - Radio physical layer channel code chain processing method - Google Patents
Radio physical layer channel code chain processing method Download PDFInfo
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Abstract
This invention relates to a channel coding link process method of wireless physical layer including: carrying out Turbo coding to information block bit data, carrying out rate match to the Turbo coded code bit based on circulation buffer storage, and bit priority mapping modulation to the system bit stream and verified bit stream.
Description
Technical Field
The invention relates to wireless communication, in particular to a wireless physical layer channel coding link processing method.
Background
In a wireless communication system, a channel coding link is a bottom layer technology of a physical layer, and determines the bottom layer transmission performance and transmission reliability of the wireless communication system. In the latest 3GPP LTE standard research, a series of latest technologies are adopted for a channel coding link, which improves the physical layer transmission performance while simplifying the implementation complexity. Wherein: in the latest 3GPP standard protocol, Turbo code of a Quadratic Polynomial Permutation (QPP for short) interleaver is adopted as a channel coding scheme of data service; and adopting a rate matching method based on Circular Buffer to realize the matching of the length of the transmitted data and the size of the allocated physical channel resources. Meanwhile, high-order modulation modes such as 16QAM, 64QAM and the like are adopted to obtain higher spectrum utilization rate and peak transmission rate.
In addition, the bit-first mapping can be used as an enhancement technology adopted in a high-order modulation mode, and the coded system bits are modulated and mapped by adopting high-reliability constellation point bits in the high-order modulation, so that the system bits are protected more strongly, the decoding performance is improved, the throughput performance of a wireless link is improved, and the transmission delay is reduced. And at present, no channel coding link processing method adopting the four technologies simultaneously or no channel coding link processing method adopting the four technologies simultaneously is disclosed.
Disclosure of Invention
The technical problem to be solved by the invention is to provide a method for processing a wireless physical layer channel coding link, which enables system bits to obtain stronger protection and improves decoding performance compared with the prior art, thereby improving the throughput performance of a wireless link and reducing transmission delay.
The above technical problem of the present invention is solved by providing a method for processing a wireless physical layer channel coding link, comprising the following steps:
1.1) carrying out Turbo coding on information block bit data I;
1.2) carrying out rate matching on code word bits C after Turbo coding based on a circular cache;
1.3) carrying out bit priority mapping modulation on the system bit stream S and the check bit stream P which are output after rate matching.
According to the processing method provided by the present invention, the Turbo coding in step 1.1) is based on QPP interleaver, and step 1.1) includes the necessary padding sub-steps, that is: before encoding, firstly, judging whether the bit data size of the information block meets the bit data size requirement of a QPP interleaver, if not, filling a certain number of padding bits before the bit data of the information block, otherwise, not filling before the bit data of the information block.
According to the processing method provided by the present invention, the "pad" bit may be "0".
According to the processing method provided by the invention, the step 1.1) further comprises the following steps:
3.1) carrying out encoding of a Turbo code first member encoder on the information block bit data X subjected to the necessary filling processing, and outputting a first check bit stream Z;
3.2) carrying out interleaving processing based on a QPP interleaver on the information block bit data X after the necessary padding processing;
3.3) the output information block X 'bit data after the interleaving processing is coded by a second member coder of Turbo codes, and a second check bit stream Z' is output;
3.4) outputting tail bit sequences generated by the first member encoder and the second member encoder of the Turbo code;
3.5) multiplexing the processed information block bit data X, the first check bit stream Z, the second check bit stream Z' and the tail bit sequence to form a Turbo coded code word bit stream based on QPP interleaving.
According to the processing method provided by the invention, the step 1.2) can have two processing methods (namely: two rate matching algorithms), wherein:
the first processing method comprises the following steps:
4.1) carrying out bit separation on the code word bit stream C output by the Turbo coding to output a system bit stream S and a first check bit stream P1And a second parity bit stream P2；
4.2) the systematic bit stream S and the first check bit stream P which are output separately1And a second parity bit stream P2Respectively carrying out sub-block interleaving treatment;
4.3) systematic bit stream S after sub-block interleavingICheck bit stream P1 after sub-block interleavingICheck bit stream P2 after sub-block interleavingIAnd carrying out bit collection processing to form virtual circular buffer CB output.
And 4.4) determining and circularly reading the bits of the transmission data packet output by rate matching from the initial position in the virtual circular cache according to the value of the redundancy version and the length of the transmission HARQ data packet, judging according to the specific reading position, and if the bits are system bits, sequentially writing the bits into a rate matching output system bit stream, otherwise, sequentially writing the bits into a rate matching output check bit stream.
The second processing method (namely, the bit selection rate matching algorithm) comprises the following steps:
and 5.1) carrying out bit separation on the code word bit stream output by the Turbo coding to output a system bit stream, a first check bit stream and a second check bit stream.
And 5.2) determining and selecting the bits of the sending HARQ data packet which is output in a rate matching manner from the separately output system bit stream, the first check bit stream and the second check bit stream according to the value of the redundancy version and the length of the sending HARQ data packet, judging according to a specific reading position, and if the bits are the system bits, sequentially writing the bits into the rate matching output system bit stream, otherwise, sequentially writing the bits into the rate matching output check bit stream.
According to the processing method provided by the present invention, the second processing method (i.e. bit selection rate matching algorithm) specifically comprises:
6.1) carrying out bit separation on code word bits after Turbo coding to output a system bit stream, a first check bit stream and a second check bit stream with the length of L;
6.2) calculating that the separated system bit stream, the first check bit stream and the second check bit stream need to virtually add D-32 ceil (L/32) -L dummy bits on each data bit stream; the dummy bits are not actually added to each data bit stream, but due to the characteristics of the circular buffer rate matching algorithm, the effect of adding the dummy bits needs to be considered in the rate matching process.
6.3) carrying out rate matching processing on the system bit stream added with the virtual bits, the first check bit stream and the second check bit stream, carrying out bit selection from the three bit streams, and generating the system bit stream and the check bit stream corresponding to the HARQ data packet. If the stuffing bits exist, the separated system bit stream and the first check bit stream are processed by the stuffing bits removal.
According to the processing method provided by the invention, the step 6.3) comprises the following steps:
7.1) set the read total bit counter n to 0, read systematic bit counter nsysRead check bit counter n as 0par＝0；
7.2) judging whether the current output n +1 th bit is a systematic bit according to a circular cache rate matching algorithm, if the output bit is the systematic bit, determining according to a corresponding formula, reading out a non-padding bit according to the address A of the current selected bit in the input systematic bit stream, and writing the non-padding bit into the nth bit of the output systematic bit streamsysBit position, reading out total bit counter n and system bit counter n simultaneouslysysRespectively adding 1; determining whether bit calculator n has been reachedReading out the total bit number requirement of the HARQ packet, if so, finishing the rate matching algorithm, otherwise, continuing the rate matching algorithm;
7.3) according to the circular buffer rate matching algorithm, judging whether the current output n +1 th bit is a check bit, if the output bit is the check bit, alternately reading from the input first check bit stream and the second check bit stream, determining according to a corresponding formula, reading the 'filling' bit of the non-second check bit stream according to the address B of the current selected bit in the input first check bit stream or the input second check bit stream, and writing the bit into the nth bit of the output check bit streamparBit position, reading out total bit counter n and check bit counter n simultaneouslyparRespectively adding 1; and judging whether the read total bit counter n meets the requirement of reading the total number of the bits of the HARQ packet, if so, finishing the rate matching algorithm, and otherwise, continuing the rate matching algorithm.
According to the processing method provided by the invention, in the bit selection rate matching algorithm, when the 'dummy bit' in the step 6.2) is virtually placed in front of the separated system bit stream, the first check bit stream and the second check bit stream, the address a in the input system bit stream in the step 7.2) is represented as a ═ ColPerm (c) -D, and the address B in the input first check bit stream or the second check bit stream in the step 7.3) is represented as B ═ ColPerm (c/2-16) -D; wherein: ColPerm is the column permutation vector of the rate matching sub-block interleaving, c is the row number, and D is the number of 'virtual bits'.
According to the processing method provided by the present invention, in the bit selection rate matching algorithm, when the "dummy bit" in the step 6.2) is virtually placed behind the separate system bitstream, the first check bitstream and the second check bitstream, the address a in the input system bitstream in the step 7.2) is represented as a ═ ColPerm (c), and the address B in the input first check bitstream or the second check bitstream in the step 7.3) is represented as B ═ ColPerm (c/2-16); wherein: ColPerm is the column permutation vector of the rate matching sub-block interleaving, and c is the row number.
According to the processing method provided by the invention, the step 1.3) specifically comprises the following steps: and transmitting the data in the system bit stream by using high-reliability bits in a constellation diagram under a high-order modulation mode for the system bit stream and the check bit stream which are output after rate matching, so as to realize bit priority mapping. The specific implementation can be realized by adopting a bit collection interleaving method or a bit interleaving method, and the implementation method only needs to be included if the system bits are transmitted on the high-reliability constellation point bits as far as possible.
Specifically, the bit collection interleaving method is as follows:
and respectively setting the lengths of the rate matching output system bit stream and the check bit stream as Ls and Lp, and the modulation order of the adopted constellation diagram as M, wherein the bit collection interleaver is a rectangular interleaver with M rows, K ═ l + Lp and M columns.
The writing method adopted by the rectangular interleaver is as follows:
the method comprises the following steps: and writing the systematic bits from left to right according to the rows from the position of the upper left corner of the rectangular interleaver, and after writing one row, if the systematic bits are not written completely, continuing to write from left to right according to the rows from the position of the leftmost bottom of the rectangular interleaver. And writing the check bits from the right to the left of the right lower corner of the rectangular interleaver according to the rows, and after writing a row, if the check bits are not written completely, continuing to write from the right to the left of the last row according to the rows.
The method 2 comprises the following steps: and writing the systematic bits from left to right according to the rows from the position of the upper left corner of the rectangular interleaver, and after writing one row, if the systematic bits are not written, continuing to write from left to right according to the rows from the position of the leftmost of the next row. After the system bit is finished, the check bits are continuously written from left to right according to the row from the last written system bit, and after the row is written, if the check bits are not completely written, the check bits are continuously written from left to right according to the row from the leftmost position of the next row.
The method 3 comprises the following steps: the system/check bit writing method of bit collection (bit collection) in HSDPA rate matching is adopted, and the only difference is that only one check bit stream is needed in the invention, and the interleaving between two check bit streams is not needed.
The reading of the bit collection interleaver adopts the reading from left to right in columns, and the data in each column is read from top to bottom.
Specifically, the bit interleaving method completes the same function as the bit collection method, which is directly realized only by different interleaving methods of the system and the check bit stream, and the three bit collection methods can simply derive the interleaving method.
For the rectangular interleaving writing method 1, the corresponding bit interleaving method is as follows:
the systematic bits are directly written to an output buffer according to output address indexes 0, M, 2M, and 3M. And for the check bits, directly writing the check bits into an output buffer according to an output address index KM-1, (K-1) M-1, (K-2) M-1,. the.
According to the processing method provided by the invention, M continuous bits are grouped in a bit data stream output by bit collection interleaving or bit interleaving and are sequentially mapped into a constellation diagram, wherein the front bits in the M bits have high reliability relative to the rear bits, and the bits with high reliability are transmitted on the bits with high reliability in the constellation diagram.
According to the processing method provided by the present invention, the high-order modulation mode includes, but is not limited to, 8PSK, 16QAM, 64QAM, or 256 QAM.
The processing method provided by the invention can be used in digital wireless communication systems of various systems.
The invention provides a wireless physical layer channel coding link processing method, which adopts a bit priority mapping technology which accords with the technical development trend, and modulates and maps the coded system bits by high-order modulation high-reliability constellation point bits, so that the system bits can obtain stronger protection, the decoding performance is improved, the throughput performance of a wireless link is improved, and the transmission delay is reduced compared with the prior art.
Drawings
The invention is further described in detail below with reference to the figures and the specific embodiments.
FIG. 1 is a flow chart of a channel coding link processing method according to the present invention;
FIG. 2 is a diagram illustrating a circular buffer rate matching according to the method of FIG. 1;
FIG. 3 is a flowchart illustrating a second channel coding link processing method according to the present invention;
FIG. 4 is a schematic diagram of a QPP interleaving-based Turbo coding structure corresponding to the second method shown in FIG. 2;
FIG. 5 is a diagram illustrating a circular buffer rate matching corresponding to the second method shown in FIG. 2;
FIG. 6 is a flow chart of a system/parity bit selection algorithm with "dummy bits" added in front of the substreams in the bit selection rate matching algorithm of FIG. 5;
fig. 7 is a flow chart of the system/parity bit selection algorithm with "dummy bits" added to the back of the substreams in the bit selection rate matching algorithm shown in fig. 5.
Detailed Description
First, the present invention is explained by combining the working principles of two specific embodiments of the present invention for wireless physical layer channel coding link processing:
the first method comprises the following steps:
a channel coding link processing method according to the present invention, as shown in fig. 1, includes the following steps:
102) turbo coding is carried out on the information block bit data;
104) carrying out rate matching processing based on circular cache on the code word bits after Turbo coding, and outputting a system bit stream and a check bit stream; in the process of rate matching processing, the bits read from the circular cache are judged, if the read bits are system bits, the bits are sequentially written to a rate matching output system bit stream part, otherwise, the bits are sequentially written to a rate matching output check bit stream part;
106) and carrying out bit-first mapping modulation on the system bit stream and the check bit stream which are output based on the rate matching of the circular buffer.
Wherein, the rate matching processing based on the circular buffer in step 104), as shown in fig. 2, specifically includes the following five sub-steps:
(1) and carrying out bit separation operation on the code word bit stream output by the Turbo coding, and separating and outputting three data bit streams including the system bit stream, the first check bit stream and the second check bit stream.
(2) And respectively carrying out sub-block interleaving processing on the system bit stream, the first check bit stream and the second check bit stream which are separately output. The sub-block interleaving of the second parity bit stream has an offset with respect to the sub-block interleaving of the first parity bit stream, the systematic bit stream.
(3) And carrying out bit collection processing on the system bit stream after the sub-block interleaving processing, the first check bit stream after the sub-block interleaving processing and the second check bit stream after the sub-block interleaving processing to form virtual cycle cache output.
(4) And selecting the bits of the sending data packet which is output in a reading rate matching mode from a certain bit position in the output virtual circular cache according to the value of the redundancy version and the length of the sending data packet. And meanwhile, judging the data bits read out by the rate matching, if the data bits are system bits, sequentially writing the data bits into a rate matching output system bit stream, and otherwise, sequentially writing the data bits into a rate matching output check bit stream.
(II) method II:
a channel coding link processing method according to the present invention, as shown in fig. 3, includes the following steps:
302) performing padding operation on the information block bit data;
304) performing QPP interleaver-based Turbo coding on the information block bit data subjected to the padding operation;
306) carrying out rate matching processing based on a circular cache on code word bits after Turbo coding based on a QPP interleaver, and outputting a system bit stream and a check bit stream after the rate matching processing;
308) and carrying out bit priority mapping modulation on the system bit stream and the check bit stream which are output after the cyclic buffer rate matching processing.
Wherein,
in step 302), "padding" operation first determines whether the size of the information block bit data meets the requirements of the QPP interleaver in Turbo coding, if not, a certain number of "padding" bits, for example, 0 bit, are padded before the information block bit data, and if yes, 0 bit is padded in the "padding" operation.
In step 304, the QPP interleaver-based Turbo coding, as shown in fig. 4, includes the following sub-steps:
(1) coding the information block bit data after the filling operation by a first member coder of a Turbo code, and outputting a first check bit stream;
(2) carrying out interleaving processing based on a QPP interleaver on the information block bit data subjected to the padding operation;
(3) coding the 'filling' information block bit data output after QPP interleaving by a second member coder of Turbo codes, and outputting a second check bit stream;
(4) and outputting tail bit sequences generated by the first member encoder and the second member encoder of the Turbo code.
(5) And multiplexing the information block bit data after the padding operation, the first check bit stream, the second check bit stream and the tail bit sequence to form a Turbo coded code word bit stream based on QPP interleaving.
Step 306), a rate matching process based on circular buffer, as shown in fig. 5, includes the following sub-steps:
(1) and carrying out bit separation operation on the code word bits after Turbo coding, and separating and outputting three data bit streams including the system bit stream, the first check bit stream and the second check bit stream, wherein the lengths of the three data bit streams are L.
(2) Calculating the number D of 'virtual bits' which are needed to be added on each path of data bit stream in the circular cache rate matching algorithm by the separated system bit stream, the first check bit stream and the second check bit stream, wherein D is 32 ceil (L/32) -L. Specifically, the "dummy bits" may be added in front of each path of data bit stream or in the back of each path of data bit stream in the circular buffer rate matching sub-block interleaving process. The adding of dummy bits does not mean that D data bits are actually added, but only that D data bits are virtually added in the subsequent step, that is, the step is not an operation that actually exists.
(3) And performing rate matching and bit de-stuffing processing to generate a system bit stream and a check bit stream of a certain HARQ packet, wherein only the system bit stream and the first check bit stream are subjected to bit de-stuffing operation. The sub-step (3) processing specifically comprises the following three sub-steps:
(3a) setting the total read bit counter n to 0, and reading the system ratioSpecial counter nsysRead check bit counter n as 0par＝0。
(3b) Judging whether the current output n +1 th bit is a systematic bit according to a given circular cache rate matching algorithm, if the output bit is a systematic bit, determining the address A of the current selected bit in the input systematic bit stream according to a specific calculation formula, reading the systematic bit according to the address A, and writing the systematic bit into the nth bit of the output systematic bit streamsysBit position, reading out total bit counter n and system bit counter n simultaneouslysysRespectively adding 1. And judging whether the bit calculator n meets the requirement of reading out the total number of the bits of the HARQ packet, if so, finishing the rate matching algorithm, and otherwise, continuing the rate matching algorithm. If the current address A indicates 'filling bit' or 'dummy bit' added in rate matching subblock interleaving, the read-write operation is not performed, and n aresysAnd is not changed.
(3c) Judging whether the currently output (n + 1) th bit is a check bit according to a given circular cache rate matching algorithm, if the output bit is the check bit, alternately reading a check bit from the input first check bit stream and the input second check bit stream, more specifically, determining the address B of the currently selected bit in the input first check bit stream or the input second check bit stream according to a calculation formula of rate matching, reading the check bit according to the address B, and writing the bit to the nth bit stream of the output check bit streamparBit position, reading out total bit counter n and check bit counter n simultaneouslyparRespectively adding 1. And judging whether the read total bit counter n meets the requirement of reading the total number of the bits of the HARQ packet, if so, finishing the rate matching algorithm, and otherwise, continuing the rate matching algorithm. If the current address B indicates 'filling bits' in the first check bit stream or 'dummy bits' added in the rate matching subblock interleaving, the read-write operation is not performed, and n areparAnd is not changed.
Step 308), transmitting the data in the system bit stream by using the high-reliability bits in the constellation diagram in the 16QAM, 64QAM or 256QAM modulation mode for the system bit stream and the check bit stream generated in step 306), so as to implement bit-first mapping modulation.
Secondly, the present invention will be explained in detail by combining the two specific embodiments of the wireless physical layer channel coding link processing scheme of the present invention:
example one
Suppose an information block bit data sequence I (I)0，i1，…，iK-1) Where K is the information block bit data length, ikAnd (K is more than or equal to 0 and less than or equal to K-1) is binary bit data.
The information block bit data I is processed by Turbo coding, and a Turbo coding code word bit stream sequence C (C) is output0，c1，…c3×S-1)。
Performing bit separation operation on the Turbo code output code word bit stream sequence C to separate out a system bit stream sequence S (S)0，s1，…sS-1) First check bit stream sequence P1(p0 1，p1 1，…pS-1 1) And a second check bit stream sequence P2(p0 2，p1 2，…pS-1 2)。
Separated systematic bit stream sequence S and first check bit stream sequence P1And a second check bit stream sequence P2Respectively carrying out sub-block interleaving, and systematic bit stream sequence S after sub-block interleavingI(s0 I，s1 I，…，sS-1 I) Sub-block interleaved first parity bit stream sequence P1I(p10 I，p11 I，…，p1S-1 I) Sub-block interleaved second parity bit stream sequence P2I(p20 I，p21 I，…，p2S-1 I). Let pisys、πp1And pip2Respectively represent the separated system ratioAnd a sub-block interleaving processing function of the bit stream, the first check bit stream and the second check bit stream, wherein delta is a sub-block interleaving offset of the second check bit stream sequence relative to the first check bit stream sequence, and the systematic bit stream sub-block interleaving is respectively related to the first check bit stream sub-block interleaving and the second check bit stream sub-block interleaving as follows:
πp2(i)＝(πsys(i)+δ)％S (0≤i≤S-1)
πp1(i)＝πsys(i) (0≤i≤S-1)
systematic bit stream S after sub-block interleavingIThe first check bit stream sequence P1 after sub-block interleavingIAnd a second parity bit stream sequence P2IPerforming bit collection processing to form a virtual circular buffer CB (CB)0，cb1，…，cb3×S-1) The specific bit collection process is as follows:
cbk＝sk′ k＝0，1，…S-1
cbS+2×k＝p1k′ k＝0，1，…S-1
cbS+2×k+1＝p2k′ k＝0，1，…S-1
determining the starting position j (j is more than or equal to 0 and less than or equal to 3 multiplied by S-1) of the HARQ data packet to be sent read in the virtual circular cache according to the value of the redundancy version and the size of the virtual circular cache, and circularly reading the size of the starting position j from the virtual circular cache to be NdataAnd transmitting the bit data of the HARQ packet. Specifically, when the data of the sending data packet is read in the virtual circulation cache, the position k of the read bit data in the virtual circulation cache is judged, when the k is more than or equal to 0 and less than or equal to S-1, the read bit data are system bits, and the read bit data are sequentially written into an output system bit stream; and when the k is not less than S and not more than 3 multiplied by S-1, the read bit data are check bits, and the read bit data are sequentially written into the output check bit stream.
Under the modulation mode of 16QAM, 64QAM or 256QAM, the system bit stream and the check bit stream which are output by rate matching utilize high-reliability bits in a constellation diagram to transmit data in the system bit stream, thereby realizing bit priority mapping modulation.
(II) example II
If the information block bit data vector I (I)1，i2，…，iK) Where K is the information block bit data length, ikAnd (K is more than or equal to 1 and less than or equal to K) is binary bit data.
Since the QPP interleaving in the Turbo encoder does not support interleaving of continuous length information blocks, when the information block bit data length does not satisfy the QPP interleaving length requirement, a padding operation is required before the information block bit data to fill in "0" bits. The "padded" information block bit data vector X (X)1，x2，…，xS) Where S is the length of the information block bit data after "padding". Bits (X) in the "padded" information block bit data vector X1，x2，…xS-K) Is "0" bit data of "padding".
The information block bit data X after being filled is input into a Turbo encoder based on QPP interleaving for encoding, and the encoding is divided into the following five substeps: (1) inputting the information block bit data X after being filled into a first member encoder for encoding, and outputting a first check bit stream vector Z (Z)1，z2，…zS) (ii) a (2) The "padded" information block bit data X is input to a QPP interleaver for interleaving, and the "padded" information block bit data X' after QPP interleaving is output (X)1′，x2′，…xS'). (3) QPP interleaved ' filler ' information block bit data X ' is input into a second member encoder for encoding and output a second check bit stream vector Z ' (Z ' bit stream1′，z2′，…zS'). (4) Outputting tail bits generated by the first member encoder and the second member encoder, wherein the tail bit sequence is as follows: x is the number ofS+1，zS+1，xS+2，zS+2，xS+3，zS+3，xS+1′，zS+1′，xS+2′，zS+2′，xS+3′，zS+3'. (5) Multiplexing the information block bit data X after being filled, the first check bit stream sequence Z, the second check bit stream sequence Z' and the tail bit sequence to form a code word bit stream sequence after Turbo coding based on QPP interleaving, wherein the specific sequence is as follows:
x1，z1，z1′，x2，z2，z2′，…，xS，zS，zS′，xS+1，zS+1，xS+2，zS+2，xS+3，zS+3，xS+1′，zS+1′，xS+2′，zS+2′，xS+3′，zS+3' the codeword bit stream sequence length is 3 × S + 12.
The QPP interleaving-based code word bit stream sequence output by the Turbo coding is input into a rate matching module based on a circular cache for processing, and the processing mainly comprises the following substeps:
(1) bit stream sequence C (C) of code words input to the rate matching module1，c2，…c3×S+12) Performing a bit separation operation to separate a systematic bit stream sequence S (S)1，s2，…sS+4) First check bit stream sequence P1(p1 1，p2 1，…pS+4 1) And a second check bit stream sequence P2(p1 2，p2 2，…pS+4 2) And the length of each path of bit stream is S + 4. Input code word bit stream sequence C, system bit stream sequence S and first check bit stream sequence P1And a second check bit stream sequence P2The following relationships exist:
sk＝c3×(k-1)+1 k＝1，2，…S+4
(2) for the system bit stream sequence S and the first check bit stream sequence P1And a second check bit stream sequence P2Performing rate matching process to remove the systematic bit stream S and the first check bit stream P in the rate matching output1The padding bits in (1) and the dummy bits supposed to be added in the rate matching are processed to output two parts of a system bit stream and a check bit stream of a certain HARQ packet. Step (2) in turn comprises in particular the following two substeps (2a) (2b1) or (2a) (2b2)
Performing sub-step (2a) (2b1) when the designer considers adding dummy bits in front of the systematic bitstream sequence S, the first parity bitstream sequence P1 and the second parity bitstream sequence P2 in the rate matching algorithm, the algorithm flow being as shown in fig. 6;
(II) when the designer considers adding dummy bits to the systematic bitstream sequence S, the first parity bitstream sequence P1 and the second parity bitstream sequence P in the rate matching algorithm2Thereafter, sub-step (2a) (2b2) is performed, and the algorithm flow is as shown in fig. 7.
(2a) Setting read total bit counter n to 0, and reading system bit counter nsysRead check bit counter n as 0parAnd 0, respectively counting the total bit number of the rate matching output, the system bit number and the check bit number. The number of hypothetical padding "dummy bits" in the rate matching sub-block interleaving process is D-32 ceil ((S +4)/32) - (S + 4). The virtual circular buffer read start line number c is σ + RV × (96/nRV), where σ is the start read line offset, RV is the redundancy version value, and nRV is the number of redundancy versions. Number of transmission HARQ sub-packet bits is Ndata。
(2b1) When the value of the read total bit counter N is less than NdataThe rate matching operation of substeps (I) (II) (III) is performed in a loop.
(I) The row number c modulo the virtual circular cache total column number 96.
(II) when the line number c is less than 32, according to the circular buffer rate matching algorithm, the current output bit is the system bit, and the substeps (I) and (II) are circularly carried out.
Calculating bit positions a, a ═ colperm (c) -D of the currently selected systematic bits in the input systematic bit stream sequence S. Where ColPerm is a column permutation vector of rate matching sub-block interleaving, ColPerm ═ 0, 16, 8, 24, 4, 20, 12, 28, 2, 18, 10, 26, 6, 22, 14, 30, 1, 17, 9, 25, 5, 21, 13, 29, 3, 19, 11, 27, 7, 23, 15, 31.
When the address A is smaller than S +4, circularly executing the operations (i) (ii): (i) when the address A is larger than or equal to S-K, reading out the systematic bit S in the systematic bit stream sequence SA+1Writing the bit to the nth bit stream of the output systemsysBit position, total bit counter n and systemSystematic bit counter nsysRespectively adding 1. Judging whether N is equal to NdataIf the rate matching algorithm is equal to the rate matching algorithm, the rate matching algorithm is ended, otherwise, the rate matching algorithm is continuously executed. (ii) Address a plus the number of subblock interleaving columns 32.
③ the line number c plus 1.
(III) when the line number c is larger than or equal to 32, according to a circular cache rate matching algorithm, taking the current output bit as a check bit, and circularly performing the substeps (I) and (II).
Calculating the current selected check bit in the input first check bit stream sequence P1Bit position B (replacing "a" with "B" is for consistency with the technical solution and to avoid confusion, as follows), B ═ ColPerm (c/2-16) -D.
(iv) when address B satisfies less than S +4, loop through operations (i) (ii) (iii) (iv) (v): (i) when the address B is greater than or equal to S-K, reading out the first check bit stream sequence P1Middle check bit pB+1 1Writing the bit to the nth output check bit streamparBit position, read total bit counter n and read check bit counter nparRespectively adding 1. Judging whether N is equal to NdataIf the rate matching algorithm is equal to the rate matching algorithm, the rate matching algorithm is ended, otherwise, the rate matching algorithm is continuously executed. (ii) Calculating the currently selected parity bits in the input second parity bit stream sequence P2B2, B2 ═ B + δ, where δ is the sub-block interleaving offset of the second parity bit stream sequence relative to the first parity bit stream sequence. (iii) When B2 is equal to or greater than S +4, B2 subtracts S +4+ D. (iv) When B2 is greater than or equal to 0, reading out the second check bit stream sequence P2Middle check bit pB2+1 2Writing the bit to the nth output check bit streamparBit position, read total bit counter n and read check bit counter nparRespectively adding 1. Judging whether N is equal to NdataIf the rate matching algorithm is equal to the rate matching algorithm, the rate matching algorithm is ended, otherwise, the rate matching algorithm is continuously executed. (v) Address B plus the number of subblock interleaving columns 32.
③ the line number c plus 2.
(2b2) When the value of the read total bit counter N is less than NdataThe rate matching operation of substeps (I) (II) (III) is performed in a loop.
(I) The row number c modulo the virtual circular cache total column number 96.
(II) when the line number c is less than 32, according to the circular buffer rate matching algorithm, the current output bit is the system bit, and the substeps (first) and (fourth) are circularly carried out.
The bit position a of the currently selected systematic bit in the input systematic bitstream sequence S is calculated, a ═ colperm (c). Where ColPerm is a column permutation vector of rate matching sub-block interleaving, ColPerm ═ 0, 16, 8, 24, 4, 20, 12, 28, 2, 18, 10, 26, 6, 22, 14, 30, 1, 17, 9, 25, 5, 21, 13, 29, 3, 19, 11, 27, 7, 23, 15, 31.
When address a is less than S-K, address a cycles plus the number of subblock interleaving columns 32.
(iii) when address a is less than S +4, loop through (i) (ii): (i) reading out systematic bits S in a systematic bit stream sequence SA+1Writing the bit to the nth bit stream of the output systemsysBit position, read total bit counter n and read system bit counter nsysRespectively adding 1. Judging whether N is equal to NdataIf the rate matching algorithm is equal to the rate matching algorithm, the rate matching algorithm is ended, otherwise, the rate matching algorithm is continuously executed. (ii) Address a plus the number of subblock interleaving columns 32.
And c, adding 1 to the line number c.
(III) when the line number c is larger than or equal to 32, according to the circular cache rate matching algorithm, the current output bit is a check bit, and the substeps of (I), (II) and (III) are circularly carried out.
Calculating the current selected check bit in the input first check bit stream sequence P1Bit position B, B ═ ColPerm (c/2-16).
When the address B is smaller than S-K, circularly executing the operations (i) (ii): reading out a second parity bit stream sequence P2Middle check bit pB+δ+1 2Writing the bit to the nth output check bit streamparBit position, read total bit counter n and read check bit counter nparRespectively adding 1. Judging whether N is equal to NdataIf the rate matching algorithm is equal to the rate matching algorithm, the rate matching algorithm is ended, otherwise, the rate matching algorithm is continuously executed. (ii) Address B plus the number of subblock interleaving columns 32.
(iii) when address B is less than S +4, performing in loop (i) (ii) (iii): (i) reading out a first check bit stream sequence P1Middle check bit pB+1 1Writing the bit to the nth output check bit streamparBit position, read total bit counter n and read check bit counter nparRespectively adding 1. Judging whether N is equal to NdataIf equal, the rate matching algorithm 2b) ends, otherwise, the rate matching algorithm 2b) continues to be executed. (ii) Reading out a second parity bit stream sequence P2Middle check bit pmod(B+δ，S+4)+1 2Writing the bit to the nth output check bit streamparBit position, read total bit counter n and read check bit counter nparRespectively adding 1. Judging whether N is equal to NdataIf the rate matching algorithm is equal to the rate matching algorithm, the rate matching algorithm is ended, otherwise, the rate matching algorithm is continuously executed. (iii) Address B plus the number of subblock interleaving columns 32.
And c, adding 2 to the line number c.
The system bit stream and the check bit stream which are output based on the rate matching of the circular buffer are transmitted by using high-reliability bits in a constellation diagram under a 16QAM, 64QAM or 256QAM modulation mode, so that bit priority mapping modulation is realized.
Claims (11)
1. A method for processing a wireless physical layer channel coding link is characterized by comprising the following steps:
1.1) carrying out Turbo coding on the bit data of the information block;
1.2) carrying out rate matching on code word bits after Turbo coding based on a circular cache;
1.3) carrying out bit priority mapping modulation on the system bit stream and the check bit stream which are output after the rate matching.
2. The processing method according to claim 1, wherein the Turbo coding in step 1.1) is a QPP interleaver-based Turbo coding, and wherein step 1.1) comprises the necessary padding: before encoding, firstly, judging whether the bit data size of the information block meets the bit data size requirement of a QPP interleaver, if not, filling a certain number of padding bits before the bit data of the information block, otherwise, not filling before the bit data of the information block.
3. The processing method according to claim 2, wherein the step 1.1) further comprises:
3.1) coding the bit data of the information block subjected to the necessary filling processing by a first member coder of a Turbo code, and outputting a first check bit stream;
3.2) carrying out interleaving processing based on a QPP interleaver on the information block bit data after the necessary padding processing;
3.3) coding the output information block bit data after the interleaving processing by a second member coder of the Turbo code, and outputting a second check bit stream;
3.4) outputting tail bit sequences generated by the first member encoder and the second member encoder of the Turbo code;
3.5) multiplexing the information block bit data after the necessary padding processing, the first check bit stream, the second check bit stream and the tail bit sequence to form a Turbo coded code word bit stream based on QPP interleaving.
4. The process according to claim 1, characterized in that said step 1.2) comprises:
4.1) carrying out bit separation on the code word bit stream output by the Turbo coding to output a system bit stream,
A first parity bit stream and a second parity bit stream;
4.2) respectively carrying out sub-block interleaving processing on the system bit stream, the first check bit stream and the second check bit stream which are separately output;
4.3) carrying out bit collection processing on the system bit stream, the first check bit stream and the second check bit stream after the sub-block interleaving processing to form virtual cycle cache output;
and 4.4) determining and circularly reading the bits of the transmission data packet output by rate matching from the initial position in the virtual circular cache according to the value of the redundancy version and the length of the transmission HARQ data packet, judging according to the specific reading position, if the bits are system bits, sequentially writing the system bits into a system bit stream output by rate matching, and otherwise, sequentially writing the system bits into a check bit stream output by rate matching.
5. The process according to claim 1, characterized in that said step 1.2) comprises: 5.1) carrying out bit separation on the code word bit stream output by the Turbo coding to output a system bit stream,
A first parity bit stream and a second parity bit stream;
and 5.2) determining and selecting the bits of the sending HARQ data packet which is output in a rate matching manner from the separately output system bit stream, the first check bit stream and the second check bit stream according to the value of the redundancy version and the length of the sending HARQ data packet, judging according to a specific reading position, and if the bits are the system bits, sequentially writing the bits into the rate matching output system bit stream, otherwise, sequentially writing the bits into the rate matching output check bit stream.
6. The process according to claim 5, characterized in that said step 1.2) comprises:
6.1) carrying out bit separation on code word bits after Turbo coding, and outputting a system bit stream, a first check bit stream and a second check bit stream with the lengths of L;
6.2) calculating the virtual addition D-32 ceil (L/32) -L dummy bits of the separated system bit stream, the first parity bit stream and the second parity bit stream on each data bit stream;
6.3) carrying out rate matching processing on the system bit stream added with the virtual bits, the first check bit stream and the second check bit stream and carrying out bit selection from the system bit stream, the first check bit stream and the second check bit stream to generate the system bit stream and the check bit stream corresponding to the HARQ data packet, and if filling bits exist, carrying out bit de-filling processing on the separated system bit stream and the first check bit stream.
7. The process of claim 6, wherein said step 6.3) comprises:
7.1) set the read total bit counter n to 0, read systematic bit counter nsysRead check bit counter n as 0par＝0；
7.2) judging whether the current output n +1 th bit is a systematic bit according to a circular cache rate matching algorithm, if the output bit is the systematic bit, determining according to a corresponding formula, reading out a non-padding bit according to the address A of the current selected bit in the input systematic bit stream, and writing the non-padding bit into the nth bit of the output systematic bit streamsysBit position, reading out total bit counter n and system bit counter n simultaneouslysysRespectively adding 1; judging whether the bit counter n meets the requirement of the total number of bits of the current generated HARQ data packet, if so, finishing the rate matching algorithm, otherwise, continuing the rate matching algorithm;
7.3) according to the circular buffer rate matching algorithm, judging whether the current output n +1 th bit is a check bit, if the output bit is the check bit, alternately reading from the separated first check bit stream and second check bit stream, determining according to a corresponding formula, reading out the non-second check bit stream according to the address B of the current selected bit in the input first check bit stream or second check bit stream, and writing the bit into the nth bit stream of the output check bit streamparBit position, reading out total bit counter n and check bit counter n simultaneouslyparRespectively adding 1; and judging whether the read total bit counter n meets the requirement of the total number of bits of the current generated HARQ data packet, if so, finishing the rate matching algorithm, and otherwise, continuing the rate matching algorithm.
8. The processing method according to claim 6, wherein when the dummy bits are virtually placed in front of the separate system bitstream, first check bitstream and second check bitstream in step 6.2), the address a in the input system bitstream in step 7.2) is denoted as a ═ ColPerm (c) -D, and the address B in the input first check bitstream or second check bitstream in step 7.3) is denoted as B ═ ColPerm (c/2-16) -D; wherein: ColPerm is the column permutation vector of the rate matching sub-block interleaving, and c is the row number.
9. The processing method according to claim 6, wherein when the dummy bits are virtually placed behind the separate system bitstream, the first check bitstream and the second check bitstream in step 6.2), the address a in the input system bitstream in step 7.2) is denoted as a ═ ColPerm (c), and the address B in the input first check bitstream or the second check bitstream in step 7.3) is denoted as B ═ ColPerm (c/2-16); wherein: ColPerm is the column permutation vector of the rate matching sub-block interleaving, and c is the row number.
10. The processing method according to claim 1, characterized in that the step 1.3) is in particular: and transmitting the data in the system bit stream by using high-reliability bits in a constellation diagram under a high-order modulation mode for the system bit stream and the check bit stream which are output after rate matching, so as to realize bit priority mapping.
11. The processing method according to claim 10, wherein the implementation employs a bit collection interleaving method or a bit interleaving method.
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