CN101097709A

CN101097709A - Picture display method and display device thereof

Info

Publication number: CN101097709A
Application number: CNA2006100904957A
Authority: CN
Inventors: 王俊陇
Original assignee: Novatek Microelectronics Corp
Current assignee: Novatek Microelectronics Corp
Priority date: 2006-06-27
Filing date: 2006-06-27
Publication date: 2008-01-02

Abstract

A screen display method and a display device thereof are suitable for displaying a plurality of screen data in an image signal on a display panel. There is a vertical blank period between each two adjacent screen data in the image signal. The screen display method comprises the following steps: displaying a background screen on the display panel during the vertical blank period of the image signal; and displaying one of the above screen data on the display panel during the non-vertical blank period of the image signal.

Description

Picture display process and display device thereof

Technical field

The invention relates to a kind of display device and picture display process thereof, and particularly relevant for a kind of display device and picture display process thereof that the picture with different panels resolution can be shown on the panel.

Background technology

Relevant studies show that, the natural visual field ratio of human eye is 16: 9, that is to say that it is 16: 9 that human eye is caught " golden section line " optimal proportion of image.In the horizontal view angle scope of observing a scenery during near 28 °～30 °, eyes just need be on the scenery image forced adjustment visual focusing point, image just can be full of whole visual field naturally.Watch 16: 9 the ratio of width to height (also claiming aspect ration) picture the time, visual range is about 27 °, near the angular field of view of focusing naturally.And same distance is when watching the picture of 4: 3 the ratio of width to height, because the horizontal view angle has only 18 °, it is tired that eyes are forced to feel.The picture of 16: 9 the ratio of width to height has dwindled the vision difference between film and display device (for example LCD) to a certain extent, and its broad picture makes the people that more strong telepresenc be arranged when watching picture.

Forcing above-mentioned advantage to do one's bidding, the signal of video signal of 16: 9 the ratio of width to height broadcast formats will become following main flow naturally.Yet because present TV programme mainly is still the signal of video signal that adopts 4: 3 the ratio of width to height broadcast formats, therefore the display device in 4: 3 in the market screen the ratio of width to height still accounts for dominant position.Fig. 1 has the synoptic diagram of the picture of less resolution for known in the fixing display device demonstration of resolution.If in the time of will playing the picture (be similar to fixedly the display device demonstration of resolution have the picture of less resolution) of 16: 9 the ratio of width to height with the display device of 4: 3 screen the ratio of width to height, often can only be shown in the top of display device screen regularly, and also can't Be Controlled and removes to show other background frame in the zone that display device does not demonstrate picture, so the picture that shows 16: 9 the ratio of width to height in can't putting under the situation of display device screen, just can make the people watch as shown in Figure 1 picture.

Therefore, some manufacturer usage ratio scaler (scaler) in display device will be shown on the panel of higher resolution in will putting than the image frame of low-res.That is, known techniques needs the proportion of utilization scaler complete raw frames data (16: 9 the ratio of width to height) to be stored in the inner storing memory body earlier, and then according to the resolution of display panel background information is inserted in the picture data to adjust its resolution, the picture data (4: 3 the ratio of width to height) that just will meet the panel resolution then sends time schedule controller to.See through the driving of time schedule controller, source electrode driver and gate pole driver, the proportional zoom device of known techniques can make the picture of 16: 9 the ratio of width to height be shown on the display panel of 4: 3 the ratio of width to height in putting.

In addition, other known techniques are also arranged by the driving integrated circuit framework that changes display device, make the display device can compatible 16: 9 and the broadcast format signal of video signal of 4: 3 the ratio of width to height, so that make the display device of 4: 3 screen the ratio of width to height can put the middle picture of playing 16: 9 the ratio of width to height, as shown in Figure 2.Fig. 2 is on the display device of fixing resolution, shows the synoptic diagram of the picture with less resolution in putting.

Yet, in the small profitsization that become more that electronic product is made a profit are competed with the haggling that becomes fierce more, adopt above-mentioned way not only to make the cost of manufacture of display device raise, and then the benefit space of having strangled manufacturer.In addition, the framework that sees through change driving integrated circuit reaches and makes the compatible two kinds of the ratio of width to height broadcast formats of display device energy with making or have much ado, has also increased the degree of difficulty of design display device, is not a kind of selection of wisdom.

Summary of the invention

Purpose of the present invention just provides a kind of picture display process, this picture display process does not need by using a large amount of storing memory bodies, and/or the driving integrated circuit framework in the change display device, just can make the picture that is different from the panel resolution be shown in display panel in putting.

Another object of the present invention provides a kind of display device, this display device only need be adjusted the sequential control of time schedule controller, promptly can not need by using the storing memory body, and/or change the driving integrated circuit framework in the display device, just can make picture be shown in display panel in putting.

Based on above-mentioned and other purpose, the present invention proposes a kind of picture display process, is suitable for a plurality of picture datas in the signal of video signal are shown in display panel.Wherein, have during the vertical blank between per two the adjacent pictures data in the signal of video signal.This picture display process comprises the following steps: that the display background picture is in display panel during the vertical blank of signal of video signal; And in the non-perpendicular interregnum of signal of video signal show above-mentioned picture data one of them in display panel.

Based on above-mentioned and other purpose, the present invention proposes a kind of display device, and this display device comprises display panel, source electrode driver, gate pole driver, processing unit and time schedule controller.Wherein source electrode driver and gate pole driver all are coupled to display panel.Processing unit is in order to provide signal of video signal.Above-mentioned signal of video signal comprises a plurality of picture datas, and has during the vertical blank between per two adjacent pictures data.Time schedule controller is coupled to processing unit, source electrode driver and gate pole driver, in order to receive signal of video signal, and by Controlling Source driver and gate pole driver and drive display panel, so that display panel display background picture during the vertical blank of signal of video signal, and make display panel in the non-perpendicular interregnum of signal of video signal show above-mentioned picture data one of them.

Described according to one embodiment of the invention, above-mentioned display background picture during the vertical blank of signal of video signal comprises the quantity that determines a plurality of clock pulse pulses in the step of display panel.During vertical blank, add above-mentioned clock pulse pulse to the gate drive clock pulse, wherein the gate drive clock pulse drives the required sequential of gate line in order to the gate pole driver that display panel is provided.During vertical blank, provide and open the gate pole driver of beginning driving pulse to display panel.The data that behind each picture data of signal of video signal, adds background frame.Utilize the data of the source electrode driver breech lock background frame of display panel.According to the data display background picture of breech lock background frame in source electrode driver in display panel.

Described according to one embodiment of the invention, above-mentioned providing opened beginning driving pulse to the step of the gate pole driver of this display panel and comprised: first impulse duration in those clock pulse pulses that added during vertical blank, making and opening the beginning driving pulse is enabled status.

Described according to one embodiment of the invention, the step of a plurality of clock pulse number of pulses of above-mentioned decision comprises: calculate gate line number poor of the horizontal bar number of above-mentioned picture data and display panel, and be the quantitative value of those clock pulse pulses with the gained result divided by 2.

In another embodiment, the step of a plurality of clock pulse number of pulses of above-mentioned decision comprises: calculate gate line number poor of the horizontal bar number of picture data and display panel, and with the gained result divided by 2, to draw first numerical value.First numerical value is added predetermined number, with quantitative value as those clock pulse pulses.

The present invention is because of having a plurality of picture datas in the signal of video signal that utilizes display device to receive, and just has the characteristic during the vertical blank between per two adjacent pictures data, and during the vertical blank of signal of video signal the display background picture in display panel, in the non-perpendicular interregnum of signal of video signal show those picture datas one of them in display panel.Therefore the present invention does not need by using the storing memory body, and/or the drive IC framework in the change display device, and only need be through the sequential of the signal that changes display device control grid driver, just can make picture be shown in display panel in putting, even make picture be shown in optional position on the display panel.Simultaneously, adopt the present invention more can reduce the benefit space of cost of manufacture, increase manufacturer, the degree of difficulty of reduction design display device.

For above-mentioned and other purposes, feature and advantage of the present invention can be become apparent, preferred embodiment cited below particularly, and cooperate appended graphicly, be described in detail below.

Description of drawings

Fig. 1 has the synoptic diagram of the picture of less resolution for known in the fixing display device demonstration of resolution.

Fig. 2 is for showing the synoptic diagram of the picture with less resolution in fixedly the display device of resolution is put.

Fig. 3 is the circuit diagram according to display device of the present invention.

Fig. 4, Fig. 5, Fig. 6, Fig. 7 and Fig. 8 are the process flow diagram according to picture display process of the present invention.

Fig. 9 and Figure 10 are the signal timing diagram according to picture display process of the present invention.

Figure 11 is the synoptic diagram according to the quantity of a plurality of clock pulse pulses of the calculating of one embodiment of the invention.

Figure 12 is according to opening beginning driving pulse GS and the sequential chart of gate drive clock pulse GC during vertical blank in another embodiment of the present invention key diagram 3.

301: processing unit

302: time schedule controller

303: source electrode driver

304: gate pole driver

305: display panel

306: liquid crystal

401,402,501,502,503,601,602,701,702,801,802,803: the step of picture display process

901,902: the clock pulse that is added to the gate drive clock pulse

903,904,1001,1002,1003: pulse

DE: data enable signal

GC: gate drive clock pulse

GS: open the beginning driving pulse

G1～G1024: gate line

IN: input signal

LD: be written into signal

N: the activation pulse of N picture data

N+1: the activation pulse of N+1 picture data

N+2: the activation pulse of N+2 picture data

PI: signal of video signal

SP: source drive pulse

S1～S1280: source electrode line

Embodiment

For the convenience that illustrates, following examples will suppose that the resolution of raw frames data is 1280 * 900, and other supposes that the resolution of display panel in the display device (is example with the LCD) is 1280 * 1024.In addition, being shown in display panel during following embodiment will put with picture is that example is set forth mode of operation of the present invention.In following examples, Fig. 3 is the circuit diagram according to display device of the present invention.Fig. 4, Fig. 5, Fig. 6, Fig. 7 and Fig. 8 are the process flow diagram according to picture display process of the present invention.Fig. 9 and Figure 10 are the signal timing diagram according to picture display process of the present invention.Please needs following the instructions and with reference to above-mentioned each figure.

Among Fig. 3 301,302,303,304,305 is respectively processing unit, time schedule controller (TimingController), source electrode driver (Source Driver), gate pole driver (Gate Driver) and display panel (Display Panel).In this embodiment, processing unit 301 can comprise proportional zoom device (scaler).Display panel 305 has gate line G1～G1024 and source electrode line S1～S1280.Gate line G1～G1024 is driven by gate pole driver 304 respectively, and source electrode line S1～S1280 is then driven by source electrode driver 303 respectively.The confluce of each gate line and source electrode line all disposes pixel (as follows shown in the pixel 306) one time.And processing unit 301 receiving inputted signal IN, so that signal of video signal PI to be provided.Wherein, signal of video signal PI comprises a plurality of picture datas, and has (Vertical Blank Period) during the vertical blank between per two adjacent pictures data separately.

Please be simultaneously with reference to Fig. 3 and Fig. 4.Because the horizontal bar number of each picture data among the signal of video signal PI (that is vertical resolution) is 900, and the gate line of display device to count G1～G1024 (that is vertical resolution of display device) be 1024, therefore if when desiring to make picture data to be shown in display device in putting, then must make the part of not display frame data of display device remove to demonstrate background frame (or not showing any picture data).Above-mentioned time schedule controller 302 is in order to receive the signal of video signal PI that processing unit 301 is exported, and time schedule controller 302 drives display panel 305 by Controlling Source driver 303 with gate pole driver 304, makes display panel 305 demonstrate background frame (as the step 401 of Fig. 4) during the vertical blank of signal of video signal PI.That is to say, utilize during the vertical blank, make the part gate line zone of not display frame data on the display panel 305 of display device remove to demonstrate background frame.Next, in the non-perpendicular interregnum of signal of video signal PI, make display panel 305 show those picture datas one of them (as step 402 of Fig. 4).

Fig. 5 is the embodiment according to step 401 in the key diagram 4 of the present invention.Fig. 9 applies signal sequential chart after each step of Fig. 5 according to embodiment of the invention explanation.Please be simultaneously with reference to Fig. 3, Fig. 5 and Fig. 9.Time schedule controller 302 is exported gate drive clock pulse GC and is opened beginning driving pulse GS to gate pole driver 304, makes gate pole driver 304 according to the gate line G1～G1024 of gate drive clock pulse GC with the sequential driving display panel 305 that opens beginning driving pulse GS.And time schedule controller 302 more carries out following operation.At first time schedule controller 302 needs the quantity (as the step 501 of Fig. 5) of a plurality of clock pulse pulses of decision.The enforcement example of step 501 will be in hereinafter describing.During vertical blank, time schedule controller 302 is added to gate drive clock pulse GC (as the step 502 of Fig. 5) with the clock pulse pulse of quantity that step 501 determines.For example, express during the adjacent pictures data during the vertical blank between the N and N+1 among Fig. 9, the clock pulse pulse 901 of quantity that step 501 determines is injected towards gate drive clock pulse GC; In addition during the adjacent pictures data during the vertical blank between N+1 and the N+2 in, the clock pulse pulse 902 of quantity that step 501 determines also is injected towards gate drive clock pulse GC.During vertical blank, time schedule controller 302 will open beginning driving pulse GS and above-mentioned gate drive clock pulse GC exports gate pole driver 304 (as the step 503 of Fig. 5) to.Thus, time schedule controller 302 just is able to drive by control grid driver 304 mode of gate lines, make display panel 305 can be during the vertical blank of signal of video signal PI the display background picture.

In addition, the DE among Fig. 9 is the data enable signal (Data Enable) that processing unit 301 exports time schedule controller 302 to.Time schedule controller 302 receives each picture data among the signal of video signal PI in regular turn according to the sequential of data enable signal DE.Wherein, N, N+1 and N+2 represent N respectively, N+1 is individual and N+2 picture data.As previously mentioned, present embodiment is that each picture data has 900 horizontal line data separately among the hypothesis signal of video signal PI, and therefore above-mentioned data enable signal DE number of pulses of (non-perpendicular interregnum) during each picture data is 900 pulses.In present embodiment, the gate drive clock pulse GC that time schedule controller 302 is exported also has 900 pulses during each picture data.In this embodiment, first impulse duration of (for example clock pulse pulse 901 or 902) in those clock pulse pulses that time schedule controller 302 is added during vertical blank, making and opening beginning driving pulse GS is enabled status (for example pulse 903 or 904), yet the user also can change the activation time of opening beginning driving pulse GS according to the actual needs in the design.

The mode of the quantity of a plurality of clock pulse pulses of above-mentioned time schedule controller 302 decisions can illustrate with Figure 11.Figure 11 is the synoptic diagram according to the quantity of a plurality of clock pulse pulses of the calculating of one embodiment of the invention.Please be simultaneously with reference to Fig. 3 and Figure 11.P among Figure 11 is expressed as the gate line number (present embodiment is 1024) of display panel 305 in the display device, S is expressed as the horizontal bar number (present embodiment is 900) of each picture data among the signal of video signal PI, and IN1 and IN2 are expressed as the gate line number of the part (background parts) of not display frame data in the display panel 305 of display device.With this embodiment, owing to be the display panel 305 that is shown in display device in picture will being put, so IN1 can be the same with the gate line number of IN2.So time schedule controller 302 calculates the gate line of above-mentioned display panel and counts the horizontal bar of P and picture data and count the poor of S, and with the gained result divided by 2, just with the resulting value in (P-S)/2, as the quantitative value of those clock pulse pulses.This quantitative value is exactly IN1 and the IN2 gate line number at this embodiment, therefore can draw IN1 and IN2 respectively is 62 gate lines.

Please be simultaneously with reference to Fig. 3, Fig. 9 and Figure 11.In a manner mentioned above, at preceding (that is during vertical blank) that the activation pulse of N+1 picture data begins to move, time schedule controller 302 just can export the pulse 903 of opening among the beginning driving pulse GS to gate pole driver 304.When exporting pulse 903 to gate pole driver 304, time schedule controller 302 also begins to export clock pulse 901 to gate pole driver 304, make gate pole driver 304 beginnings drive gate line G1～G62 one by one, drive 62 gate lines altogether according to the sequential of those clock pulse pulses 901 that added.Then, transmit picture datas during the time schedule controller 302 at processing unit 301, just when the activation pulse of N+1 picture data begins to move, gate pole driver 304 just drives gate line G63～G962 one by one according to the sequential of gate drive clock pulse GC, drives 900 gate lines altogether.Then, gate pole driver 304 drives gate line G963～G1024 according to the clock pulse pulse 902 that time schedule controller 302 is exported again, drives 62 gate lines altogether.So the gate line type of drive just can make picture be shown in display device in putting.

Yet, because in this embodiment, first impulse duration in the clock pulse pulse 902 that time schedule controller 302 is during vertical blank to be added, making and opening beginning driving pulse GS is enabled status (referring to pulse 904 at this).Therefore, during time schedule controller 302 output clock pulse pulses 902, gate pole driver 304 also drives gate line G1～G62 simultaneously in regular turn except driving gate line G963～G1024 in regular turn.Thus, gate line G963～G1024 and gate line G1～G62 just can be driven by gate pole driver 304 during same.The purpose of doing like this is the clock pulse pulse sum that can economization be added during vertical blank, make gate pole driver 304 be difficult for, and cause gate pole driver 304 disorder in logic with the mutual crossover of original clock pulse (for example the gate drive clock pulse of N picture data or the gate drive clock pulse of N+1 picture data) because those clock pulses (for example pulse 901) that added are too much.

Fig. 8 is in the flow chart of steps of source drive aspect according to step 401 among embodiment of the invention explanation cooperation Fig. 4.Figure 10 applies signal sequential chart after each step of Fig. 8 according to embodiment of the invention explanation.Please be simultaneously with reference to Fig. 3, Fig. 8 and Figure 10.Because this embodiment desires to make the part of not display frame data of display device to remove to demonstrate background frame, therefore processing unit 301 must add the data (as the step 801 of Fig. 8) of background frame behind each picture data of signal of video signal PI, and the signal of video signal PI that will add the background frame data sends time schedule controller 302 to.Cooperate the background frame data that is added, processing unit 301 increases an extra pulse (shown in pulse among Figure 10 1001) again in its data enable signal DE back of exporting.In order to make the finishing touch horizontal line data (being the background frame data that is added) of reason unit 301, the source electrode driver 303 energy breech lock dwelling picture data of exporting, therefore time schedule controller 302 is just according to the sequential of pulse 1001, being written into signal (source driver load) LD at its source drive pulse of exporting (source driver start pulse) SP and source electrode has increased a pulse respectively, as pulse among Figure 10 1002 with shown in the pulse 1003.Be written into the sequential control of signal LD according to source drive pulse SP and source electrode, so source electrode driver 303 can correctly be latched in each source electrode data in the background frame data in the corresponding data channel (as the step 802 of Fig. 8) according to this extra pulse 1002.

Then, source electrode driver 303 each source electrode data (being the data of background frame) that will be latched in the data channel according to the sequential of pulse 1003 exports display panel 305 to.The data of the background frame that this source electrode driver 303 is exported will be held, and is written into up to source electrode to occur another pulse among the signal LD, and the output of source electrode driver 303 just can be updated.At source electrode driver 303 breech locks and after beginning to export the data of background frame, promptly enter during the vertical blank.During vertical blank, gate pole driver 304 just drives gate line G1～G62 and gate line G963～G1024 according to aforementioned operation with the sequential of clock pulse pulse 901 in regular turn.Thus, the display panel 305 of display device just can be according to the data of breech lock background frame in source electrode driver 303 display background picture (as the step 803 of Fig. 8), and then make display device originally the part of not display frame data demonstrate background frame.Yet whether the user can determine execution in step 801～803 according to actual needs.For example, time schedule controller 302 can Controlling Source driver 303, make source electrode driver 303 not export any data (for example making the accurate position of its output equal the accurate position of common voltage of display panel 305) during vertical blank, the change of this embodiment also can reach the effect of present embodiment.

According to spirit of the present invention, can determine the position of being desired between display frame and the display panel to concern according to demand.Therefore, the mode of the quantity of a plurality of clock pulse pulses of above-mentioned time schedule controller 302 decisions can illustrate with Fig. 6.Fig. 6 is the substep process flow diagram according to step 501 in the embodiment of the invention key diagram 5.Please be simultaneously with reference to Fig. 3, Fig. 6 and Fig. 9.In other embodiment, when if user's desire is presented at picture data the position of lower middle of display device, as long as the gate line that then makes time schedule controller 302 calculate above-mentioned display panel 305 is counted the horizontal bar of P and picture data and is counted the poor of S, and with the gained result divided by 2, with the numerical value of winning (as the step 601 of Fig. 6), then again first numerical value is added predetermined number X, i.e. (P-S)/2+X is with the quantitative value (as the step 602 of Fig. 6) as those clock pulse pulses.Then, time schedule controller 302 is added to gate drive clock pulse GC with (P-S)/2+X clock pulse pulse and gets final product during vertical blank.For example continue to use the hypothesis of last embodiment, first numerical value (P-S)/2 is added predetermined number X (supposing X=10), i.e. (1024-900)/2+10, the quantitative value of the clock pulse pulse that is then added just is 72.Therefore, gate pole driver 304 can drive gate line G1～G72 and gate line G973～G1024 earlier during vertical blank.Thus, when end and data enable signal DE began to move during the vertical blank, gate pole driver 304 just can drive gate line G73～G972 according to gate drive clock pulse GC.So the gate line type of drive just can make picture be shown in the position, lower middle of display device.

Fig. 7 is the substep process flow diagram according to step 501 in another embodiment of the present invention key diagram 5.Figure 12 is according to opening beginning driving pulse GS and the sequential chart of gate drive clock pulse GC during vertical blank in another embodiment of the present invention key diagram 3.Please be simultaneously with reference to Fig. 3, Fig. 7 and Figure 12.In like manner, when if user's desire is presented at picture data the position of upper middle of display device, as long as the gate line that then makes time schedule controller 302 calculate above-mentioned display panel 305 is counted the horizontal bar of P and picture data and is counted the poor of S, and with the gained result divided by 2, with the numerical value of winning (as the step 701 of Fig. 7), then again first numerical value is deducted predetermined number X, i.e. (P-S)/2-X, with as after opening beginning driving pulse GS in during the vertical blank and taking place, the quantitative value (as the step 702 of Fig. 7) of clock pulse pulse among the gate drive clock pulse GC.Overlap for avoiding desiring display frame and background frame, therefore need during vertical blank in and before the sequential that opens beginning driving pulse GS, will be at least among 2X clock pulse pulse adding gate drive clock pulse GC (as the step 703 of Fig. 7), as shown in figure 12.Other of present embodiment are not addressed part can apply it with reference to aforementioned all embodiment, therefore repeats no more.It should be noted that in all embodiments institute's predetermined number of adding or deducting must belong to natural number.

In a word, so long as add a plurality of clock pulses to the gate drive clock pulse during utilizing the vertical blank of signal of video signal PI, make gate pole driver during the vertical blank of signal of video signal PI, just drive the gate line of corresponding those clock pulse numbers in advance, and then make picture be presented at assigned address in the display device, just met spiritual place of the present invention, so the present invention should be not limited to above-mentioned cited embodiment.

The present invention is because of having a plurality of picture datas among the signal of video signal PI that utilizes display device and receive, and just has the characteristic during the vertical blank between per two adjacent pictures data, and during the vertical blank of signal of video signal PI the display background picture in display panel, in the non-perpendicular interregnum of signal of video signal PI show those picture datas one of them in display panel.Therefore the present invention can not need by using the storing memory body, and/or the driving integrated circuit framework in the change display device, and only need be through the sequential of the signal that changes display device control grid driver, just can make picture be shown in display panel in putting, even make picture be shown in optional position on the display panel.Simultaneously, adopt the present invention more can reduce the benefit space of cost of manufacture, increase manufacturer, the degree of difficulty of reduction design display device.

Though the present invention discloses as above with preferred embodiment; right its is not in order to limiting the present invention, anyly has the knack of this skill person, without departing from the spirit and scope of the present invention; when can doing a little change and retouching, so protection scope of the present invention is as the criterion when looking the claim person of defining.

Claims

1. A picture display method, characterized in that it is suitable for displaying multiple picture data in an image signal on a display panel, wherein there is a vertical blank period between every two adjacent picture data in the image signal, The screen display methods include:

displaying a background image on the display panel during the vertical blank period of the image signal; and

One of the image data is displayed on the display panel during the non-vertical blank period of the image signal.

2. The image display method according to claim 1, wherein the step of displaying a background image on the display panel during the vertical blank period of the image signal comprises:

Determine the number of multiple clock pulses;

During the vertical blank period, adding the clock pulses to a gate driving clock, wherein the gate driving clock is used to provide the timing required for the gate driver of the display panel to drive the gate lines; and

During the vertical blank period, a start driving pulse is provided to the gate driver of the display panel.

3. The image display method according to claim 2, wherein the step of providing the start driving pulse to the gate driver of the display panel comprises:

During the first pulse period of the clock pulses added during the vertical blank period, the start driving pulse is enabled.

4. The image display method according to claim 2, wherein the step of determining the number of clock pulses comprises:

Calculate the difference between the number of horizontal bars of the above picture data and the number of gate lines of the display panel, and divide the obtained result by 2 to obtain the quantity value of the clock pulses.

5. The image display method according to claim 2, wherein the step of determining the number of clock pulses comprises:

calculating the difference between the number of horizontal bars of the picture data and the number of gate lines of the display panel, and dividing the obtained result by 2 to obtain a first value; and

A predetermined number is added to the first value to be the quantity value of the clock pulses.

6. The picture display method according to claim 2, wherein the step of determining the number of clock pulses comprises:

calculating the difference between the number of horizontal bars of the picture data and the number of gate lines of the display panel, and dividing the obtained result by 2 to obtain a first value;

subtracting a predetermined number from the first value as the number of clock pulses in the gate drive clock after the start drive pulse occurs in the vertical blank period; and

During the vertical blank period and before the timing of the start driving pulse, at least twice the predetermined number of clock pulses are added to the gate driving clock.

7. The image display method according to claim 1, further comprising:

adding the background frame information after each frame information of the video signal;

latching the background image data using source drivers of the display panel; and

The background image is displayed on the display panel according to the data of the background image latched in the source driver.

8. A display device, characterized in that it comprises:

a display panel;

a source driver coupled to the display panel;

a gate driver coupled to the display panel;

A processing unit is used to provide an image signal, wherein the image signal includes a plurality of frame data, and there is a vertical blank period between every two adjacent frame data;

a timing controller, coupled to the processing unit, the source driver and the gate driver, for receiving the image signal, and driving the display panel in the image by controlling the source driver and the gate driver A background picture is displayed on the display panel during the vertical blank period of the signal, and one of the picture data is displayed on the display panel during the non-vertical blank period of the image signal.

9. The display device according to claim 8, wherein the timing controller further outputs a gate driving clock and a start driving pulse to the gate driver, so that the gate driver The timing of the clock and the start drive pulse drives the gate lines of the display panel; the timing controller further determines the number of clock pulses, and adds these clock pulses to the gate during the vertical blank period a gate drive clock; and the timing controller outputs the start drive pulse to the gate driver during the vertical blank period.

10. The display device according to claim 9, wherein the timing controller enables the start driving pulse during the first pulse period of the clock pulses added during the vertical blank period state.

11. The display device according to claim 9, wherein the timing controller further calculates the difference between the number of horizontal bars of the picture data and the number of gate lines of the display panel, and divides the obtained result by 2 as the The number of clock pulses.

12. The display device according to claim 9, wherein the timing controller further calculates the difference between the number of horizontal bars of the above-mentioned picture data and the number of gate lines of the display panel, and divides the obtained result by 2, and then A predetermined number is added as the quantity value of the clock pulses.

13. The display device according to claim 9, wherein the timing controller further calculates the difference between the number of horizontal bars of the above-mentioned picture data and the number of gate lines of the display panel, and divides the obtained result by 2, and then Then subtract a predetermined number as the number of clock pulses in the gate drive clock after the start drive pulse occurs in the vertical blank period, and the timing controller is in the vertical blank period and in the start drive Before starting the timing of the driving pulse, at least twice the predetermined number of clock pulses are added to the gate driving clock.

14. The display device according to claim 8, wherein the timing controller further adds data of the background picture after each picture data of the image signal, and controls the source driver to latch the data of the background picture material.

15. The display device according to claim 14, wherein the timing controller further drives the display panel by controlling the source driver and the gate driver during the vertical blank period, so that the display panel is driven according to the latch The background image is displayed by locking the data of the background image in the source driver.