CN101067804A - A high-speed configurable extended SPI bus and working method thereof - Google Patents

Abstract

This invention discloses a high speed SPI bus and its working method including at least one master module, a slave module, a SCLK clock output signal line in SPI, MOSI data line, MISO data line, SS gating signal line and configured signal line SCFG, in which, a variable bus T/R device FPGA/CPLD set in the master module, and a bus R/T device FPGA/CPLD in the slave module compose a bus configured transceiver, the FPGA/CPLD of the master module is connected with the FPGA/CPLD of one of the slave modules by serial-cascading configured signal line SCFG, and said FPGA/CPLD of the slave module are serial to those of other slave modules by the SCFG, at the same time, the SPI of the master module is connected with other slave modules via STP and carries out difference process to the SPI bus signals.

Description

A kind of high-speed configurable extended SPI bus and method of work thereof

Technical field

Patent of the present invention relates to a kind of industrial control technology, relates in particular to a kind of high-speed configurable extended SPI bus and method of work thereof.

Background technology

In industry automatic control, Automatic Production System need carry out the collection and the operation of a large amount of digital signals and simulating signal.Fieldbus can be realized the distribution control of signal as a kind of communication means, and it is used more and more widely.The existing most traffic rate of bussing technique is not high, and flexible relatively poor, is not easy to realize the synchro control of each module on the bus.

The spi bus technology is the serial interface technologies of transmitting between a kind of IC of being used for, and can realize the full duplex synchronous transmission of data.Its physics realization is shown in Fig. 4-1.Wherein SCLK (Serial Clock) is that the clock output mos I (MasterOutput, Slave Input) of primary module exports to clock cable from module for primary module.MISO (Master Input, Slave Output) is a data signal line of giving primary module from module.SS (Slave Select) gives gating signal line from module for primary module.SPI only is fit to the short distance high-speed communication between chip and the chip, and the transfer rate of bus can reach more than tens Mbps, but but can't satisfy long Distance Transmission and many expanded configuration needs from module of industry spot.

Summary of the invention

Purpose of the present invention is exactly not high in order to solve present fieldbus structure traffic rate, flexible poor, be not easy to realize the problems such as synchro control of each module on the bus, provide a kind of have rational in infrastructure, easy to use, the research and development of improvement and communication protocol on the spi bus technical foundation, the long Distance Transmission of high speed between principal and subordinate's module and the synchro control of submodule have been realized, can carry out ONLINE RECOGNITION and configuration to the expansion and the change of any submodule, and coordinate the high-speed configurable extended SPI bus and the collocation method thereof of advantages such as each module synchronization action.

For achieving the above object, the present invention adopts following technical scheme:

A kind of high-speed configurable extended SPI bus, it has at least one primary module and at least one from module, and the SCLK clock output signal line in the spi bus, MOSI data line, MISO data line, SS gating signal line and configuration signal line SCFG, be provided with variable length bus transmission/receiver FPGA/CPLD in the described primary module, be provided with bus reception/transmitter FPGA/CPLD in module, they form the bus configuration transceiver jointly; Primary module variable length bus transmission/receiver FPGA/CPLD is connected with one of them bus reception/transmitter FPGA/CPLD from module by serially concatenated configuration signal line SCFG, should then connect mutually from module bus reception/transmitter FPGA/CPLD with other from module bus receptions/transmitter FPGA/CPLD by configuration signal line SCFG, the variable-length of carrying out data message by communication protocol and FPGA (Field Programmable Gate Array) design is transmitted and from the flexible Configuration Online of module; The spi bus of primary module also is connected from module with other by Shielded Twisted Pair simultaneously, and the spi bus signal is carried out difference processing, and a master of the long distance of high speed of realization packet is many from communication.

Described variable length bus transmission/receiver FPGA/CPLD comprises message length register, transmitting counter, transmitting counter receives and sends enable signal and counting clock signal, message length register, transmitting counter output termination comparer, comparator output terminal connects SCLK clock output signal line, counting clock signal also divides two-way, one the tunnel connects SCLK clock output signal line, and another road connects the serial transmitter input end, its output termination MOSI data line.

Described bus reception/transmitter FPGA/CPLD comprises control information receiver and data information receiver; Mainboard and each daughter board respectively have at least one control information receiver and a data information receiver.

A kind of method of work of high-speed configurable extended SPI bus, its method be,

1) system's power-on self-test;

2) primary module is to automatic identification and configuration from module, to realize main many transmission from pattern, process is: the configuration signal high level that primary module sends by communication protocol make be attached thereto first put height from the CFG_EN signal of module receiver, should prepare from module, receive primary module configuration data bag and return oneself information; First after the block configuration end, forbids self configuration module work, simultaneously the CFG_OE signal is put height, and this moment, next CFG_EN from module of series connection was put height with it, should be triggered from the modules configured operation, and triggering is gone down successively; When last no configuration information returned, configuration finished, thereby realized the software Configuration Online, with the data packet transmission that satisfies different length and the online expansion and the configuration of submodule;

3) enter normal manipulation mode; Bus address divides broadcast address and common address, if broadcast address, all submodules receive the primary module order synchronously; If common address, submodule receive only the packet with self matching addresses, when receiving, corresponding data is sent to primary module; Cooperate message protocol, realize position control, I/O control and other function that is provided with.

Described step 2) communication protocol comprises main to from communication message M2S with to main communication message S2M in; They are again respectively by configuration message: C message and data message: the D message is formed, by the most significant digit MSB sign of message.

Described master is that M2S C message format is from the configuration message C of communication message M2S extremely: be labeled as flag C/D, be command message, 0 bit data message if be labeled as 1; The message data length DL that closelys follow later of primary module address bit BA, the 3bits of 4bits; Data message DATA, its length is determined by data message length DL; Check bit VR;

From the configuration message C to main communication data message S2M is that S2M C message format is, daughter board associated description information DATA; Check bit VR;

The master is that M2S D message format is to the data message D from communication data message M2S, and flag C/D is command message if be labeled as 1, and 0 is data message; The message transfer address BS of 4bits; Submodule address MS in the plate of 4bits; The data control bit DC that comes into force; Data message position DATA, its length is determined by the DL in when configuration; Check bit VR;

From the data message D to main communication data message S2M is that S2M D message format is, flag C/D is command message if be labeled as 1, and 0 is data message; Data qualifier bit DC, 0 expression data are instant data, the synchrodata that latchs in the 1 expression buffer zone; Data message DATA, length is determined by the DL in when configuration; Check bit VR.

Described step 2) at primary module to from block configuration the time, behind the configuration signal high level, extract M2SC message BA from module monitors, BA press in the DL position, the information of DL position sends to primary module with S2M C message, the transmission of S2M C message is synchronous with the reception of M2S C message; Meanwhile extract relevant information configuration message transmission length among the M2S, write down self address; Submodule with the control of SCLK counting, realizes that by the control information receiver information extraction is to relevant register by counter in the layoutprocedure.

The position is controlled to be in the described step 3) normal manipulation mode, when primary module sends data M2S D message identification position DC is put 1, adopt common address to send, temporarily leave in the buffer zone after making each module receive data, put 1 broadcasting packet by DC then the data sync output that cushions in each submodule is realized each synchro control; And in synchronous output data, each submodule can latch the peripheral hardware sampled data synchronously, is read successively by primary module when sending order data for each submodule in the next cycle then;

If I/O is controlled to be the no synchronous requirement of each I/O point, can make M2S D message put 0, the data instant that reaches submodule is come into force and the instant data of the peripheral hardware of sampling reach primary module; If synchronous requirement is arranged, but the method for reference bit control function realizes synchronous output and sampling between each module.

In the described step 3), for common address, the control information receiver is with data dash receiver address at first; When the address receives,, this plate transmission output terminal is put high resistant forbid that data of this plate communication this time send to prevent many drivings of MISO data line if not judge this plate address; If receiver module address and DC position are continued in this plate address; After receiving the DC position data information receiver of module's address correspondence is opened the reception data; Data information receiver receives data and there is send buffer in it; After pending data finishes receiving, if the DC position be high, use then that the SS signal sends data on the bus from buffering, if low, wait broadcasting command and other plates send synchronously;

For broadcast address, the control information receiver is with data receiver address at first; If broadcast address, and the DC position is 0 o'clock, enables all module data message recipients and receives public broadcasting data; If it is 1 that DC receives the position, keep all data information receiver to forbid, after finishing, the pending data transmission utilize the SS signal that the data in all module send buffers are sent.

The present invention mainly comprises primary module, SS from module and SPI communication bus, SCFG, MOSI, MISO, SCLK signal wire formation has increased layout line on the basis of SPI (Serial Peripheral Interface) and with the signal differential processing, how a master of the long distance of high speed of realization packet is from communication.Realize the variable-length transmission of data message and the flexible Configuration Online of submodule by message protocol and the design of FPGA/CPLD FPGA (Field Programmable Gate Array).

The present invention is by increasing a SCFG serially concatenated layout line, and the system that makes has from the modules configured function.By difference processing, solved the anti-interference transmission problem of long distance of signal to bus signals.Its communication protocol adopts addressing mechanism and FPGA/CPLD programmable configuration information extraction logical design, has realized the ONLINE RECOGNITION configuration and the expansion of submodule.Communication protocol adopts synchronization mechanism to realize the synchronizing function logical design that respectively corresponding order sends the synchronous and FPGA/CPLD of data acquisition between module.Variable length bus transmission/receiver by communication protocol variable length collocation method and FPGA/CPLD, realized the variable length transmission of data message and the Configuration Online of data packet length, so realized one main more than from framework and from the flexible Configuration Online and the expansion of module.

The invention has the beneficial effects as follows:

A transmission speed height, transmission range is long

Improve by differencing, can realize the long Distance Transmission of high speed of signal spi bus.

B message data packet length configurable

By configuration, can realize transmission for the different message lengths of different submodules, can improve the flexibility of system greatly.

The Configuration Online of c submodule and functions of modules

By configuration, can realize the combination in any between the different submodules.Make the module expansion convenient, development and maintenance is simple.

The Configuration Online of d module number

By configuration, can realize the random increase and decrease of module.System flexibility is improved greatly.

The synchronous coordination of e intermodule

The synchronous coordination between each submodule be can realize, position control and other control field needs satisfied with synchronous requirement.

Transmission medium of the present invention adopts Shielded Twisted Pair, and the gordian technique of principal and subordinate's module realizes by advanced FPGA/CPLD technology, and is with low cost, reliable.

Description of drawings

Fig. 1 is traditional spi bus structural representation;

Fig. 2 is a bus physical implementation structure synoptic diagram;

Fig. 3 is a primary module bus transmitter structural representation;

Fig. 4 is a bus configuration line connection diagram;

Fig. 5 is a bus configuration information extraction functional schematic;

Fig. 6 is the proper communication structural representation;

Fig. 7 is the serial bus structure design drawing.

Wherein, 1, primary module, 2, from module, 3, spi bus, 4, serially concatenated layout line SCFG, 5, the message length register, 6, transmitting counter, 7, comparer, 8, serial transmitter, 9, serial received device.

Embodiment

The invention will be further described below in conjunction with accompanying drawing and embodiment.

Content of the present invention mainly comprises physics realization and software protocol two parts.Bus can realize the transmission of at a high speed long distance by the transformation to the SPI Physical layer.And can realize respectively being affiliated on the bus the online software arrangements of module.Be implemented as follows.

Fig. 1 is existing spi bus structural drawing.

Among Fig. 2, the present invention carries out difference processing to suppress interference with signal, increases the reliability of transmission, and transmission range is increased.Increase a serially concatenated configuration signal, can realize, to realize main many transmission from pattern to automatic identification and configuration from module.Transceiver is realized with FPGA/CPLD, and the available software Configuration Online is to realize the data packet transmission of different length.

It has at least one primary module 1 and at least one from module 2, and the SCLK clock output signal line in the spi bus 3, MOSI data line, MISO data line, SS gating signal line, SCFG configuration signal line, be provided with variable length bus transmission/receiver FPGA/CPLD in the primary module 1, be provided with bus reception/transmitter FPGA/CPLD in module 2, they form the bus configuration device jointly; Primary module 1 variable length bus transmission/receiver FPGA/CPLD is connected with one of them bus reception/transmitter FPGA/CPLD from module 2 by serially concatenated layout line SCFG 4, should then connect mutually from module 2 bus reception/transmitter FPGA/CPLD with other from module 2 bus receptions/transmitter FPGA/CPLD by serially concatenated layout line SCFG 4, the variable-length of carrying out data message by communication protocol and FPGA (Field Programmable Gate Array) design is transmitted and from the flexible Configuration Online of module; The spi bus 3 of primary module also is connected from module with other by Shielded Twisted Pair simultaneously, and the spi bus signal is carried out difference processing, and a master of the long distance of high speed of realization packet is many from communication.

Among Fig. 3, variable length bus transmission/receiver FPGA/CPLD comprises message length register 5, transmitting counter 6, transmitting counter 6 receives and sends enable signal and counting clock signal, message length register 5, transmitting counter 6 output termination comparers 7, comparer 7 output termination SCLK clock output signal lines, counting clock signal also divides two-way, and one the tunnel connects SCLK clock output signal line, another road connects serial transmitter 8 input ends, its output termination MOSI data line.

Bus receiver comprises control information receiver 8 and data information receiver among the CPLD; Each daughter board has a control information receiver, and each submodule is to there being a data information receiver on the daughter board.

The communication data message divides Master to Slave (M2S) data message and Slave to Master (S2M) data message.Wherein each is made up of configuration message (C message) and data message (D message) again for M2S and S2M data message, by most significant digit (MSB) sign of message.

M2S C message format is defined as follows:

C/ D	BA(4bits)				DL(3bits)			-	DATA	VR
												1	BA3	BA2	BA1	BA0	DL2	DL1	DL0	-	…	1/0
MSB LSB

Being described below shown in the table of each data bit:

Title	Figure place	Describe
			C/ D	1	The Command/Data flag, 1 is command message, 0 bit data message
BA	4	Board Address, 0～15
			DL	4	Data length, the length of the message data of closelying follow later. 000:2bits 001:4bits 010:8bits 011:16bits 100:24bits 101:32bits 110:64bits 111:128bits
DATA	DL	Data message, length is determined by DL.Can pass to the relevant information of daughter board about mainboard.
			VR	1	Check bit

S2M C message format is defined as follows:

-	-				-			-	DATA	VR
												1	1	1	1	1	1	1	1	-	…	1/0
MSB LSB

Being described below shown in the table of each data bit:

Title	Figure place	Describe
			DATA	DL	The daughter board associated description information
VR
		1	Check bit

M2S D message format is defined as follows:

C/ D	BS(4bits)				MS(4bits)			DC	DATA	VR
												1	BS3	BS2	BS1	BS0	MS2	MS1	MS0		1/0	…	1/0
MSB LSB

Each data bit is described below

Title	Figure place	Describe
			C/ D	1	The Command/Data flag, 1 is command message, 0 bit data message
BS	4	Board Select, 0～15 this message transfer address of sign
			MS	4	Module Select, the submodule address
DC	1	The data control bit that comes into force.If common address, 1 for to come into force the DATA data in this message in submodule, make the peripheral data information of submodule to the instant sampling of primary module synchronized transmission simultaneously.0 for temporarily to be kept at the DATA data in this message in the send buffer of submodule.Make the data of submodule in primary module synchronized transmission submodule transmission buffering simultaneously.If broadcast address, 1 is with the output of the data sync of all submodule send buffers, and makes each submodule synchronous acquisition peripheral data and be latched in and send in the buffer zone.0 comes into force for data in the M2S broadcast data packet are directly delivered to each submodule, and makes each submodule synchronous acquisition peripheral data and be latched in and send in the buffer zone.
			DATA	DL	Data message, length is determined by the DL in when configuration.
VR	1	Check bit

S2M D message format is defined as follows:

C/D	-				-			DC	DATA	VR
											1	-	-	-	-	-	-	-	1/0	…	1/0
MSB LSB

Each data bit is described below

Title	Figure place	Describe
			DC	1	Data type.0 expression data are instant data, the synchrodata that latchs in the 1 expression buffer zone.
DATA	DL	Data message, length is determined by the DL in when configuration.
			VR	1	Check bit

Serially concatenated layout line SCFG is used for the triggering system configuration operation, and detailed process is as follows:

Among Fig. 4, the configuration signal high level that primary module 1 sends makes first to put height from module 2 inner CFG_EN signals, and first prepares from module 2, receives primary module 1 configuration data bag and returns oneself information.First after module 2 configuration end, forbid self configuration module work, simultaneously the CFG_OE signal are put height, and this moment, next CFG_EN from module 2 was put height, should be triggered from the configuration operation of module 2.Go down successively.When last no configuration information returns, think that configuration finishes.Change normal manipulation mode over to.

The layoutprocedure of individual module is:

Module monitors is extracted M2S C message BA behind the configuration signal high level, BA is pressed in the DL position, and the information of DL position sends to primary module with the S2MC message, and the transmission of S2M C message and M2S C message receive synchronously.Meanwhile extract relevant information configuration message transmission length among the M2S, write down self address.Submodule with the control of SCLK counting, realizes that by the control information receiver information extraction is to relevant register, as shown in Figure 5 by counter in the layoutprocedure.

Normal mode of operation is used the D message, and the address is divided into broadcast address and common address in the message.If the message address that receives is a broadcast address, all submodules receive primary module order or synchrodata synchronously.If common address, submodule receives only the packet with self matching addresses, when receiving corresponding data is sent to primary module, if message address and self address do not match, then self and being connected of MISO are put high resistant and prevent the MISO generations that drive more, as Fig. 6.

Cooperate the use of DC position in agreement M2S message and the S2M message, can realize position control, the I/O control function.

A. the position controls function for example

In the position control, the position command that needs to send to each comes into force synchronously and needs to obtain each synchrodata.But each might be assigned in the different daughter boards or the different submodules of identical daughter board in.Can when sending data, will use primary module the M2S D message DC of common address transfer to put 1 in such cases, temporarily leave in the buffer zone after making each module receive data, the broadcasting packet of putting the transmission of 1 broadcast address by DC is realized each synchro control with the data sync output that cushions in each submodule then.And and in synchronous output data, each submodule can latch peripheral data synchronously, read successively by primary module when sending order data for each submodule in the next cycle then.(referring to M2S D message structure.)

The b.I/O control function for example

Be used for I/O when control,, data instant come into force and the instant data of the peripheral hardware of sampling if the no synchronous requirement of each I/O point can make M2S D message put 0.If synchronous requirement is arranged, but the method for reference bit control function realizes synchronous output and sampling between each module.

Daughter board bus receiver of the present invention can be realized based on the serial received device in CPLD.Be divided into control information receiver and data information receiver.Each daughter board has a control information receiver, and each submodule is to there being a data information receiver on the daughter board.As follows with concrete receiving course design.

A. the general data bag receives

The control information receiver is with data dash receiver address at first.When the address receives,, this plate is sent output terminal put the reception that high resistant is forbidden this packet of this plate if not judge this plate address.If receiver module address and DC position are continued in this plate address.After receiving the DC position data information receiver of module's address correspondence is opened the reception data.Data information receiver receives data and there is send buffer in it.After pending data finishes receiving, if the DC position be high, use then that the SS signal sends data on the bus from buffering, if low, wait broadcasting command and other plates send synchronously.

B. broadcast data packet receives

The control information receiver is with data receiver address at first.If broadcast address, and the DC position is 0 o'clock, enables all module data message recipients and receives public broadcasting data.If it is 1 that DC receives the position, keep all data information receiver to forbid, after finishing, the pending data transmission utilize the SS signal that the data in all module send buffers are sent.

Primary module variable length bus transmitter can be realized the transmission of different length message.In the motherboard design, the message length of setting is stored in the message length register, counter will send the data bits counting, and count value and message length relatively come control data to send length, as shown in Figure 3.

The design of serial transmitter as shown in Figure 7, wherein the SS signal is as the reset signal and the enable signal of counter.SS arrival hour counter reset and begin the counting, counter inhibit during the SS signal ended.Control the channel selecting of multiway intersection switch by the count value of counter, the number that data send in the buffer zone is sent in step-by-step.Wherein, the SS signal is as the reset signal and the enable signal of counter.SS arrival hour counter reset and begin the counting, counter inhibit during the SS signal ended.Control the channel selecting of multiway intersection switch by the count value of counter, the number that data send in the buffer zone is sent in step-by-step.

Claims (9)

1, a kind of high-speed configurable extended SPI bus, it has at least one primary module and at least one from module, and the SCLK clock output signal line in the spi bus, MOSI data line, MISO data line, SS gating signal line and configuration signal line SCFG, it is characterized in that: be provided with variable length bus transmission/receiver device FPGA/CPLD in the described primary module, be provided with bus reception/transmitter FPGA/CPLD in module, they form the bus configuration transceiver jointly; Primary module variable length bus transmission/receiver FPGA/CPLD is connected with one of them bus reception/transmitter FPGA/CPLD from module by serially concatenated configuration signal line SCFG, should then connect mutually from module bus reception/transmitter FPGA/CPLD with other from module bus receptions/transmitter FPGA/CPLD by configuration signal line SCFG, the variable-length of carrying out data message by communication protocol and FPGA (Field Programmable Gate Array) design is transmitted and from the flexible Configuration Online of module; The spi bus of primary module also is connected from module with other by Shielded Twisted Pair simultaneously, and the spi bus signal is carried out difference processing, and a master of the long distance of high speed of realization packet is many from communication.

2, high-speed configurable extended SPI bus according to claim 1, it is characterized in that: described variable length bus transmission/receiver FPGA/CPLD comprises message length register, transmitting counter, transmitting counter receives and sends enable signal and counting clock signal, message length register, transmitting counter output termination comparer, comparator output terminal connects SCLK clock output signal line, counting clock signal also divides two-way, one the tunnel connects SCLK clock output signal line, another road connects the serial transmitter input end, its output termination MOSI data line.

3, high-speed configurable extended SPI bus according to claim 1 is characterized in that: described bus reception/transmitter FPGA/CPLD comprises control information receiver and data information receiver; Mainboard and each daughter board respectively have at least one control information receiver and a data information receiver.

4, the method for work of the described high-speed configurable extended SPI bus of a kind of claim 1 is characterized in that: its method is,

1) system's power-on self-test;

2) primary module is to automatic identification and configuration from module, to realize main many transmission from pattern, process is: the configuration signal high level that primary module sends by communication protocol make be attached thereto first put height from the CFG_EN signal of module receiver, should prepare from module, receive primary module configuration data bag and return oneself information; First after the block configuration end, forbids self configuration module work, simultaneously the CFG_OE signal is put height, and this moment, next CFG_EN from module of series connection was put height with it, should be triggered from the modules configured operation, and triggering is gone down successively; When last no configuration information returned, configuration finished, thereby realized the software Configuration Online, with the data packet transmission that satisfies different length and the online expansion and the configuration of submodule;

3) enter normal manipulation mode; Bus address divides broadcast address and common address, if broadcast address, all submodules receive the primary module order synchronously; If common address, submodule receive only the packet with self matching addresses, when receiving, corresponding data is sent to primary module; Cooperate message protocol, realize position control, I/O control and other function that is provided with.

5, the collocation method of high-speed configurable extended SPI bus according to claim 4 is characterized in that: communication protocol comprises main to from communication message M2S with to main communication message S2M described step 2); They are again respectively by configuration message: C message and data message: the D message is formed, by the most significant digit MSB sign of message.

6, the collocation method of high-speed configurable extended SPI bus according to claim 5, it is characterized in that: described master is that M2S C message format is from the configuration message C of communication message M2S extremely: be labeled as flag C/D, be command message, 0 bit data message if be labeled as 1; The message data length DL that closelys follow later of primary module address bit BA, the 3bits of 4bits; Data message DATA, its length is determined by data message length DL; Check bit VR;

From the configuration message C to main communication data message S2M is that S2M C message format is, daughter board associated description information DATA; Check bit VR;

The master is that M2S D message format is to the data message D from communication data message M2S, and flag C/D is command message if be labeled as 1, and 0 is data message; The message transfer address BS of 4bits; Submodule address MS in the plate of 4bits; The data control bit DC that comes into force; Data message position DATA, its length is determined by the DL in when configuration; Check bit VR;

From the data message D to main communication data message S2M is that S2M D message format is, flag C/D is command message if be labeled as 1, and 0 is data message; Data qualifier bit DC, 0 expression data are instant data, the synchrodata that latchs in the 1 expression buffer zone; Data message DATA, length is determined by the DL in when configuration; Check bit VR.

7, according to claim 4 or 6 described high-speed configurable extended SPI bus, it is characterized in that: described step 2) at primary module to from block configuration the time, from module monitors behind the configuration signal high level, extract M2S C message BA, the DL position, press BA, the information of DL position sends to primary module with S2M C message, and the transmission of S2M C message and M2S C message receive synchronously; Meanwhile extract relevant information configuration message transmission length among the M2S, write down self address; Submodule with the control of SCLK counting, realizes that by the control information receiver information extraction is to relevant register by counter in the layoutprocedure.

8, according to claim 4 or 6 described high-speed configurable extended SPI bus, it is characterized in that: the position is controlled to be in the described step 3) normal manipulation mode, when primary module sends data M2S D message identification position DC is put 1, adopt common address to send, temporarily leave in the buffer zone after making each module receive data, put 1 broadcasting packet by DC then the data sync output that cushions in each submodule is realized each synchro control; And in synchronous output data, each submodule can latch the peripheral hardware sampled data synchronously, is read successively by primary module when sending order data for each submodule in the next cycle then;

If I/O is controlled to be the no synchronous requirement of each I/O point, can make M2S D message put 0, the data instant that reaches submodule is come into force and the instant data of the peripheral hardware of sampling reach primary module; If synchronous requirement is arranged, but the method for reference bit control function realizes synchronous output and sampling between each module.

9, according to claim 4 or 6 described high-speed configurable extended SPI bus, it is characterized in that: in the described step 3), for common address, the control information receiver is with data dash receiver address at first; When the address receives,, this plate transmission output terminal is put high resistant forbid that data of this plate communication this time send to prevent many drivings of MISO data line if not judge this plate address; If receiver module address and DC position are continued in this plate address; After receiving the DC position data information receiver of module's address correspondence is opened the reception data; Data information receiver receives data and there is send buffer in it; After pending data finishes receiving, if the DC position be high, use then that the SS signal sends data on the bus from buffering, if low, wait broadcasting command and other plates send synchronously;

For broadcast address, the control information receiver is with data receiver address at first; If broadcast address, and the DC position is 0 o'clock, enables all module data message recipients and receives public broadcasting data; If it is 1 that DC receives the position, keep all data information receiver to forbid, after finishing, the pending data transmission utilize the SS signal that the data in all module send buffers are sent.

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