CN101017794A - A method for sealing the small hole of the multi-hole low dielectric material in the Damascus structure - Google Patents
A method for sealing the small hole of the multi-hole low dielectric material in the Damascus structure Download PDFInfo
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- CN101017794A CN101017794A CN 200710037774 CN200710037774A CN101017794A CN 101017794 A CN101017794 A CN 101017794A CN 200710037774 CN200710037774 CN 200710037774 CN 200710037774 A CN200710037774 A CN 200710037774A CN 101017794 A CN101017794 A CN 101017794A
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Abstract
The sealing method for porous low delectric material pore in Damascus structure comprises: with twice bi-Damascus structure pattern technology, processing the throughole and groove in the first time over the desired value; full filling the hole and groove by poreless media, and second patterning in the media to form the objective size. This invention enhances mechanical strength of media layer, and controls well the figure size and appearance and film thickness.
Description
[technical field]
The present invention relates to semiconductor integrated circuit and make the field, especially about a kind of method that seals porous low dielectric material aperture in the damascene structure.
[background technology]
Along with constantly dwindling of device size, the RC problem of circuit has proposed more harsh requirement to the manufacturing of integrated circuit.As everyone knows, the delay of circuit, crosstalk etc. is to be directly proportional with the product of C with R, and R is the resistance of circuit connection, and C is the electric capacity between the circuit.The resistance of circuit connection and himself resistivity are proportional, and in the circuit size that dwindles day by day, the higher resistance of aluminum conductor becomes the factor that the restricting circuits size develops toward littler direction, and (resistivity of aluminium is about 2.8 * 10
-6Europe centimetre), simultaneously, the reliability aspect characteristic of aluminum conductor itself is also poor.At present, in a lot of advanced technologies, (resistivity of copper is about 1.7 * 10 all to have adopted copper
-6Europe centimetre) replace aluminium as plain conductor, like this, greatly reduce the resistance of line, make the circuit scaled down become possibility, and the aspect of performance of reliability such as deelectric transferred, also obtained improving greatly.
Traditional is in the preparation process of lead with aluminium, generally is first deposit aluminium, and then utilizes photoetching and etching that it is carried out graphically, and then deposit medium in adjacent aluminum steel carries out planarization.These steps above repeating finally realize piling up of multiple layer metal.But owing to be difficult to copper is carried out dry etching, therefore, in the wiring process of copper, people have adopted the method in Damascus.So-called Damascus technics is derived from the technology that casts a sword in ancient Damascus.According to this technology, the first deposit medium of general at present employing, then by photoetching and etching, in dielectric layer, realize graphical, obtain the figure of needed copper connecting lines, and then deposit prevents the metal barrier and the copper seed layer of copper diffusion, the method for electricity consumption chemical plating again (ECP) is deposited to silicon chip surface with copper, use the method for chemical-mechanical planarization (CMP) that unnecessary copper, barrier layer are removed at last, realize planarization.Repeat the step of front, can realize piling up of multiple layer metal.So-called dual damascene, be with respect to single big horse scholar difference: it once can realize graphical and depositing metal in two layer medium, generate the through hole of metal, the figure of groove simultaneously that is:, and fills up through hole and groove in a step deposition process.
Meanwhile, the dielectric material of the positive active research application of people low-k reduces the influence that capacitor C causes, traditional dielectric material silicon dioxide (SiO
2, k=3.9-4.2) obviously can not satisfy the demands.Except positive searching had relatively low dielectric constant material, people also attempted to adopt to generate and mix up or method such as porous material reduces the dielectric constant of dielectric material.(form the fluorine silex glass except usually reducing dielectric constant as adding fluorine by other yuan of adding in silicon dioxide, k is about 3.7), also develop lower organic media of some dielectric constants such as SiLK (a kind of organic polymer low-K material), Black Diamond (black diamond technology) etc.In order further to reduce dielectric constant, people make loose structure with medium, make it more to approach the dielectric constant (dielectric constant of air is 1) of air.At present, the K value of porous SiLK etc. can reach 2.2 even lower.
Yet there are a lot of problems in the porous low dielectric material.At first, the dielectric constant of porous low dielectric material is along with the increase of the density in hole and diameter and reduce.Existence just because of material internal aperture (can reach the above diameter of 2nm), (etching finish after) can stay hole inevitably at the metal throuth hole and the metallic channel sidewall of medium after graphically finishing, this will cause causing the growth of barrier layer or copper seed layer discontinuous in the process of ensuing PVD (Physical Vapor Deposition physical vapour deposition (PVD)) or CVD (Chemical VaporDeposition chemical vapour deposition (CVD)) or ALD (Atomic Layer Deposition ald) deposit, cause metals such as copper to enter medium inside, influence device property; Perhaps in the metal deposition process, the hole in metal connecting line causes reliability problems.In addition, along with the increase of the inner hole of medium, dielectric constant can descend to some extent, but thing followed mechanical strength also can descend, and promptly Young's modulus will reduce greatly, and then bring contingency question.When carrying out chemical-mechanical planarization, Young's modulus generally need reach more than the 8GPa, peel off phenomenon otherwise medium can occur, and porous silica is reaching dielectric constant at 2.2 o'clock, and its Young's modulus only is 5GPa.
Therefore, aspect the sealing and mechanical strength in hole, need make improvement to the porous low dielectric material.At present, at the sealing problem in hole, people have proposed with processing methods such as ultraviolet ray (UV), electron beams, and wherein electron beam since the damage that may bring primer be eliminated.Also the someone proposes to form after the dual damascene figure in porous media, sidewall and the thin nonporous medium of bottom deposit one deck at through hole and groove, reach the purpose of closed hole, be as described in the patent of CN1591858 as patent publication No., via layer adopts low dielectric nonporous medium as the metal throuth hole layer, and deposit etching barrier layer thereon, and then deposit one deck porous low dielectric material, as the metallic channel layer, form figure therein by the dual damascene method, the nonporous medium that the one deck of growing thereon again is thin is realized the sealing to the porous media hole, utilize back then and carve the medium that removes the bottom, realize metal connecting line again.But because the mechanical strength of porous media own, this method is difficult to make its mechanical strength to obtain big raising.
[summary of the invention]
The objective of the invention is to overcome the porous low dielectric mechanical strength deficiency of prior art, adopted the method for twice dual damascene, form the medium of one deck atresia at the sidewall of the metal throuth hole of porous low dielectric medium and groove, make it reach sealing, and strengthened the mechanical strength of dielectric layer from structure, controlled the size of figure and the thickness of pattern and dielectric film preferably.
The present invention realizes by following technical method: a kind of method that seals porous low dielectric material aperture in the damascene structure, adopt the graphical PROCESS FOR TREATMENT of secondary double damask structure, the size of through hole on Damascus figure of the graphical PROCESS FOR TREATMENT formation of double damask structure and groove is greater than the size of graphic designs for the first time, after described through hole and groove being filled up with nonporous medium, it is graphical to carry out second time dual damascene again in this nonporous medium, the through hole that forms and the size of groove equal the size of graphic designs, with metal described through hole and groove are filled again, finish the interconnection of metal connecting line.
Wherein, described porous low dielectric material aperture reaches more than the 2nm.Described nonporous medium mechanical strength is greater than the porous low dielectric material, and dielectric constant is higher than the porous low dielectric material.The porous low dielectric material can be porous SiLK, porous silica, porous MSQ (methylsilsesquioxane, methyl silsesquioxane), a kind of among the porous SiOCH (silicon oxide carbide) or their combination.Nonporous medium is a kind of in silica, carborundum, silicon nitride, the nitrogen carbon silicon or their combination.Metal barrier is a kind of of tantalum nitride, tantalum or its combination.
A kind of method that seals porous low dielectric material aperture in the damascene structure of another technology provided by the invention is characterized in that may further comprise the steps: barrier layer, the first porous low dielectric material layer, first etching barrier layer, the second porous low dielectric material medium layer, second etching barrier layer on underlying substrate successively; Utilization traditional double damascene process is carried out graphically in porous low dielectric material medium layer, forms through hole and groove greater than design size, and etching is stopped at respectively on the barrier layer and first etching barrier layer on the substrate; Deposit nonporous medium in through hole that forms and groove fills up it; Utilize back the method for carving to realize planarization, etching is stopped on second etching barrier layer; The utilization dual damascene method second time carries out graphically reaching the desired size of design rule in nonporous medium again, forms metal throuth hole and groove; Etching is stopped at first etching barrier layer, and gets through the barrier layer on the substrate, and metal throuth hole is communicated with substrate; Depositing metal barrier layer in metal throuth hole and groove, the row metal line of going forward side by side is realized metallization, and is finally carried out planarization.
Wherein, described barrier layer is a silicon carbide layer.Described barrier layer is by the deposit of PECVD method, and thickness is 300A.Described porous low dielectric material can be porous SiLK, porous silica, porous MSQ, a kind of among the porous SiOCH or their combination.Described porous low dielectric material thickness is 3000A.
The method that forms first and second porous low dielectric material medium layer may further comprise the steps: 1. spin coating one deck porous low dielectric material; Again just silicon chip place hot environment to cure, dry its solvent also can not dissolve medium; 3. and then with silicon chip place the stove of filling with inert gas to solidify, form porous media structure.Described hot environment temperature is 200 degree.Described curing furnace temperature is 400 degree, and be 30 minutes curing time.
Described first and second etching barrier layer is a silicon carbide layer.Described first and second etching barrier layer adopts the PECVD deposit, and thickness is 500A.Described through hole and groove are greater than design size 50-100nm.Described nonporous medium is a kind of in silica, carborundum, silicon nitride, the nitrogen carbon silicon or their combination.Utilize PVD depositing metal barrier layer and copper seed crystal to silicon chip, and utilize electrochemistry plating depositing metal copper to silicon chip, carry out planarization at last.Described metal barrier is a kind of of tantalum nitride, tantalum or its combination.
The present invention utilizes the method for twice dual damascene, form the medium of one deck atresia at the sidewall of the metal throuth hole of porous low dielectric medium and groove, make it reach sealing, solved because the existence of aperture on dielectric material graphical back metal throuth hole and the metallic channel sidewall, and cause that metal barrier is discontinuous, to enter dielectric material by aperture during the conducting metal deposit and after the deposit inner and device is exerted an influence.Simultaneously, because the mechanical strength of nonporous medium is better than the porous low dielectric medium, can strengthen the mechanical strength of dielectric layer from structure.And because the method that all adopts dual damascene twice, the size of figure and pattern can be controlled preferably, reach the thickness of control medium film preferably.
[description of drawings]
Fig. 1 is the structural representation after intact required each layer of dual damascene process of deposit of the present invention;
Fig. 2 is that the present invention finishes dual damascene figure structural representation afterwards for the first time;
Fig. 3 is the structural representation after the intact nonporous medium of deposit of the present invention;
Fig. 4 is that the present invention carries out the graphical structural representation afterwards of dual damascene for the second time to nonporous medium;
Fig. 5 is that the present invention finishes metal barrier, metal connecting line deposit structural representation afterwards.
[embodiment]
Below in conjunction with accompanying drawing of the present invention, implementation step of the present invention is described further.
The present invention adopts the graphical PROCESS FOR TREATMENT of secondary double damask structure, the size of through hole on Damascus figure of the graphical PROCESS FOR TREATMENT formation of double damask structure and groove is greater than the size of graphic designs for the first time, after described through hole and groove being filled up with nonporous medium, it is graphical to carry out second time dual damascene again in this nonporous medium, the through hole that forms and the size of groove equal the size of graphic designs, with metal described through hole and groove are filled again, finish the interconnection of metal connecting line.
At first please refer to Fig. 1, Fig. 1 is the structural representation after intact required each layer of dual damascene process of deposit of the present invention.In Fig. 1, barrier layer 1, the first porous low dielectric material layer 2, first etching barrier layer 3, the second porous low dielectric material medium layer 4, second etching barrier layer 5 on underlying substrate 10 successively.At a specific embodiment that forms these five layers on the substrate successively can be: after on substrate 10, finishing lower pattern, by PECVD (Plasma Enhanced Chemical VaporDeposition plasma auxiliary chemical vapor deposition) method, growth one deck 300A carborundum is as barrier layer 1 on substrate 10.And then the method by spin coating, spin coating one deck 3000A porous SiLK places silicon chip 200 degree environment to cure as the first porous low dielectric material 2 again on barrier layer 1, so that dry solvent and medium can not be dissolved.And then place the stoves of 400 degree filling with inert gas to solidify 30 minutes the silicon chip, form porous media structure.Use PECVD (Plasma EnhancedChemical Vapor Deposition plasma auxiliary chemical vapor deposition) method thereon, growth one deck 500A carborundum is as etching barrier layer 3.By the method for spin coating, spin coating one deck 3000A porous SiLK places silicon chip 200 degree to cure, so that dry solvent and medium can not be dissolved as the second porous low dielectric material 4 again on barrier layer 1.Again silicon chip is placed the stove of 400 degree filling with inert gas to solidify 30 minutes, form porous media structure.Use PECVD (Plasma EnhancedChemical Vapor Deposition plasma auxiliary chemical vapor deposition) method thereon, growth one deck 500A carborundum is as barrier layer 5.
The first or second porous low dielectric material 2,4 here not only can be the porous SiLK that mentions among the above embodiment, a kind of among porous silica, porous MSQ, the porous SiOCH or their combination and other similarly have loose structure, and the material that has low dielectric property simultaneously can be used as the of the present invention first or second porous low dielectric material 2,4 too.Generally speaking, the of the present invention first or second porous low dielectric material 2,4 apertures reach more than the 2nm.
See also Fig. 2, Fig. 2 is that the present invention finishes dual damascene figure structural representation afterwards for the first time.In Fig. 2, utilization traditional double damascene process is carried out graphically in the first and second porous low dielectric material medium layers 2,4, forms through hole and groove greater than design size, and etching is stopped at respectively on the barrier layer 1 and first etching barrier layer 3 on the substrate.A preferred embodiment of the present invention is groove and the hole pattern of formation than the big 50-100nm of the actual design needed size of rule of exposing on silicon chip, utilize the big etching selection ratio of carborundum and photoresist, on carborundum, make a breach, and utilize the big etching selection ratio of SiLK and carborundum, make and be etched in being parked in after the SiLK etching on silicon carbide barrier layer 1 and 3, the needed figure of final formation obtains structure as shown in Figure 2.
Next, see also Fig. 3, Fig. 3 is the structural representation after the intact nonporous medium of deposit of the present invention.In Fig. 3, deposit nonporous medium 6 in rapid through hole that forms of previous step and groove fills up it.Utilize back the method for carving to realize planarization, etching is stopped on second etching barrier layer 5.A specific embodiment can be the method for utilization spin coating, fills up silicon dioxide in formed groove and through hole, obtains structure shown in Figure 3; Use back the method for carving again, silicon dioxide is carried out planarization, utilize the etching selection ratio of silicon dioxide and carborundum, it is rested on the silicon carbide barrier layer 5;
By above-mentioned introduction to etch step as can be known: barrier layer of the present invention 1 first and second etching barrier layer the 3, the 5th, silicon carbide layer can certainly be the material that other any photoresist and nonporous medium 6 have big etching selection ratio.
See also Fig. 4, Fig. 4 is that the present invention carries out the graphical structural representation afterwards of dual damascene for the second time to nonporous medium.The utilization dual damascene method second time carries out graphically reaching the desired size of design rule in nonporous medium 6 once more, form metal throuth hole and groove, etching is stopped at first etching barrier layer 3, and gets through the barrier layer 1 on the substrate 10, and metal throuth hole is communicated with substrate 10.A preferred embodiment is an etching selection ratio of utilizing silicon dioxide and carborundum, in silicon dioxide, carry out photoetching and etching, it is rested on the silicon carbide barrier layer 3, reach needed dimension of picture, and utilize the big etching selection ratio of carborundum and photoresist to get through barrier layer 1, through hole is connected with lower substrate 10, obtains structure shown in Figure 4.
See also Fig. 5 at last, Fig. 5 is that the present invention finishes metal barrier, metal connecting line deposit structural representation afterwards.
In the deposition process of double damask structure copper barrier layer.Copper is used in the integrated circuit fabrication process as new link material.Because copper is to the harmfulness of semiconductor device, thus before the cement copper, should first deposit one deck barrier layer, to prevent the diffusion of copper.The general at present ionized physical vapor deposition technology barrier layer that adopts.The effect that stops the copper diffusion has been played in the barrier layer between dielectric layer and copper.
The present invention is depositing metal barrier layer 7 in metal throuth hole and groove, and the row metal line 8 of going forward side by side is realized metallization, and finally carried out planarization.Concrete steps are to utilize PVD (Physical Vapor Deposition physical vapour deposition (PVD)) depositing metal barrier layer and copper seed crystal to silicon chip, and utilize electrochemistry plating depositing metal copper to silicon chip, carry out planarization at last.Described metal barrier 7 is a kind of of tantalum nitride, tantalum or its combination.
In a possible embodiment, utilize PVD depositing metal barrier layer tantalum nitride/tantalum and copper seed crystal to obtain silicon chip, and utilize electrochemistry plating (ECP) depositing metal copper to silicon chip, utilize chemical-mechanical planarization (CMP) to carry out planarization then.Finally obtain structure shown in Figure 5.
What more than introduce is basic implementation step of the present invention.Any to the invention process step do well know in the art be equal to change or replace all do not exceed creation of the present invention and protection range.
Claims (20)
1, a kind of method that seals porous low dielectric material aperture in the damascene structure, it is characterized in that: the graphical PROCESS FOR TREATMENT that adopts the secondary double damask structure, the size of through hole on Damascus figure of the graphical PROCESS FOR TREATMENT formation of double damask structure and groove is greater than the size of graphic designs for the first time, after described through hole and groove being filled up with nonporous medium, it is graphical to carry out second time dual damascene again in this nonporous medium, and the through hole of formation and the size of groove equal the size of graphic designs.
2, the method for porous low dielectric material aperture in the sealing damascene structure as claimed in claim 1, it is characterized in that: described porous low dielectric material aperture reaches more than the 2nm.
3, the method for porous low dielectric material aperture in the sealing damascene structure as claimed in claim 1, it is characterized in that: described nonporous medium mechanical strength is greater than the porous low dielectric material, and dielectric constant is higher than the porous low dielectric material.
4, the method for porous low dielectric material aperture in the sealing damascene structure as claimed in claim 1, it is characterized in that: described porous low dielectric material can be a porous organo polysilica compound low-K material, porous silica, the porous methyl silsesquioxane, a kind of in the porous carbon silica or their combination.
5, the method for porous low dielectric material aperture in the sealing damascene structure as claimed in claim 1 is characterized in that: described nonporous medium is a kind of in silica, carborundum, silicon nitride, the nitrogen carbon silicon or their combination.
6, the method for porous low dielectric material aperture in the sealing damascene structure as claimed in claim 1, it is characterized in that: metal barrier is a kind of of tantalum nitride, tantalum or its combination.
7, a kind of method that seals porous low dielectric material aperture in the damascene structure is characterized in that may further comprise the steps:
A) barrier layer, the first porous low dielectric material layer, first etching barrier layer, the second porous low dielectric material medium layer, second etching barrier layer on underlying substrate successively;
B) utilization traditional double damascene process is carried out graphically in porous low dielectric material medium layer, forms through hole and groove greater than design size, and etching is stopped at respectively on the barrier layer and first etching barrier layer on the substrate;
C) deposit nonporous medium in through hole that forms and groove fills up it;
D) utilize back the method for carving to realize planarization, etching is stopped on second etching barrier layer;
E) use dual damascene method for the second time again, in nonporous medium, carry out graphically reaching the desired size of design rule, form metal throuth hole and groove, etching is stopped at first etching barrier layer, and gets through the barrier layer on the substrate, and metal throuth hole is communicated with substrate;
F) depositing metal barrier layer in metal throuth hole and groove, the row metal line of going forward side by side is realized metallization, and is finally carried out planarization.
8, the method for porous low dielectric material aperture in the sealing damascene structure as claimed in claim 7, it is characterized in that: described barrier layer is a silicon carbide layer.
9, the method for porous low dielectric material aperture in the sealing damascene structure as claimed in claim 7 is characterized in that: described barrier layer is by the deposit of PECVD method, and thickness is 300A.
10, the method for porous low dielectric material aperture in the sealing damascene structure as claimed in claim 7, it is characterized in that: described porous low dielectric material can be the porous low dielectric constant silicon materials, porous silica, the porous methyl silsesquioxane, a kind of in the porous carbon silica or their combination.
11, the method for porous low dielectric material aperture in the sealing damascene structure as claimed in claim 7, it is characterized in that: described porous low dielectric material thickness is 3000A.
12, the method for porous low dielectric material aperture in the sealing damascene structure as claimed in claim 7, it is characterized in that: the method that forms first and second porous low dielectric material medium layer may further comprise the steps: 1. spin coating one deck porous low dielectric material; Again just silicon chip place hot environment to cure, dry its solvent also can not dissolve medium; 3. and then with silicon chip place the stove of filling with inert gas to solidify, form porous media structure.
13, the method for porous low dielectric material aperture in the sealing damascene structure as claimed in claim 12 is characterized in that: described hot environment temperature is 200 degree.
14, the method for porous low dielectric material aperture in the sealing damascene structure as claimed in claim 12 is characterized in that: described curing furnace temperature is 400 degree, and be 30 minutes curing time.
15, the method for porous low dielectric material aperture in the sealing damascene structure as claimed in claim 7, it is characterized in that: described first and second etching barrier layer is a silicon carbide layer.
16, the method for porous low dielectric material aperture in the sealing damascene structure as claimed in claim 7 is characterized in that: described first and second etching barrier layer adopts the PECVD deposit, and thickness is 500A.
17, the method for porous low dielectric material aperture in the sealing damascene structure as claimed in claim 7, it is characterized in that: through hole described in the step b and groove are greater than design size 50-100nm.
18, the method for porous low dielectric material aperture in the sealing damascene structure as claimed in claim 7 is characterized in that: described nonporous medium is a kind of in silica, carborundum, silicon nitride, the nitrogen carbon silicon or their combination.
19, the method for porous low dielectric material aperture in the sealing damascene structure as claimed in claim 7, it is characterized in that: step e further may further comprise the steps: utilize PVD depositing metal barrier layer and copper seed crystal to silicon chip, and utilize electrochemistry plating depositing metal copper to silicon chip, carry out planarization at last.
20, the method for porous low dielectric material aperture in the sealing damascene structure as claimed in claim 7, it is characterized in that: described metal barrier is a kind of of tantalum nitride, tantalum or its combination.
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Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101383397B (en) * | 2007-09-04 | 2010-06-02 | 财团法人工业技术研究院 | Phase change memory device and fabrication method thereof |
| CN101924063A (en) * | 2009-06-11 | 2010-12-22 | 新加坡格罗方德半导体制造私人有限公司 | Use the integrated circuit (IC) system and the manufacture method thereof of low-K dielectric |
| CN102237304A (en) * | 2011-07-05 | 2011-11-09 | 复旦大学 | Method for inhibiting porous low dielectric constant medium from absorbing water vapor |
| CN102315163A (en) * | 2011-09-28 | 2012-01-11 | 上海华力微电子有限公司 | Manufacturing method of ultralow-dielectric-constant film copper-interconnecting layer |
| CN102412188A (en) * | 2011-05-13 | 2012-04-11 | 上海华力微电子有限公司 | Metal hard mask dual damascene process of super-thick top metal |
| CN103165514A (en) * | 2011-12-08 | 2013-06-19 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and forming method thereof |
| CN112786525A (en) * | 2019-11-07 | 2021-05-11 | 长鑫存储技术有限公司 | Semiconductor device and method of forming the same |
| CN114156231A (en) * | 2021-11-04 | 2022-03-08 | 上海至临半导体技术有限公司 | Method for improving wafer bridging wire structure |
| CN114975361A (en) * | 2022-05-20 | 2022-08-30 | 江苏芯德半导体科技有限公司 | Ultra-narrow-spacing PI layer opening method and semiconductor packaging structure |
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Cited By (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101383397B (en) * | 2007-09-04 | 2010-06-02 | 财团法人工业技术研究院 | Phase change memory device and fabrication method thereof |
| CN101924063A (en) * | 2009-06-11 | 2010-12-22 | 新加坡格罗方德半导体制造私人有限公司 | Use the integrated circuit (IC) system and the manufacture method thereof of low-K dielectric |
| CN102412188A (en) * | 2011-05-13 | 2012-04-11 | 上海华力微电子有限公司 | Metal hard mask dual damascene process of super-thick top metal |
| CN102237304A (en) * | 2011-07-05 | 2011-11-09 | 复旦大学 | Method for inhibiting porous low dielectric constant medium from absorbing water vapor |
| CN102315163A (en) * | 2011-09-28 | 2012-01-11 | 上海华力微电子有限公司 | Manufacturing method of ultralow-dielectric-constant film copper-interconnecting layer |
| CN103165514A (en) * | 2011-12-08 | 2013-06-19 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and forming method thereof |
| CN103165514B (en) * | 2011-12-08 | 2015-07-08 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and forming method thereof |
| CN112786525A (en) * | 2019-11-07 | 2021-05-11 | 长鑫存储技术有限公司 | Semiconductor device and method of forming the same |
| CN112786525B (en) * | 2019-11-07 | 2023-07-07 | 长鑫存储技术有限公司 | Semiconductor device and method of forming the same |
| CN114156231A (en) * | 2021-11-04 | 2022-03-08 | 上海至临半导体技术有限公司 | Method for improving wafer bridging wire structure |
| CN114156231B (en) * | 2021-11-04 | 2024-09-20 | 上海至临半导体技术有限公司 | Method for improving structure of wafer bridging wire |
| CN114975361A (en) * | 2022-05-20 | 2022-08-30 | 江苏芯德半导体科技有限公司 | Ultra-narrow-spacing PI layer opening method and semiconductor packaging structure |
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