CN101006406A - Method and apparatus for intelligently setting dead time - Google Patents
Method and apparatus for intelligently setting dead time Download PDFInfo
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- CN101006406A CN101006406A CN 200580022904 CN200580022904A CN101006406A CN 101006406 A CN101006406 A CN 101006406A CN 200580022904 CN200580022904 CN 200580022904 CN 200580022904 A CN200580022904 A CN 200580022904A CN 101006406 A CN101006406 A CN 101006406A
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Abstract
Apparatus for setting dead time between ON times of two series connected switches of a power converter circuit connected across a supply potential, the apparatus comprising a circuit for monitoring a power converter circuit parameter and providing an output corresponding to the circuit parameter; a memory addressed by a signal related to the output of the monitoring circuit, the memory having values stored therein related to the dead times and associated with values of the circuit parameter; a processor providing an output of the memory associated with the value of the circuit parameter to set the dead time corresponding to the stored value in the memory, and a dead time implementing stage for implementing the dead time in accordance with the output of the memory.
Description
Related application
That the application requires to submit on July 6th, 2004, name is called " Intelligent Dead Time ", sequence number is No.60/585, the right of priority of 678 U.S. Provisional Patent Application, its whole disclosures are hereby expressly incorporated by to be quoted.
Background technology
The present invention relates to power supply and relate in particular to the electric pressure converter that adopts two controlled switchs, one of them switch is as synchronous rectifier work.Described two switches are controlled as two switches usually and never open simultaneously.Provide " Dead Time " to prevent the cross-conduction in dc voltage source between the opening time of two switches, wherein said two switches are connected between the described dc voltage source.
In the low-voltage output translator of voltage-dropping type (Buck), booster type (boost), inverse-excitation type (fly back) and positive activation type various topologys such as (forward), extensively adopted synchronous rectifier.By adopting switch mosfet substituted for silicon or Schottky (Schottky) diode, can reduce rectifier loss significantly.
For synchronous converter, keeping the non-overlapped cycle (Dead Time) is very important with the excessive cross-conduction that prevents gauge tap and synchronous rectifier switch.The additional conduction loss that is used for producing during significantly overlapping power loss penalty and the Dead Time is compared much higher.
However, the Dead Time loss is extremely important, particularly when the converter frequency of operation increases.The synchronous buck converter that use has a following characteristic is as example:
Frequency of operation=1Mhz
Input voltage=12 volt
Output voltage=1 volt
Output current=40 ampere
Synchro switch opening resistor=3 milliohms
The synchro switch body diode is the forward operating voltage (VF@40A)=0.8 volt of 40 ampere-hours at electric current
The real-time power loss is 4.8 watts when synchro switch FET opens, and when the body diode conducting is only arranged is 32 watts.Under these conditions, be converted into the power attenuation of additional 27mW at the Dead Time of per nanosecond.Two toggle edges in each cycle of 20ns Dead Time cause in the synchro switch 1.088 watts additional loss respectively, and the loss of this element has been increased by 20%.Use the schottky diode in parallel this numeral can be reduced 30% to 40%, but can bring additional cost and number of elements with described MOSFET.
In addition, in case the body diode conducting of synchro switch is easy to be subjected to the influence of inversion recovery cycle and associated charge, this must eliminate in connection.This is equivalent to cross-conduction and has caused added losses among the control FET.
The present invention is conceived to make the minimum power losses related with Dead Time.This is by Dead Time is minimized with the conduction loss of reduction body diode and in some cases by allowing the conducting of FET switch cross to realize to eliminate the loss that thereby the body diode conducting is eliminated with oppositely recovery is relevant fully.
The technology that has multiple reduction Dead Time at present.Comprise:
The adjustable dead band time.Thereby regulate during the design phase Dead Time under all working condition and the whole process that realizes all elements that described Dead Time relates to avoid cross-conduction in changing.It may be important that semi-conductive process changes, and circuit may be worked in wide in range scope.Therefore, when realize not having when intersection by the worst case element under worst case conditions, the Dead Time under optimal cases element and the condition is too much.The power consumption that causes excess waste like this.
The adaptive dead zone time.The adaptive dead zone time is a kind of improvement with respect to the adjustable deadband time, wherein along with condition changing and when the component variation one by one the carrying out of unit regulate simultaneously.This is logic control in essence, and the grid of one of them switch (gate) is detected at the grid of another switch and is prevented from opening before closing.To the eye, this has solved problem, but does not in fact have.Logic control and the grid of power switch self charged and discharge need the limited time cycle.In actual conditions, caused the Dead Time about the 10ns to 30ns when T.T. is each switch transition in each cycle of 20ns to 60ns like this.
The prediction Dead Time.The subject matter of adaptive dead zone time is to switch the FET required time of opening and closing.Thereby the prediction Dead Time has solved this defective until it near zero to reduce Dead Time by using phaselocked loop or some other ring.Seemed to provide a lot of advantages identical like this, but be to use control loop to have attendant disadvantages with the present invention.Since this method depend on certain kind control loop so that Dead Time to be set, in this ring, also exist association really immediately between.In transient condition, when described ring tries to settle into new steady state (SS) cross-conduction may take place.Fixing Dead Time to be avoiding cross-conduction if programmed in described ring, and then most of described times are can be than minimum Dead Time bigger and dependent loss is more.Under any circumstance, described ring solution depends on some electrical conditions and the loss related with Dead Time minimized arbitrarily.Test result shows that this method can not produce minimum possible power consumption.
Minimise power consumption Dead Time (PLMDT).This technology has all advantages of the present invention, and the optimum dead zone time of " memory " various conditions of work is not provided with except it.For power work, this optimization needs for a long time-tens of milliseconds.This means that in quick load transient environments, the PLMDT operation can not be caught up with power source change.Averaging allows the PLMDT circuit to find the mean value of under large-scale load current " optimum " of optimum work.Effect is fine like this, but still can not obtain accurately suitable Dead Time to each electric current.To be the applicant submit to February 16 in 2005 PLMDT, the theme of the patented claim IR-2673 that determines of end, U. S. application number 11/058,969 simultaneously, and its full content is incorporated into this as quoting.
Fig. 4 has shown the converter circuit that comprises transistor Q1 and Q2, and wherein PLMDT is used to be provided with Dead Time.The variation of the duty factor of pwm signal 10 is used to the estimating power loss and changes.Multiplication module 22 is used to by pwm signal modulation V
IN(supply voltage of switch Q1 and Q2) produces the signal DxV that is proportional to duty factor
INThis signal produces slow variable signal through low-pass filter 24, if the output voltage when this slow variable signal equals not have transducer loss.This signal (DxV
IN) be exaggerated (kxDxV by factor k
IN) and be split to two paths.One paths directly arrives judges comparer 26, another paths offer judge comparer 26 before through for example sampling and keeping module 28.Described sampling and maintenance module 28 are used to preserve last time " kxDxV
IN" signal, thereby the signal that produces after can changing with Dead Time is relatively.
Fig. 4 shown sampling and kept module 28, but sampling and keep the function can accomplished in various ways comprises, for example uses " N " bit memory or other equivalence techniqueses.Similarly, comparator function can be carried out by for example logic value comparer or other equivalence techniqueses.
Dead Time processor 20 (DTP) among Fig. 4 can be realized by logical circuit, microcontroller or microprocessor.DTP20 control sampling and holding circuit 28 are provided with Dead Time by Dead Time modulator 16 and 18, and handle " better (the Better) " signal from the output of judging comparer.If new signal (current D) is less than last signal (D last time), then new Dead Time " better " (comparer is output as height) and DTP20 preserve current new Dead Time value.Otherwise abandon described new Dead Time and recover old Dead Time.After changing Dead Time, need certain delay to allow the power supply feedback circuit to establish new duty factor.Several factors may influence this time, but in fact about 100 times of times of power supply switching cycle seem comparatively suitable.
Although do not need to prove principle, but in fact, DTP20 preferably before specific Dead Time is made final conclusion, averages a plurality of judgements in relative cycle long period, to obtain reliability and to prevent because the wrong dead band time setting that noise or transient state cause.Need hundreds of or more sample.The average so effectively influence of quick load transient to power supply.If use some additive method except that duty factor to determine power consumption, also can use identical averaging.
PLMDT can use combine digital PWM or digital signal processing (DSP) and realize, but rudimentary algorithm is identical in fact.
Fig. 5 has shown rudimentary algorithm, and this algorithm can be realized by digital signal processor, microprocessor, microcontroller or the logic state machine that realizes PLMDT.The example that has wherein also shown the program that realizes by Fig. 4 circuit fully.
With reference to figure 5, only shown the flow process of close synchronously (sync-off) passage.As described below, sync-on channel flow is identical in fact.From A, suppose that the result who is provided with sync-off delay and previous (previous) Dead Time is the power consumption that last time, (last) Dead Time produced, show that last time, sampling was better than previous sampling, promptly produce lower dutycycle and lower power consumption, the "Yes" by point " A " enters flow process.The test counter that count down to " N " increases progressively 50.In 52 samplings and preserve current power consumption.As shown in 54, Dead Time is shortened or reduces a step-length.This means to close to postpone to be increased, because Dead Time has been reduced.Whether be arbitrarily to Dead Time when initial if increasing or reducing.Yet, because target reduces power consumption and this is to realize by reducing Dead Time, so Dead Time preferably is reduced when initial.At the second portion (II) of Fig. 5 flow process, Dead Time is increased, and realizes producing the Dead Time of more low-power consumption.
Realize to postpone to allow as at the establishment supply voltage shown in 56.Now will new power consumption (after Dead Time changes) and old power consumption comparison 58.As shown in the 58A, old power consumption is saved by previous step 52.If new power consumption lower (for example determining by dutycycle), shown in determination module 60, then flow process proceeds to module 62, and wherein " better " counter is incremented.Described " better " counting keeps following the tracks of the number of times that new power consumption is better than old power consumption.
If new power consumption is not better than old power consumption in step 60, then counter does not increase progressively.Flow process proceeds to determination module 66 to determine whether N test is finished then.As mentioned above, preferably repeatedly test to obtain reliable results.If N test do not finished, flow process route via 69.71, recover last time Dead Time and in 73, realize postponing allowing establishing power supply, and test counter increases progressively 50 once more, and compare with old power consumption once more.In case finish N test, then arrive outlet 68.Dead Time was realized in step 54 last time.Carry out N test to guarantee it relatively is reliably, consider, then may lead to errors if only carry out the single test for for example noise or load transient.By repeatedly testing, can obtain higher degree of accuracy and fiduciary level.
In step 68, determine whether that N/2+1 time test is more excellent, that is to say whether " better " counter shows the power consumption more excellent above the test shows of half.If then enter the part ii of flow process by flow line 70.If there is no N/2+1 time more excellent test then recovers old Dead Time 74, and realizes postponing 75 before proceeding to step 76.
In step 76, test counter " N " increases progressively once more.Current power consumption is saved 78,80 Dead Time is increased a step-length, reduces sync-off delay.82, realize postponing to allow to establish power supply.84, relatively in the old power consumption 84A of step 78 preservation and new power consumption.Old power consumption display is in 84A.In step 86, determine whether new power consumption is lower along with Dead Time increases.If new power consumption is lower, then increase progressively " better " counter 88.If new power consumption is not lower or after 88 increase progressively described better counter, check to determine whether to have finished N test.If no, then return and increase progressively test counter once more, and compare once more 84 76 by path 93.In case in step 90, finished N test, then in 92, checked to determine that most cases is for more excellent in N the test.If such situation, then flow process proceeds to sync-on channel flow, and this flow process synchronous off channel example with shown in Figure 5 in fact is identical.Handling the sync-on channel Dead Time in the mode identical with synchronous off channel example shown in Figure 5 postpones.Therefore, in sync-on channel, can carry out similar flow process, it is older power consumption and corresponding to the new power consumption of the Dead Time that increases and reduce, if power consumption is more excellent, then keep new Dead Time, if power consumption is not more excellent, then recover old Dead Time, come down to as the mode in the synchronous off channel example shown in Figure 5.
The PLMDT technology has produced the Dead Time of optimizing.Yet the result is based on the compromise of averaging circuit condition rather than based on the accurate optimal value of instant condition of work.Intelligent Dead Time disclosed herein (IDT) has solved " speed " problem related with PLMDT.
Summary of the invention
According to the present invention, the equipment of the Dead Time between the opening time of two tandem taps that the power converter circuit that provides a kind of setting to be connected to supply voltage is interior, described equipment comprises: circuit is used for monitoring power converter circuit parameter and output corresponding to described circuit parameter is provided; Storer is addressed by the signal relevant with the output of described monitoring circuit, has stored in the described storer about described Dead Time and the value related with the value of described circuit parameter; Processor provides the storer output related with the value of described circuit parameter, to be provided with corresponding to the Dead Time that is stored in the value in the described storer; And Dead Time realization level, be used for realizing described Dead Time according to the output of described storer.
The present invention also comprises the method for the Dead Time between the opening time that two tandem taps in the power converter circuit be connected to supply voltage are set, and described method comprises monitoring power converter circuit parameter and output corresponding to described circuit parameter is provided; By the signal relevant storer is carried out addressing, stored in the described storer about described Dead Time and the value related with the value of described circuit parameter with described output; Provide the storer output related, to be provided with corresponding to the Dead Time that is stored in the value in the described storer with the value of described circuit parameter; And realize described Dead Time according to the output of described storer.
The present invention can be applied to be directly connected to the switch of supply voltage, and the topology that may be separated by transformer of two switches, for example in synchronous boost type, inverse-excitation type or positive activation type converter.
According to one aspect of the invention, be called intelligent Dead Time (IDT) at this, thereby use look-up table or suitable closing form to solve scheme and change Dead Time in response to changing converter and initial conditions.All use storer preservation Dead Time value or coefficient in order to waiting a moment use in both cases.When outage, keep this storer if desired, then need to use nonvolatile memory.Directly store look-up tables still solves scheme for closing form, can storage coefficient.
In a kind of enforcement, can use the minimum power losses Dead Time (PLMDT) (seeing above-mentioned while pending application application) of certain form, thereby with respect to the Dead Time of circuit condition map out optimum.Finish this process and have some selections.
By PLMDT, according to making the minimized mode of overall converter power losses change Dead Time.Can use Several Methods to come monitoring power consumption, comprise the combination that monitors the input and output voltage and current.If input and output voltage is fixed, then only need standby current, and if use averaging, then only need to measure input current.Yet tool cost efficiency is to use the relative tolerance of gauge tap duty factor as power attenuation with method easily.Thereby when the adjusting Dead Time minimizes duty factor, converter power losses is minimized.In a kind of enforcement, error amplifier output is used to substitute duty factor.This is possible, because error signal is the modulation input of PWM level.Therefore, the PWM duty factor is proportional to error voltage.
In one embodiment of the invention, thus use the Dead Time value of preserving after this can make minimum power losses and do not need at the moment according to PLMDT technology spending time search optimal value by PLMDT.Although preferably use PLMDT, also can adopt other technologies to upgrade the Dead Time value of being stored.
The Dead Time value of being stored can be determined in the design phase of prototype.An advantage of this selection is need not comprise the PLMDT circuit in final the application.Major defect is manufacturing changeability, component tolerance and the component ageing that Dead Time selects to comprise expectation.Can force the conservative more setting of use like this, cause the suboptimum loss.
If (typically in driver IC) combined the PLMDT circuit during the product after design was used, then can when starting first, shine upon Dead Time.The advantage of doing like this is manufacturing and component tolerance can be combined in the dead band time setting.Shortcoming is not comprise component ageing, must allow to wear out thereby be provided with.Sort circuit is optimized more than the design phase calibration, but still not ideal enough.Yet it is enough good using for majority.
Preferred selection is to shine upon with periodic intervals at the whole life period that product is used from the performance starting point.In this way, in case find optimized setting, then can be periodically updated.For example, PLMDT can periodically call to determine to be stored in the new optimized value in the storer in system.
Other features and advantages of the present invention can be clearer by following detailed description with reference to the accompanying drawings.
Description of drawings
With reference now to the more detailed description the present invention of accompanying drawing,, wherein:
Fig. 1 is the structural drawing of an embodiment realizing in a circuit according to the invention;
Figure 1A has shown second embodiment;
Fig. 2 has shown the waveform of the circuit of Fig. 1 or 1A;
Fig. 3 is the process flow diagram of the algorithm realized in the Digital Implementation of the present invention;
Fig. 4 has shown the circuit of realization minimum power losses Dead Time (PLMDT), and described circuit can use to update stored in the Dead Time value in the storer together in conjunction with the present invention; And
Fig. 5 has shown the process flow diagram of realizing the algorithm of PLMDT.
Embodiment
Refer again to accompanying drawing, Fig. 1 has shown that a kind of of converter circuit who realizes according to intelligent Dead Time of the present invention (IDT) method may realize.Various other realizations also are possible, because flesh and blood of the present invention is " memory " optimum Dead Time in the power work scope, and when after this needing " memory " then.By the condition under the described system monitoring according to the difference that realizes and difference still can comprise: input voltage, output current (for example synchronous switch current) and mosfet driver temperature.
Fig. 1 has shown a kind of may realize in conjunction with digital and analog circuit of the present invention.Other realizations also are possible, and most module and function can be implemented as digital circuit and mimic channel.
Fig. 1 has shown the DC-DC converter circuit, thereby this circuit is modified to comprise according to technology of the present invention minimise power consumption during Dead Time makes Dead Time is set intelligently.Preferably, described circuit is based on periodically adopting PLMDT to optimize and the renewal Dead Time.Described converter comprises two switch Q1 and Q2 (being generally MOSFET), at power supply node V
INAnd connect between the ground connection.Converter shown in the figure is a buck converter, but the present invention can be applied to any type of switched-mode power supply with synchronous rectification.
As known, the switching node N of buck converter is coupled to load by outputting inductance L.Output capacitance C is coupling in the load two ends.The gate driver circuit 2 that the grid of each switch Q1 and Q2 shows by signal and 4 and below with the adjunct circuit of describing is coupled to pulse-length modulation (PWM) signal from PWM controller 12 (be respectively control and synchronously).Because gate drive signal is complementary, signal has shown inverter 6 in a gate driving passage.As known, in buck converter, switch Q1 is as gauge tap work, and switch Q2 is as synchronous rectifier work.
Produce pwm signal 10 by PWM controller 12 with known manner.Pwm signal 10 postpones by fixed delay block 14.Allow programmable Dead Time scope to comprise positive and negative Dead Time value like this.The shut-in time and the opening time of synchro switch Q2 signal can change, and as shown in Figure 2, thereby change the Dead Time amount.Open synchronously and postpone for example to realize that modulator 16 can comprise for example counter, tapped (tapped) simulation or digital delay line or single-shot circuit (single shot circuit) by 4 Dead Time modulators 16.Same, realize sync-off delay by similar modulator 18.They are independently programmed by Dead Time processor 20A and allow independent regulation to open synchronously and the sync-off delay time.
In example shown in Figure 1, the output that monitors 3 A/D converters 15 of the electric current among the transistor Q2 is used to directly storer 23 be carried out addressing, storer 23 can be the part of processor 20A, comprise determine by 3 bits 8 kinds may current level in each dead band time setting.Although as shown in the figure 3 bit pads, also can use to have the more i.e. converter of multidigit more of high resolving power.Counter 25 uses as lock usually, and along with memory content is loaded together to be sent to Dead Time modulator 16 and 18.These modulators are worked in the manner described above realizing Dead Time, and identical with the modulator that uses in the PLMDT technology.
Fig. 1 shown by the electric current in the parallel switch S 1 that connects of sensing and monitored the Q2 electric current, and S1 can be for carrying the more transistor switch of low current, and the electric current among its electric current and the Q2 has to be determined to concern.Switch S 1 has realized sampling and holding circuit and during the FET opening time that continues potential destructive voltage has been isolated from A/D converter 15.Other current sense solutions also are possible.For example, can use and export the simple sensing resistor RS that switch Q1 and Q2 (seeing Figure 1A) connect or the average dc voltage V at inductance L (seeing Figure 1A) two ends
DCIndicate as electric current.
Fig. 2 has shown the waveform of circuit shown in Figure 1.Wherein shown pwm signal 10.Signal controlling (CONTROL) postpones by the fixed delay of Postponement module 14.The signal Synchronization (SYNC) that offers the grid of synchro switch Q2 has variable sync-off delay and variable synchronous unlatching delay as mentioned above, thereby determines the Dead Time between signal CONTROL and the SYNC.The close synchronously signal is determined by DTP 20A and offers modulator 18 as 4 position digital signals.The output of modulator 18 is provided for D bistable multivibrator 30, and D bistable multivibrator 30 is removed D bistable multivibrator 32, off switch Q2 when variable delay after setting.Similarly, modulator 16 is opened switch Q2 by D bistable multivibrator 32 is set when selected variable unlatching postpones.When bistable multivibrator 32 is output as when high, switch Q2 is unlocked.When bistable multivibrator 32 is output as when low, remove bistable multivibrator 30, thereby bistable multivibrator 30 will be set up when the next sync-off delay of being determined by modulator 18.Can in synchronizing channel, realize positive and negative Dead Time effectively thereby the fixed delay in the control channel 14 postpones enough time quantum modulators 16 and 18 with the CONTROL pwm signal, effectively allow to open synchronously according to the requirement that realizes selected Dead Time and close synchronously is delayed or shift to an earlier date.
Dead Time processor 20A preferably realizes the PLMDT algorithms by module 27 as mentioned above and in above-mentioned while pending application application.Provide signal corresponding to power attenuation to PLMDT module 27 by power attenuation testing circuit 40.Preferably, the duty factor of circuit monitors pwm signal as shown in the figure, but also can monitor other parameters.Circuit 40 can comprise element for example shown in Figure 4 22 and 24, and the signal that is proportional to duty factor and the power attenuation related with each Dead Time are provided.In another implementation, can determine power attenuation by the error amplifier output that monitors the pwm circuit of indicating duty factor.This is shown as the circuit of realizing PLMDT in Figure 1A.The output of error amplifier 11 can be used to refer to duty factor and power attenuation.This is because error signal is the modulation input of PWM level.Therefore, the PWM duty factor is proportional to error voltage.PLMDT module 27 (preferably periodically) when being called is carried out the steps necessary of PLMDT algorithm to determine optimum Dead Time.As above described about the description of PLMDT, PLMDT module 27 can be the combination of numeral, simulation and software function.
Preferably, the PLMDT algorithm is periodically implemented.In the case, counter 25 can be used to test greater than with the Dead Time that is lower than the value of preserving in the storer (DT) value to check that wherein whether one be provided with than current DT and have lower loss.
Fig. 3 has shown the basic operation sequence of IDT.
With reference to figure 3, in step 100, when Q2 opens, the electric current among the sensing Q2.By the output of A/D converter 15 storer 23 is carried out addressing in step 110, described A/D converter 15 provides the digital value of sensing circuit.The content of storer 23 is corresponding to the Dead Time (open synchronously and postpone and synchronous turn-off delay) of the corresponding mapping value of Q2 electric current.At step 120 counter 25 load id T memory contents.Enable counter 25 outputs in step 130 and give modulator 16 and 18 so that new DT value (open synchronously and postpone and sync-off delay) to be provided.
Q2 is being closed (140) by the appropriate time in the determined PWM of the sync-off delay cycle then.In 150, check then to determine whether to realize PLMDT.If not, then return round-robin and begin the place and open Q2 and repetitive cycling once more.If arrived the time (preferred periodically realization) of realizing PLMDT 150, then realize the PLMDT algorithm 27 of processor 20A and upgrade the IDT storer with new, more excellent minimum power losses Dead Time (for the Q2 electric current that senses), the IDT storer that has upgraded is used to be implemented once more up to PLMDT in the next cycle.In one implementation, increase progressively by counter and the Dead Time value of testing of successively decreasing above and below storing value in the storer more excellent so which to be checked.
IDT can change the DT value of power cycle based on the cycle.Therefore there is not the load transient problem of operative association therewith.On the other hand, when periodically calling PLMDT, must be noted that and guarantee that the DT value of being stored is actual value corresponding to correct electric current.Consider can be by the result in the tens of millisecond the is averaged optimum PLMDT that finishes, above points for attention should finish.
Thereby a kind of method that realizes this operation is to use PLMDT circuit map out optimum Dead Time when power supply starts first.These values can be stored in the nonvolatile memory and use with the whole life period at power supply.This can by first between the starting period good the loading to power supply and in whole range of current, progressively change (stepping) described load then of application definition realize.
According to the present invention, make Dead Time control optimization, thereby make minimum power losses, and do not need the correct Dead Time of spended time search.Use net result just power attenuation rather than wave edges or synchro switch forward voltage Dead Time is set, avoided the secondary power loss in other sources.Because always select minimum power attenuation, so do not need to know the relative importance of minor cross conduction for the loss reduction in the reverse recovery of synchro switch.
Although described the present invention with reference to specific embodiment, those skilled in the art can easily make variations and modifications and other uses to it.Therefore, the present invention is not limited to certain content disclosed herein, but only is defined by the following claims.
Claims (53)
1. a setting is connected to the equipment of the Dead Time between opening time of two tandem taps in the power converter circuit of supply voltage, and described equipment comprises:
Circuit is used for monitoring power converter circuit parameter and output corresponding to described circuit parameter is provided;
Storer is addressed by the signal relevant with the output of monitoring circuit, has stored in the described storer about described Dead Time and the value related with the value of described circuit parameter;
Processor provides the storer output related with the value of described circuit parameter, to be provided with corresponding to the Dead Time that is stored in the value in the described storer; And
Dead Time is realized level, is used for realizing described Dead Time according to the output of described storer.
2. equipment according to claim 1, wherein said processor comprise and are used for updating stored in the value of described storer so that the device of the minimise power consumption during the Dead Time in seclected time.
3. equipment according to claim 1, the value that wherein is stored in the described storer is stored in the storer at described converter circuit during the design.
4. equipment according to claim 1, wherein said storer comprises look-up table.
5. equipment according to claim 1, wherein be stored in value in the described storer and be connected to first at described converter circuit and be stored in the storer when load and power supply are provided for described converter circuit, by the circuit parameter in the working range that this value is mapped to described converter circuit this value is stored in the described storer thus.
6. equipment according to claim 1, wherein said circuit parameter comprise the temperature through input voltage or at least one described switch of the electric current of a described switch, described power converter circuit.
7. equipment according to claim 6, one of them described switch is a synchronous rectifier, and described circuit parameter comprises the electric current through a described switch.
8. equipment according to claim 7, wherein said monitoring circuit comprises current sensing circuit, is used to monitor the electric current through a described switch.
9. equipment according to claim 8, wherein said current detection circuit comprise the sensing resistor of connecting with described switch or use the circuit of average dc voltage at the outputting inductance two ends of described power converter circuit.
10. equipment according to claim 8, wherein said current sensing circuit comprise the second switch with described switch in parallel coupling.
11. equipment according to claim 1, wherein said monitoring circuit comprises A/D converter, is used to provide the digital value corresponding to described circuit parameter.
12. equipment according to claim 11, wherein said A/D converter provide output so that described storer is carried out addressing, thus described storer produce be stored in storer in related, corresponding with the described circuit parameter value of Dead Time.
13. equipment according to claim 12, it further comprises lock-in circuit, is used for that the value from described storer is offered described Dead Time and realizes level.
14. equipment according to claim 13, wherein said lock-in circuit comprises up-down counter.
15. equipment according to claim 14, wherein said processor comprises and is used for updating stored in the value of described storer so that the device of the minimise power consumption during the Dead Time in seclected time, and wherein said counter increases progressively the value from described storer and successively decreases, and whether produces lower power consumption with the value of determining to be greater than or less than from the value of described storer.
16. equipment according to claim 15, it further comprises circuit, is used for the value corresponding to the power consumption of the Dead Time of being realized is offered described processor.
Be used for determining the power consumption related and make device with the related minimise power consumption of Dead Time 17. equipment according to claim 2, the wherein said device that is used for updating stored in the value of described storer comprise with Dead Time.
18. monitoring, equipment according to claim 17, the wherein said device that is used for determining power consumption offers at least one the dutycycle of pwm signal of described two switches.
19. equipment according to claim 17 wherein saidly is used for determining that the device of power consumption monitors error signal output, described error signal output provides modulation to input to be used for producing and offers at least one the circuit of pwm signal of described two switches.
20. equipment according to claim 17, wherein said device is updated periodically the value in the described storer.
21. the level that realizes equipment according to claim 20, wherein said Dead Time realizes the control signal of a described switch variable closed and to the variable unlatching of the control signal of a described switch.
22. equipment according to claim 21, synchronous rectification carried out by a wherein said switch and another switch is a gauge tap.
23. equipment according to claim 21, wherein said device are included in the module corresponding to the described pulse width modulating signal of selected instantaneous sampling in the time of first and second Dead Times; And the processor that is used to control the timing of described sampling.
24. equipment according to claim 23, wherein said Dead Time realize that level comprises first and second variable delay circuits by described processor control.
25. equipment according to claim 24, wherein said first and second variable delay circuits receive the numeral input from described processor, amount time delay of the opening and closing of the described switch of described processor selection.
26. equipment according to claim 2, wherein said device postpones to change Dead Time by changing variable unlatching, and monitor that after described change selected parameter is to determine whether power consumption is lower, if power consumption is lower, realize that then described unlatching postpones, if and power consumption is not lower, the unlatching that then recovers previous postpones, and further, wherein said device postpones to change Dead Time by changing variable closing, and monitors that after described change selected parameter is to determine whether power consumption is lower, if power consumption is lower, then realize the described delay of closing, and if power consumption not lower, then recover the previous delay of closing.
27. equipment according to claim 26, wherein said device transmits each first and second signal realizes level to described Dead Time, thereby before the control signal of controlling a described switch is unlocked and closes, select the closing of control signal of another described switch to postpone and open to postpone respectively.
28. equipment according to claim 27, it further comprises the fixed delay level, is used to postpone to control the control signal of a described switch.
29. equipment according to claim 28, wherein said fixed delay level allow described Dead Time to realize that level realizes positive and negative Dead Time amount.
30. equipment according to claim 1, wherein said processor comprises any one in digital signal processor, microprocessor, microcontroller or the logical circuit.
31. equipment according to claim 1, wherein said two switches comprise semiconductor switch.
32. equipment according to claim 31, wherein said two switches comprise MOSFET.
33. a setting is connected to the method for the Dead Time between opening time of two tandem taps in the power converter circuit of supply voltage, described method comprises:
Monitoring power converter circuit parameter and output corresponding to described circuit parameter is provided;
By the signal relevant storer is carried out addressing, stored in the described storer about described Dead Time and the value related with the value of described circuit parameter with described output;
Provide the storer related to export to be provided with corresponding to the Dead Time that is stored in the value in the described storer with the value of described circuit parameter; And
Output according to described storer realizes described Dead Time.
34. method according to claim 33, it further is included in the value that updates stored in seclected time in the described storer, so that the minimise power consumption during the Dead Time.
35. method according to claim 33, it further is included in described converter circuit during the design and stores described value in described storer.
36. method according to claim 33, it further is included in the described value of storage in the look-up table.
37. method according to claim 33, it further is included in described converter circuit when being connected to load first and power supply being provided to described converter circuit, described value is stored in the described storer, by the circuit parameter in the working range that described value is mapped to described converter circuit described value is stored in the described storer thus.
38. method according to claim 33, wherein said circuit parameter comprise the temperature through input voltage or at least one described switch of the electric current of a described switch, described power converter circuit.
39. according to the described method of claim 38, one of them described switch is a synchronous rectifier, and described circuit parameter comprises the electric current through a described switch.
40. according to the described method of claim 39, wherein said monitoring step comprises the electric current that monitors through a described switch.
41. according to the described method of claim 40, wherein said monitoring step comprises the electric current of sensing by the sensing resistor of connecting with described switch, perhaps uses the average dc voltage at the outputting inductance two ends of described power converter circuit.
42. method according to claim 33, the digital value that provides corresponding to described circuit parameter is provided wherein said monitoring step.
43. according to the described method of claim 42, it further comprises provides described digital value so that described storer is carried out addressing, thus described storer produce be stored in wherein Dead Time related, corresponding to the value of described circuit parameter.
44. according to the described method of claim 43, it further is included in and upgrades the described value that is stored in the storer seclected time, so that the minimise power consumption during the Dead Time, and it further comprises the value from described storer is increased progressively and successively decreases, and whether produces lower power consumption with the value of determining to be greater than or less than from the value of described storer.
45. according to the described method of claim 44, it further comprises the value of determining corresponding to being the power consumption of realization Dead Time.
Determine the power consumption related and make the minimise power consumption related 46. method according to claim 34, the wherein said step that updates stored in the value in the described storer comprise with Dead Time with Dead Time.
47. according to the described method of claim 46, the step of wherein said definite power consumption comprises that supervision offers the dutycycle of at least one pwm signal in described two switches.
48. according to the described method of claim 46, the step of wherein said definite power consumption comprises and monitor error signal output, described error signal output provides modulation to input to be used for producing and offers at least one the circuit of pwm signal of described two switches.
49. according to the described method of claim 46, wherein said step of updating comprises the value that is updated periodically in the described storer.
50 according to the described method of claim 49, and the step of wherein said realization Dead Time comprises that realization is closed the control signal of a described switch variable and to the variable unlatching of the control signal of a described switch.
51. according to the described method of claim 50, synchronous rectification carried out by a wherein said switch and another switch is a gauge tap.
52. method according to claim 34, the wherein said step that updates stored in the value in the described storer comprises by changing variable unlatching and postpones to change Dead Time, and monitor that after described change selected parameter is to determine whether power consumption is lower, if power consumption is lower, realize that then described unlatching postpones, if and power consumption is not lower, the unlatching that then recovers previous postpones, and further comprise by changing variable closing and postpone to change Dead Time, and monitor that after described change selected parameter is to determine whether power consumption is lower, if power consumption is lower, then realize the described delay of closing, if and power consumption is not lower, then recover the previous delay of closing.
53. one kind make with the power converter circuit that is connected to supply voltage in opening time of two tandem taps between the equipment of the related minimise power consumption of Dead Time, described equipment comprises:
Control device is used to monitor the related selected parameter of power consumption during the Dead Time with described converter;
Described control device changes to second Dead Time with Dead Time from first Dead Time, and relatively with the power consumption of the described selected parameter association of described first and second Dead Times, and which is littler to determine the power consumption related with described two Dead Times;
Dead Time is realized level, is used to realize described two Dead Times; And
Described control device is selected the Dead Time related with described littler power consumption and is provided signal to realize grade so that selected Dead Time to be set to described Dead Time, and wherein said selected parameter comprises from the output of the error signal of error amplifier, and described error signal output provides modulation to input to be used for producing and offers at least one the circuit of pwm signal of described two switches.
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US58567804P | 2004-07-06 | 2004-07-06 | |
| US60/585,678 | 2004-07-06 | ||
| US11/172,163 | 2005-06-30 |
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|---|---|---|---|
| CN 200580022904 Pending CN101006406A (en) | 2004-07-06 | 2005-07-05 | Method and apparatus for intelligently setting dead time |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI465026B (en) * | 2008-07-25 | 2014-12-11 | Cirrus Logic Inc | Resonant switching power circuit, method of controlling switching in resonant switching power circuit and integrated circuit controller |
| CN104410300A (en) * | 2014-11-24 | 2015-03-11 | 深圳创维－Rgb电子有限公司 | Synchronous rectification drive circuit and television set |
| CN105207452A (en) * | 2015-09-14 | 2015-12-30 | 江苏物联网研究发展中心 | IGBT drive circuit |
| CN107707121A (en) * | 2017-11-20 | 2018-02-16 | 电子科技大学 | Switch converters adaptive dead zone generation circuit based on body diode conduction detection |
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2005
- 2005-07-05 CN CN 200580022904 patent/CN101006406A/en active Pending
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI465026B (en) * | 2008-07-25 | 2014-12-11 | Cirrus Logic Inc | Resonant switching power circuit, method of controlling switching in resonant switching power circuit and integrated circuit controller |
| CN104410300A (en) * | 2014-11-24 | 2015-03-11 | 深圳创维－Rgb电子有限公司 | Synchronous rectification drive circuit and television set |
| CN104410300B (en) * | 2014-11-24 | 2016-09-21 | 深圳创维－Rgb电子有限公司 | Synchronous rectification driving circuit and television set |
| CN105207452A (en) * | 2015-09-14 | 2015-12-30 | 江苏物联网研究发展中心 | IGBT drive circuit |
| CN107707121A (en) * | 2017-11-20 | 2018-02-16 | 电子科技大学 | Switch converters adaptive dead zone generation circuit based on body diode conduction detection |
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