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CN1006597B - 制造薄膜线条的方法 - Google Patents

制造薄膜线条的方法

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Publication number
CN1006597B
CN1006597B CN86102448A CN86102448A CN1006597B CN 1006597 B CN1006597 B CN 1006597B CN 86102448 A CN86102448 A CN 86102448A CN 86102448 A CN86102448 A CN 86102448A CN 1006597 B CN1006597 B CN 1006597B
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CN86102448A (zh
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吉亚姆比罗·弗拉里斯
阿东尼奥·特萨尔维
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Xi Mensi Telecommunications Co
Italtel SpA
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    • GPHYSICS
    • G03PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03FPHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/004Photosensitive materials
    • G03F7/022Quinonediazides
    • G03F7/023Macromolecular quinonediazides; Macromolecular additives, e.g. binders
    • G03F7/0233Macromolecular quinonediazides; Macromolecular additives, e.g. binders characterised by the polymeric binders or the macromolecular additives other than the macromolecular quinonediazides
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814Conductive parts
    • H01L21/4846Leads on or in insulating or insulated substrates, e.g. metallisation
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/10Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
    • H05K3/108Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern by semi-additive methods; masks therefor
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/03Use of materials for the substrate
    • H05K1/0306Inorganic insulating substrates, e.g. ceramic, glass
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/05Patterning and lithography; Masks; Details of resist
    • H05K2203/0548Masks
    • H05K2203/0554Metal used as mask for etching vias, e.g. by laser ablation
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/05Patterning and lithography; Masks; Details of resist
    • H05K2203/0562Details of resist
    • H05K2203/0577Double layer of resist having the same pattern
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/05Patterning and lithography; Masks; Details of resist
    • H05K2203/0562Details of resist
    • H05K2203/0585Second resist used as mask for selective stripping of first resist
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/09Treatments involving charged particles
    • H05K2203/095Plasma, e.g. for treating a substrate to improve adhesion with a conductor or for cleaning holes
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/14Related to the order of processing steps
    • H05K2203/1476Same or similar kind of process performed in phases, e.g. coarse patterning followed by fine patterning
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/0011Working of insulating substrates or insulating layers
    • H05K3/0017Etching of the substrate by chemical or physical means
    • H05K3/0041Etching of the substrate by chemical or physical means by plasma etching
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/38Improvement of the adhesion between the insulating substrate and the metal
    • H05K3/388Improvement of the adhesion between the insulating substrate and the metal by the use of a metallic or inorganic thin film adhesion layer

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  • Spectroscopy & Molecular Physics (AREA)
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  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
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  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Laminated Bodies (AREA)
  • Inorganic Insulating Materials (AREA)
  • Drying Of Semiconductors (AREA)
  • Weting (AREA)
  • Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
  • Manufacturing Of Printed Wiring (AREA)

Abstract

本发明叙述了一种利用光刻厚的光致抗蚀剂,并继而电化选择生长金属的技术制造薄膜线条的方法。本发明的方法可以制得具有高分辨率的非常薄(2-10微米)的线条(8),即侧壁面(9)几乎是垂直的,宽度的公差仅约一微米。这种结果是采取了下列措施取得的,即采用聚酰亚胺作厚的光致抗蚀剂(3),让其经历特殊的固化期,采用特殊的干蚀刻工艺在聚酰亚胺层上制得凹座(6),其后,在凹座(6)内制备线条(8)。

Description

本发明涉及利用光刻厚的光致抗蚀剂,并继而电化选择产生金属的技术来制造薄膜线条的方法。
大家知道,以现有技术可得到高厚度(5-7微米)的薄膜线条。其最小宽度有40-50微米,宽度的公差是5-8微米。
当前,微波领域的趋势是在越来越高的频率(20-30GHZ),同时具有高的特性阻抗(200-300欧姆)和集总电路情况下采用薄膜线条。因而必须采用高厚度(5-7微米)的宽度约4-10微米,高分辩率的,并具有几乎是垂直的侧壁面,公差小到约1微米的薄膜线条。
大家也已知道,高分辩率的线条可以用真空溅射金的技术来获得,但是这种技术的生长速度是非常低的,所以实际上不能应用在大规模生产上。另外,由于这种方法必须首先在整个绝缘基片上溅射上金后再制造线条,因而金的浪费是极大的。用这种方法还存在着线条侧腐蚀的缺点,其侧腐蚀的宽度至少等于其厚度,所以线条的侧壁面产生凹陷。
进一步说,大家已经知道,使用电化选择生产技术可以获得好的生长速度,金也只是加在传导电路上。但是,以现在这样的技术不可能获得所要求的线条分辩率和精度。实际上,需要生长金的凹座是在厚的光致抗蚀剂的基底上制得的。为了要使凹座的壁面符合机械强度的要求,须进行热处理过程。然而热处理使壁面遭损变园,因此生长金后所得到的线条变成了很不规则的蘑菇形。
本发明的一个目的是要克服上述的弊端,提出了一种用光刻厚的光致抗蚀剂,并继而电化选择生长金属的技术制得具有高分辩率,几乎垂直的侧壁面和最大宽度公差大约1微米的薄膜线条的方法。
为了达到上述的目的,本发明涉及利用光刻厚的光致抗蚀剂,并继而电化选择生长金属以制道薄膜线条的方法。其特点为,这种厚的光致抗蚀剂的制造是先在绝缘基片上涂覆一层聚酰亚胺,进行第一次固化,再第二次涂覆一层聚酰亚胺,并进行第二次固化。
本发明的进一步的目的和优点,从下面最佳实施方案详细描述和附图中可以清楚地看出。但这只是举例说明,本发明的内容不仅限于此。这里图1到图11表示了按本发明用光刻厚的光致抗蚀剂的方法制造薄膜线条一个周期的各步骤。
参照附图,制造线条的方法按下面的步骤(工序)进行:
图1:在基片1,即氧化铝、玻璃、兰宝石、氧化铍基片上用真空阴极溅射法敷金属,所敷金属实际含有一个氮化钽电阻层,一个钛粘结层和一个钯防扩散层,它们构成一个三重层(2),总厚度为4000-5000埃。
图2:离心涂覆第一层厚度2-5微米的聚酰亚胺层3a,在反射炉中进行第一次固化,温度范围为120~150℃,时间约2小时,接着温度在170~220℃范围为内,时间2小时。然后,离心涂覆第二层厚度为2~5微米的聚酰亚胺层3b,第二次固化仍是在反射炉中进行,温度范围150~170℃,约2小时,温度范围为170~220℃时也是2小时。聚酰亚胺3a和3b二层完全贴合,形成一均匀的聚酰亚胺层3,总厚度为4~10微米。
图3:在聚酰亚胺层3上用真空阴极溅射法沉积氧化钛层4,厚 度为1000埃。
图4:在氧化钛层4上离心涂覆光敏漆层5,厚度为0.8微米。
图5:该光敏漆层5,通过一金属掩膜,进行紫外曝光,显影后形成10微米宽的凹座6。这些凸座的宽度决定于所要求的线条宽度。按本发明的加工目标,可形成宽度为2微米的线条。
图6:用氢氟酸蚀刻氧化钛金属层4,在氧化钛金属层4处也形成凹座6。
图7:将中间制品沉浸在由生产光敏漆厂家推荐的溶液中,除去光敏漆层5。
图8:在具有高压力(4-8毫巴)和射频13.56兆赫的低密度激发能(2-7瓦/厘米2)的氧气等离子体中对聚酰亚胺进行干蚀刻5-10分钟,借此在聚酰亚胺层3中也同样得到了具有几乎垂直的侧壁面7的凹座6。
图9:在聚酰亚胺层3中所形成的凹座6内,选择性地电化淀积金属。例如,金、银、铜。结果在凹座6内得到了导线8,其厚度为3-7微米,侧壁面9几乎是垂直的。
图10:用氢氟酸溶液除去氧化钛金属层4。
图11:在具有高压力(4-8毫巴)和射频13.56兆赫的低密度激发能(2-7瓦/厘米2),的氧气等离子体中进行干性蚀刻5-10分钟,完全去除聚酰亚胺。在不撤除真空下,吸去氧气等离子体,引入氩气,在低压力(2-4×104毫巴)和高密度的激发能(9-15瓦/厘米2)下,继续干蚀刻5-10分钟,其时三重金属层也完全除去。
整个方法可以制得线段8,其宽变为2-10微米,厚度3-7 微米,其壁面9几乎是垂直的,宽度公差为±0.5微米。能得到这样的结果是由于采用了聚酰亚胺这样的材料来产生凹座6,并对聚酰亚胺进行固化,以及选择了合适的干蚀刻的参数。实际上,使用了聚酰亚胺,特别是特殊的初始固化周期,保证了聚酰亚胺层3的优良的机械强度,而蚀刻的方法和合适的参数的选择。使制得的凹座6能保证其壁7有优良的分辩率。
本发明的制造薄膜线条的方法,其优点是显而易见的。特别是从下面的事实中可以看出,该工艺制造的线条,宽度在2-10微米,厚度3-7微米。其公差仅为0.5微米。跟先有技术相比,得到了明显的改善,线条宽度减小20倍,而宽度的公差减小了10倍。这些线条具有非常好的理论设计价值,可望制造出相互靠得很近的线段。就金属的用量来说,本发明只消耗按精确计算所必须的用量,尤其对金来说,本发明在经济上的节约是非常可观的。此外,因工作时间缩短,从而进一步降低了生产成本。
本领域的技术人员知道,在不脱离本发明范围的情况下,本工艺可有很多改良形式。

Claims (13)

1、一种利用光刻厚的光致抗蚀剂,并继而电化选择生长金属的技术在绝缘基底上制造薄膜线条的方法,其特征在于:
在绝缘基底上敷盖一金属性层;
制备厚光致抗蚀剂:在金属性层上涂覆第一层聚酰亚胺,接着进行第一次固化,再继以涂覆第二层聚酰亚胺,并接着进行第二次固化,该第一和第二层聚酰亚胺固化层形成单一均匀的聚酰亚胺层;
在聚酰亚胺层敷盖一金属层;
在金属层上敷盖一光敏漆层;
使该光敏漆通过使用金属掩膜被紫外光曝光;
使曝光的光敏漆显影,从而在光敏层上得到一些凹座;
蚀刻所述金属层从而在金属层上产生一些凹座;
在第一次特定时间内用氧气等离子体对聚酰亚胺层进行蚀刻;
该蚀刻在聚酰亚胺层上产生壁几乎是垂直的凹座;
在凹座内电化选择沉积金属线条,该金属线条的特点是其壁几乎是垂直的;
去除所述金属层;
在第二次特定时间内用氧气等离子体对聚酰亚胺进行蚀刻;
在该第二次特定的时间之后,用氩气代替氧气在第三次特定的时间是再进行蚀刻。
2、按权利要求1所述的制造薄膜线条的方法,其特征在于所说的氧气等离子体蚀刻要求在高压和低密度激发能下进行。
3、按权利要求2所述的制造薄膜线条的方法,其特征在于所说的氧气等离子体的压力在4到8毫巴之间,激发能的密度在2和7瓦/厘米2之间。
4、按权利要求1所述的制造薄膜线条的方法,其特征在于其中所述的第一次蚀刻时间在5~10分钟之间。
5、按权利要求1所述的制造薄膜线条的方法,其特征在于所说的用氩气进行的第三次蚀刻,在低压力和高密度的激发能下进行。
6、按权利要求5所述的制造薄膜线条的方法,其特征在于氩气的压力在2×10-4至4×10-4毫巴之间,氩气的激发能密度在9至15瓦/厘米2之间。
7、按权利要求1所述的制造薄膜线条的方法,其特征为所说的第三蚀刻时间为5至10分钟。
8、利用权利要求1的方法制造的高厚度薄膜金属线条,其特征在于其侧壁面(9)几乎的垂直的。
9、按权利要求8所述的高厚度薄膜金属线条,其特征在于该侧壁面(9)的宽度公差在于±0.5微米之间。
10、按权利要求8所述的高厚薄膜金属线条,其特征在于该线条的宽度在2至10微米之间,厚度在3至7微米之间。
11、按权利要求8所述的高厚度薄膜金属线条,其特征在于使用的金属是金。
12、按权利要求8所述的高厚度薄膜金属线条,其特征在于使用的金属是银。
13、按权利要求8所述的高厚度薄膜金属线条,其特征在于使用的金属是铜。
CN86102448A 1985-05-03 1986-04-19 制造薄膜线条的方法 Expired CN1006597B (zh)

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IT (1) IT1184535B (zh)
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CN110028670A (zh) * 2019-04-11 2019-07-19 明士新材料有限公司 低介电损耗负性光敏聚酰胺酸酯树脂、树脂组合物、其制备方法及应用

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US4367119A (en) * 1980-08-18 1983-01-04 International Business Machines Corporation Planar multi-level metal process with built-in etch stop
US4451971A (en) * 1982-08-02 1984-06-05 Fairchild Camera And Instrument Corporation Lift-off wafer processing
US4555414A (en) * 1983-04-15 1985-11-26 Polyonics Corporation Process for producing composite product having patterned metal layer
JPS59202636A (ja) * 1983-05-04 1984-11-16 Hitachi Ltd 微細パタ−ン形成方法
US4523976A (en) * 1984-07-02 1985-06-18 Motorola, Inc. Method for forming semiconductor devices
JPS61242044A (ja) * 1985-04-19 1986-10-28 Matsushita Electronics Corp 半導体装置の製造方法
US4606998A (en) * 1985-04-30 1986-08-19 International Business Machines Corporation Barrierless high-temperature lift-off process

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IT1184535B (it) 1987-10-28
IT8520567A0 (it) 1985-05-03
JPS61255029A (ja) 1986-11-12
NO861090L (no) 1986-11-04
US4812388A (en) 1989-03-14
AU5485286A (en) 1986-11-06
ZA862336B (en) 1986-11-26
EP0200237A3 (en) 1988-09-07
EP0200237A2 (en) 1986-11-05
AU585955B2 (en) 1989-06-29
CN86102448A (zh) 1986-10-29

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