CN100583653C

CN100583653C - An encoding method, decoding method and decoder of LDPC cascade connection code

Info

Publication number: CN100583653C
Application number: CN200810056049A
Authority: CN
Inventors: 王达; 管武; 董明科; 金野; 项海格
Original assignee: Peking University
Current assignee: Peking University
Priority date: 2008-01-11
Filing date: 2008-01-11
Publication date: 2010-01-20
Anticipated expiration: 2028-01-11
Also published as: CN101217284A

Abstract

The invention discloses a design scheme of LDPC cascaded code, which is an LDPC-SPC product code which takes LDPC code as horizontal code and SPC code as vertical code, and each bit of an SPC code word is acquired by the even parity check of the bits in corresponding positions of n LDPC code words. The scheme can solve the flat bed of error codes of the LDPC code and has higher flexibility and greater encoding gain than the cascaded methods of BCH code. The invention simultaneously provides an encoding method of the LDPC-SPC product code and two decoding methods (a hard decision method and a soft decision iteration method), and provides corresponding decoders. The LDPC-SPC product code provided by the invention can acquire greater encoding gain with very small redundancy cost and is a signal channel encoding scheme which is applicable to delay-insensitive businesses.

Description

Encoding method, decoding method and decoder of LDPC (Low Density parity check) concatenated code

Technical Field

The invention relates to a channel coding technology, in particular to a construction and decoding method of an LDPC (low density parity check) concatenated code, belonging to the technical field of information.

Background

As a basic technology for ensuring reliable transmission of a communication system, a channel coding technology has been rapidly developed in the last decade, and a large number of channel codes, whose performance can approach a theoretical limit, represented by a Turbo code and an LDPC code (low density parity check code), which has been particularly spotlighted in recent years, have been successively discovered and intensively studied, wherein the LDPC code has been particularly spotlighted because of having an error correction performance approaching a shannon limit and a simple decoding algorithm suitable for parallel computation, and has been adopted by many communication standards, such as DVB-S2, WiMAX, and the like. This indicates that LDPC codes will become a dominant channel coding in communication systems for a considerable period of time in the future.

Research on near-shannon limit codes such as Turbo codes and LDPC codes shows that the error rate curve of the near-shannon limit codes can be divided into two areas, namely a waterfall (waterfall) area and a floor (floor) area, different from all previous channel codes. In the waterfall region, the bit error rate near the shannon limit code decreases rapidly as the normalized signal-to-noise ratio increases, and the bit error rate curve now appears almost perpendicular to the x-axis. In the flat zone, the rate of the bit Error rate of the near shannon limit code is reduced obviously relative to the waterfall zone along with the increase of the normalized signal to noise ratio, and even the rate of the bit Error rate is not reduced any more, the bit Error rate curve looks like a platform parallel to the x axis at the moment, and the Error flat zone (Error Floor) is named accordingly.

Unlike the error floor of Turbo code, which is mainly caused by its small weight codeword, in the Additive White Gaussian Noise (AWGN) channel, the error floor of LDPC code is mainly determined by its acquisition set (trapping). When the error floor of the LDPC code appears, the probability that the iterative decoding algorithm converges to an approximate code word (near code word) close to the correct code word is increased. The "approximate codeword" can satisfy most of the check equation constraints. Therefore, the error floor phenomenon of the LDPC code has two characteristics, one is that when the code length of the LDPC code is long, for example, reaches a length of several thousands of bits, the error floor thereof is mainly determined by "approximate codewords", because they cannot satisfy all check relations, the erroneous codewords can be detected by the decoder; secondly, because the approximate code word is very similar to the correct code word, the number of error bits in each error code word is not too large.

For example: the error curve of the LDPC code with the length of 8064 bits and the code rate of 1/2 is shown in FIG. 1. The LDPC code starts to generate an error code leveling layer when the normalized signal-to-noise ratio is equal to 1.5dB, and 200 error LDPC code words are respectively counted when the normalized signal-to-noise ratios are respectively 1.5dB and 1.6dB in order to analyze the error code leveling layer.

The statistical result shows that under two normalized signal-to-noise ratios, 200 error code words respectively counted cannot meet the check relation of the H matrix, and therefore the error code words can be detected by the LDPC decoder, and the first characteristic is met. Secondly, as can be seen from fig. 2, in 200 error code words counted respectively at two signal-to-noise ratios, although the number of error bits exceeding 10 bits at 1.5dB is slightly more than the statistical result at 1.6dB, in both signal-to-noise ratios, the number of errors occurring in one code word exceeding 10 bits is not more than 10%, and the maximum number of error bits is only 25 bits. The number of error bits is much smaller than 8064 bits of code length, and the statistical result is well in line with the second characteristic mentioned above regarding the error-leveling layer of the LDPC code. Interestingly, it can also be seen from fig. 2 that when the decoder reaches the maximum number of iterations and the decoding fails, a significant proportion of the erroneous LDPC codewords are only 1 bit erroneous. This occurs because the check equations in which the erroneous bits participate typically contain two or more bits with confidence soft information near 0. In each iteration process of the sum-product algorithm, the confidence soft information of the bits with low confidence coefficient will be continuously inverted above or below 0, so that the LDPC decoder can not converge to the correct code word all the time.

When the error floor occurs in the LDPC code, in order to analyze whether error bits of multiple error code words occur at the same position, the positions of the error bits are counted when normalized signal-to-noise ratios are 1.5dB and 1.6dB, respectively, as can be seen from fig. 3, under two normalized signal-to-noise ratios, most of the bit positions where errors occur are only once erroneous, and the bit positions where errors occur twice or more are only 20% of all the error bit positions. If statistics are performed once for every n LDPC codewords, the ratio of bit positions where errors occur twice or more in the n LDPC codewords is smaller. For example, if two or more codewords are erroneous in every 100 LDPC code words, the bit positions where two or more errors occur are less than 1% of all the erroneous bit positions in these erroneous codewords. That is, within 100 LDPC codewords, it is rare that the same bit position occurs twice or more errors.

The error floor phenomenon has plagued the implementation of many communication systems that require high error performance. Therefore, the study on the error-level layer of the LDPC code has been an important study direction in the field of channel coding in recent years. At present, three methods are mainly used for overcoming the error code level of the LDPC code, one method is an algebraic method, the purpose of reducing the error code level is mainly achieved by constructing the LDPC code with a large minimum code distance, and the defects are that the performance of the LDPC code with the large minimum code distance is not ideal and the constructed parameters are not continuous; the second method is to adopt ACE criterion in the construction process of LDPC code, although the method can construct a code with lower decoding threshold, the effect of reducing error code threshold is limited; the third method is to concatenate the LDPC code with the BCH code, which is also the most common method. The method takes BCH as an outer code and LDPC as an inner code, and information code words to be coded enter a BCH coder to generate BCH coded code words, and then enter the LDPC coder to generate final coded output code words. The decoding is the reverse process of the encoding, the received code word firstly enters an LDPC decoder, a BCH code word is decoded and sent to the BCH decoder for decoding, and the final decoding result is output.

A large number of simulation results show that the LDPC-BCH cascade code can effectively reduce the error code level of the LDPC code to 10^-11The following can satisfy the needs of most systems. However, this method has two main disadvantages, one is that the redundancy cost is high, because the BCH code has no simple soft-decision decoding algorithm, usually only a hard-decision algorithm can be adopted, and the coding gain loss is large; secondly, the actual communication system often has many different code rates, which requires the BCH code to provide different code lengths and different error correction capabilities for the LDPC codes with different code rates, and increases the difficulty of the design of the concatenated code scheme and the complexity of the coding and decoding system.

Disclosure of Invention

Aiming at the current situation of the LDPC code, the invention provides a new and better LDPC cascade code scheme and a coding and decoding scheme thereof in order to better reduce the error code level of the LDPC code and improve the error code performance of the LDPC code. The specific coding scheme is as follows:

1. initialization: framing the information bit stream;

2. and performing modulo-2 summation on bits of each n information frames at corresponding positions, wherein n is a positive integer and can be selected according to actual needs. I.e. the n +1 th redundant frame is

Wherein N is the length of the information frame and is a positive integer;

3. the n +1 information frames are sequentially passed through an LDPC code encoder to obtain n +1 LDPC code words, wherein the n +1 LDPC code words are redundant code words, the redundant code words are named as Single Parity Check (SPC) codes in the invention, and as the LDPC code is a linear block code, each bit of the SPC code word is obtained by parity check of the bits of the n LDPC code words at corresponding positions, if the jth bit of the SPC code word is c_SPC ^jThe jth bit of the ith code word of the n LDPC code words is

Then there are:

the coded code word pattern is shown in fig. 4, and it can be seen from the figure that the LDPC concatenated code scheme proposed by the present invention is an LDPC-SPC product code scheme in which an LDPC code is a horizontal code and an SPC code is a vertical code. As can be seen from the encoding process, the SPC code words are also LDPC code words that conform to the same H matrix constraint. If the code rate of the LDPC code is R, the code rate of the obtained LDPC-SPC product code is n · R/(n +1), wherein n is a positive integer.

In theory n can take any positive integer from 1 to positive infinity. However, because the coding of the LDPC-SPC product code is to add an SPC redundant code word on the basis of the LDPC code, the loss of the normalized signal-to-noise ratio isWhen the value of n is small, the coding redundancy is large, the loss of the signal-to-noise ratio is large, and the error code performance of the LDPC is not improved; however, when n is large, although the coding redundancy brought by the n is negligible, the number of error code words that may occur in n LDPC code words is correspondingly increased, which increases the complexity of the decoding method. The invention is obtained through a large number of simulation results, the value of n between 50 and 400 is a reasonable choice, the coding redundancy can be ignored at the moment, and the complexity of the decoding method is not large. Of course, the value of n may be increased or decreased according to actual needs.

As can be seen from the analysis in the background art, almost all error code words can be detected when the error-floor of the LDPC code occurs. By utilizing the error detection characteristic of the LDPC code, the invention provides two decoding methods of the LDPC-SPC product code: a hard decision method and a soft decision iteration method.

The hard decision decoding method of the LDPC-SPC product code comprises the following steps:

1. initialization: sequentially decoding every n LDPC code words and 1 SPC code word by the LDPC code decoder, namely enabling the ith LDPC code word

And entering an LDPC code decoder for decoding, wherein i is cycled from 1 to n +1,

C_{{LDPC}_{n + 1}} = C_{SPC},

obtaining hard decision results of n +1 LDPC code decoding;

2. according to the characteristic that an LDPC code decoder can detect errors, various error patterns in n +1 LDPC codes can be counted, and the specific processing is as follows:

a) if no code word decoding fails in the n +1 LDPC code words, the decoding is finished;

b) if the decoding of more than 1 code word in the n +1 LDPC code words fails, the decoding is finished;

c) if only one of the n +1 LDPC code words fails to be decoded, two cases can be considered:

i. if the wrong code word is the SPC code, the SPC code can be directly deleted as the SPC code is the redundancy check code word, the first n correct LDPC codes are output, and the decoding is finished;

if the erroneous codeword is one of the first n LDPC codes, proceed to step 3.

3. And restoring a correct code word according to the even check relation of the SPC code word, wherein the specific processing steps are as follows:

3-1 deleting the LDPC code words in error;

3-2, performing modulo-2 sum on the rest n correct LDPC code words bit by bit in the column direction, wherein the obtained result is the recovered correct code word;

3-3 outputs the recovered correct codeword.

Wherein the proof of step 3-2 is as follows:

due to the fact that

The jth bit of the erroneous codeword

<math> <mrow> <msubsup> <mi>c</mi> <mi>Error</mi> <mi>j</mi> </msubsup> <mo>=</mo> <msubsup> <mi>c</mi> <mi>SPC</mi> <mi>j</mi> </msubsup> <mo>+</mo> <msubsup> <mi>c</mi> <mrow> <mi>LDP</mi> <msub> <mi>C</mi> <mn>1</mn> </msub> </mrow> <mi>j</mi> </msubsup> <mo>+</mo> <msubsup> <mi>c</mi> <mrow> <mi>LDP</mi> <msub> <mi>C</mi> <mn>2</mn> </msub> </mrow> <mi>j</mi> </msubsup> <mo>+</mo> <msubsup> <mi>c</mi> <mrow> <mi>LDP</mi> <msub> <mi>C</mi> <mn>3</mn> </msub> </mrow> <mi>j</mi> </msubsup> <mo>+</mo> <mo>·</mo> <mo>·</mo> <mo>·</mo> <mo>+</mo> <msubsup> <mi>c</mi> <mrow> <mi>Error</mi> <mo>-</mo> <mn>1</mn> </mrow> <mi>j</mi> </msubsup> <mo>+</mo> <msubsup> <mi>c</mi> <mrow> <mi>Error</mi> <mo>+</mo> <mn>1</mn> </mrow> <mi>j</mi> </msubsup> <mo>+</mo> <mo>·</mo> <mo>·</mo> <mo>·</mo> <mo>+</mo> <msubsup> <mi>c</mi> <mrow> <mi>LDP</mi> <msub> <mi>C</mi> <mi>n</mi> </msub> </mrow> <mi>j</mi> </msubsup> <mi>mod</mi> <mn>2</mn> <mo>,</mo> </mrow> </math>

Namely, it is

<math> <mrow> <msubsup> <mi>c</mi> <mi>Error</mi> <mi>j</mi> </msubsup> <mo>=</mo> <munderover> <mi>Σ</mi> <mfenced open='' close=''> <mtable> <mtr> <mtd> <mi>k</mi> <mo>=</mo> <mn>1</mn> </mtd> </mtr> <mtr> <mtd> <mi>k</mi> <mo>&NotEqual;</mo> <mi>Error</mi> </mtd> </mtr> </mtable> </mfenced> <mrow> <mi>n</mi> <mo>=</mo> <mn>1</mn> </mrow> </munderover> <msubsup> <mi>c</mi> <mrow> <mi>LDP</mi> <msub> <mi>C</mi> <mi>k</mi> </msub> </mrow> <mi>j</mi> </msubsup> <mi>mod</mi> <mn>2</mn> <mo>.</mo> </mrow> </math>

Obtaining the syndrome.

Through the steps, it is not difficult to find that the LDPC-SPC product code hard decision decoding method can only correct the condition that only one error code word appears in every n +1 LDPC code words, so that the decoding performance of the LDPC-SPC product code hard decision decoding method is related to the error code word rate of the LDPC code and can be obtained through calculation and estimation. The error probability of each LDPC code word before cascade connection is set as P, after cascade connection, only when n LDPC code words are wrong and only one code word is wrong, and the SPC code word is correct, the error can be corrected by the hard decision method, and the probability of the condition is P₁＝nP(1-P)ⁿTherefore, the error code rate P' of the concatenated LDPC code is P-P₁/n＝P-P(1-P)ⁿIf it is to (1-P)ⁿIs unfolded to obtain

When n is far less than 1/P, the error code word rate P' of the LDPC code after the decoding of the cascade code is approximately equal to nP². Because the code error rate and bit error rate of the LDPC code are very small in amplitude along with the change of the normalized signal-to-noise ratio when the error floor occurs, the code error rate P' of the LDPC code after the cascade connection after n is fixed can be considered to be reduced according to the proportion nP compared with the code error rate P before the cascade connection. Since the performance of the hard decision method is not affected by the number of error bits per erroneous codeword, it can be considered approximately product-codedThe bit error rate p is also a bit error rate p for which only LDPC coding is performed, scaled down by the ratio nP. The simulation result can be accurately estimated by using the estimation method, so that a large amount of simulation time is saved.

The hard decision method is a decoding method with extremely low complexity, and can help the LDPC code with an error floor to reduce the error floor. However, when 2 or more than 2 error code words appear in n LDPC code words and 1 SPC code word, the hard decision method cannot correct them, which limits further improvement of LDPC code performance, and the soft decision iterative decoding method given below can correct the error code pattern, thereby improving the error code performance of LDPC code to a greater extent.

As can be seen from the analysis result of the error-floor in the background art, when the LDPC error-floor occurs, and 2 or more error codewords occur in the n LDPC codewords and 1 SPC codeword, most error bits do not occur at the same position, and thus the error pattern shown in fig. 5 occurs with a high probability, that is, in each longitudinal check relationship of the concatenated code, most check equations only include one error bit. Although theoretically, the error bits can be recovered through the rest of the correct bits, the LDPC decoder cannot determine the positions of the correct bits in the error code words, so the present invention provides a soft-decision iterative decoding method. By using the method, each bit in the longitudinal check equation provides the confidence soft information of the bit as external information to the bit in other LDPC code words, and provides the obtained external information to the LDPC code decoder to which the bit belongs so as to help the decoder to smoothly converge to the correct code word.

The soft-decision iterative decoding method of the LDPC-SPC product code comprises the following specific steps:

1. initialization: sequentially decoding each n LDPC code words and 1 SPC code word by the LDPC decoder to obtain the hard decision results of n +1 LDPC code decoding and the confidence information L of each bit_i ^jWherein L is_i ^jShow the ithConfidence information of jth bit of codeword, i from 1 to N +1, j from 1 to N, N being code length of LDPC code,

L_{LDP C_{n + 1}}^{j} = L_{SPC}^{j},

setting the maximum iteration times of soft decision decoding as T;

b) if only one of the n +1 LDPC code words fails to be decoded, two cases can be considered:

if the wrong codeword is one of the first n LDPC codes, then a similar method to hard decision decoding is performed:

first, deleting the erroneous LDPC codeword;

secondly, performing modulo-2 sum on the rest n correct LDPC code words bit by bit in the column direction, wherein the obtained result is the restored correct code word;

thirdly, outputting the recovered correct code word, and ending decoding;

c) if 2 or more than 2 code words in the n +1 LDPC code words have errors, performing longitudinal decoding;

i. if the maximum iteration number T of the soft decision decoding is reached, the decoding is finished.

if the maximum iteration number T of the soft-decision decoding is not reached, go to step 3.

3. Respectively calculating the extrinsic information of each bit of the error code word according to the longitudinal even check relation:

<math> <mrow> <msubsup> <mi>e</mi> <msub> <mi>i</mi> <mi>k</mi> </msub> <mi>j</mi> </msubsup> <mo>=</mo> <mn>2</mn> <mi>ar c</mi> <mi>tanh</mi> <mrow> <mo>(</mo> <munderover> <mi>Π</mi> <mrow> <mi>t</mi> <mo>=</mo> <mn>1</mn> <mo>,</mo> <mi>t</mi> <mo>&NotEqual;</mo> <msub> <mi>i</mi> <mi>k</mi> </msub> </mrow> <mrow> <mi>n</mi> <mo>+</mo> <mn>1</mn> </mrow> </munderover> <mi>tanh</mi> <mrow> <mo>(</mo> <mfrac> <msubsup> <mi>L</mi> <mi>t</mi> <mi>j</mi> </msubsup> <mn>2</mn> </mfrac> <mo>)</mo> </mrow> <mo>)</mo> </mrow> <mo>,</mo> </mrow> </math>

i_krepresenting a k error code word in n +1 code words, k being a positive integer, j representing a j bit in the k error code word;

4. updating confidence of each bit of an erroneous codeword

L_{i_{k}}^{j} = L_{i_{k}}^{j} + e_{i_{k}}^{j},

Wherein i_kRepresenting a k error code word in n +1 code words, k being a positive integer, j representing a j bit in the k error code word;

5. and (4) sequentially sending the error code words with updated confidence degrees to an LDPC code decoder for decoding, and then returning to the step 2.

A flowchart of a soft-decision iterative decoding method of LDPC-SPC product codes is shown in fig. 6.

And step 3 is the core step of the soft-decision iterative decoding method of the LDPC-SPC product code. Wherein, the calculation formula of the extrinsic information of each bit of the error code word is realized through the longitudinal check relation

<math> <mrow> <msubsup> <mi>e</mi> <mi>i</mi> <mi>j</mi> </msubsup> <mo>=</mo> <mn>2</mn> <mi>ar c </mi> <mi>tanh</mi> <mrow> <mo>(</mo> <munderover> <mi>Π</mi> <mrow> <mi>t</mi> <mo>=</mo> <mn>1</mn> <mo>,</mo> <mi>t</mi> <mo>&NotEqual;</mo> <mi>i</mi> </mrow> <mrow> <mi>n</mi> <mo>+</mo> <mn>1</mn> </mrow> </munderover> <mi>tanh</mi> <mrow> <mo>(</mo> <mfrac> <msubsup> <mi>L</mi> <mi>t</mi> <mi>j</mi> </msubsup> <mn>2</mn> </mfrac> <mo>)</mo> </mrow> <mo>)</mo> </mrow> </mrow> </math>

The following were demonstrated:

after n +1 LDPC code words including SPC code words pass through the LDPC code decoder, the confidence coefficient of the jth bit in the ith LDPC code word is set to be L_i ^jLet the confidence soft information of n +1 bits participating in the jth longitudinal check relation be K respectively₁ ^j，L₂ ^j，…，L_n+1 ^jWherein

L_{i}^{j} = \log \frac{p (c_{i}^{j} = 0)}{p (c_{i}^{j} = 1)},

p (c_{i}^{j} = 0)

Represents the probability that the jth bit of the ith LDPC code codeword is equal to 0,

p (c_{i}^{j} = 1)

representing the probability that the bit is equal to 1, 1 ≦ i ≦ n + 1.

Due to the fact that

Let S be 0 to represent the even check relationship, the soft information of the ith bit in the jth check relationship output by decoding is:

{Ls}_{i}^{j} = \log \frac{p (c_{i}^{j} = 0 | S = 0)}{p (c_{i}^{j} = 1 | S = 0)}

wherein,

thus, it is possible to provide

And also

Wherein S' represents a checksum of n bits other than the ith bit, which can be obtained by the above simplification:

will be provided with

c_{i}^{j} = 0

Is mapped as

u_{i}^{j} = 1,

c_{i}^{j} = 1

Is mapped as

u_{i}^{j} = - 1,

Then

<math> <mrow> <mi>p</mi> <mrow> <mo>(</mo> <msup> <mi>S</mi> <mo>′</mo> </msup> <mo>=</mo> <mn>0</mn> <mo>)</mo> </mrow> <mo>=</mo> <mi>p</mi> <mrow> <mo>(</mo> <munderover> <mi>Π</mi> <mfenced open='' close=''> <mtable> <mtr> <mtd> <mi>k</mi> <mo>=</mo> <mn>1</mn> </mtd> </mtr> <mtr> <mtd> <mi>k</mi> <mo>&NotEqual;</mo> <mi>i</mi> </mtd> </mtr> </mtable> </mfenced> <mrow> <mi>n</mi> <mo>+</mo> <mn>1</mn> </mrow> </munderover> <msubsup> <mi>u</mi> <mi>k</mi> <mi>j</mi> </msubsup> <mo>=</mo> <mn>1</mn> <mo>)</mo> </mrow> <mo>,</mo> </mrow> </math>

<math> <mrow> <mi>p</mi> <mrow> <mo>(</mo> <msup> <mi>S</mi> <mo>′</mo> </msup> <mo>=</mo> <mn>1</mn> <mo>)</mo> </mrow> <mo>=</mo> <mi>p</mi> <mrow> <mo>(</mo> <munderover> <mi>Π</mi> <mfenced open='' close=''> <mtable> <mtr> <mtd> <mi>k</mi> <mo>=</mo> <mn>1</mn> </mtd> </mtr> <mtr> <mtd> <mi>k</mi> <mo>&NotEqual;</mo> <mi>i</mi> </mtd> </mtr> </mtable> </mfenced> <mrow> <mi>n</mi> <mo>+</mo> <mn>1</mn> </mrow> </munderover> <msubsup> <mi>u</mi> <mi>k</mi> <mi>j</mi> </msubsup> <mo>=</mo> <mo>-</mo> <mn>1</mn> <mo>)</mo> </mrow> </mrow> </math>

Since all bits come from different LDPC codes, and the bits are relatively independent, there are:

<math> <mrow> <mi>p</mi> <mrow> <mo>(</mo> <munderover> <mi>Π</mi> <mfenced open='' close=''> <mtable> <mtr> <mtd> <mi>k</mi> <mo>=</mo> <mn>1</mn> </mtd> </mtr> <mtr> <mtd> <mi>k</mi> <mo>&NotEqual;</mo> <mi>i</mi> </mtd> </mtr> </mtable> </mfenced> <mrow> <mi>n</mi> <mo>+</mo> <mn>1</mn> </mrow> </munderover> <msubsup> <mi>u</mi> <mi>k</mi> <mi>j</mi> </msubsup> <mo>=</mo> <mn>1</mn> <mo>)</mo> </mrow> <mo>=</mo> <mn>1</mn> <mo>+</mo> <munderover> <mi>Π</mi> <mfenced open='' close=''> <mtable> <mtr> <mtd> <mi>k</mi> <mo>=</mo> <mn>1</mn> </mtd> </mtr> <mtr> <mtd> <mi>k</mi> <mo>&NotEqual;</mo> <mi>i</mi> </mtd> </mtr> </mtable> </mfenced> <mrow> <mi>n</mi> <mo>+</mo> <mn>1</mn> </mrow> </munderover> <mrow> <mo>(</mo> <mi>p</mi> <mrow> <mo>(</mo> <msubsup> <mi>u</mi> <mi>k</mi> <mi>j</mi> </msubsup> <mo>=</mo> <mn>1</mn> <mo>)</mo> </mrow> <mo>-</mo> <mi>p</mi> <mrow> <mo>(</mo> <msubsup> <mi>u</mi> <mi>k</mi> <mi>j</mi> </msubsup> <mo>=</mo> <mo>-</mo> <mn>1</mn> <mo>)</mo> </mrow> <mo>)</mo> </mrow> </mrow> </math>

<math> <mrow> <mi>p</mi> <mrow> <mo>(</mo> <munderover> <mi>Π</mi> <mfenced open='' close=''> <mtable> <mtr> <mtd> <mi>k</mi> <mo>=</mo> <mn>1</mn> </mtd> </mtr> <mtr> <mtd> <mi>k</mi> <mo>&NotEqual;</mo> <mi>i</mi> </mtd> </mtr> </mtable> </mfenced> <mrow> <mi>n</mi> <mo>+</mo> <mn>1</mn> </mrow> </munderover> <msubsup> <mi>u</mi> <mi>k</mi> <mi>j</mi> </msubsup> <mo>=</mo> <mo>-</mo> <mn>1</mn> <mo>)</mo> </mrow> <mo>=</mo> <mn>1</mn> <mo>-</mo> <munderover> <mi>Π</mi> <mfenced open='' close=''> <mtable> <mtr> <mtd> <mi>k</mi> <mo>=</mo> <mn>1</mn> </mtd> </mtr> <mtr> <mtd> <mi>k</mi> <mo>&NotEqual;</mo> <mi>i</mi> </mtd> </mtr> </mtable> </mfenced> <mrow> <mi>n</mi> <mo>+</mo> <mn>1</mn> </mrow> </munderover> <mrow> <mo>(</mo> <mi>p</mi> <mrow> <mo>(</mo> <msubsup> <mi>u</mi> <mi>k</mi> <mi>j</mi> </msubsup> <mo>=</mo> <mn>1</mn> <mo>)</mo> </mrow> <mo>-</mo> <mi>p</mi> <mrow> <mo>(</mo> <msubsup> <mi>u</mi> <mi>k</mi> <mi>j</mi> </msubsup> <mo>=</mo> <mo>-</mo> <mn>1</mn> <mo>)</mo> </mrow> <mo>)</mo> </mrow> </mrow> </math>

then

<math> <mrow> <msubsup> <mi>Ls</mi> <mi>i</mi> <mi>j</mi> </msubsup> <mo>=</mo> <mi>log</mi> <mfrac> <mrow> <mi>p</mi> <mrow> <mo>(</mo> <msup> <mi>S</mi> <mo>′</mo> </msup> <mo>=</mo> <mn>0</mn> <mo>)</mo> </mrow> </mrow> <mrow> <mi>p</mi> <mrow> <mo>(</mo> <msup> <mi>S</mi> <mo>′</mo> </msup> <mo>=</mo> <mn>1</mn> <mo>)</mo> </mrow> </mrow> </mfrac> <mo>+</mo> <msubsup> <mi>L</mi> <mi>i</mi> <mi>j</mi> </msubsup> <mo>=</mo> <mi>log</mi> <mfrac> <mrow> <mn>1</mn> <mo>+</mo> <munderover> <mi>Π</mi> <mfenced open='' close=''> <mtable> <mtr> <mtd> <mi>k</mi> <mo>=</mo> <mn>1</mn> </mtd> </mtr> <mtr> <mtd> <mi>k</mi> <mo>&NotEqual;</mo> <mi>i</mi> </mtd> </mtr> </mtable> </mfenced> <mrow> <mi>n</mi> <mo>+</mo> <mn>1</mn> </mrow> </munderover> <mrow> <mo>(</mo> <mi>p</mi> <mrow> <mo>(</mo> <msubsup> <mi>u</mi> <mi>k</mi> <mi>j</mi> </msubsup> <mo>=</mo> <mn>1</mn> <mo>)</mo> </mrow> <mo>-</mo> <mi>p</mi> <mrow> <mo>(</mo> <msubsup> <mi>u</mi> <mi>k</mi> <mi>j</mi> </msubsup> <mo>=</mo> <mo>-</mo> <mn>1</mn> <mo>)</mo> </mrow> <mo>)</mo> </mrow> </mrow> <mrow> <mn>1</mn> <mo>-</mo> <munderover> <mi>Π</mi> <mfenced open='' close=''> <mtable> <mtr> <mtd> <mi>k</mi> <mo>=</mo> <mn>1</mn> </mtd> </mtr> <mtr> <mtd> <mi>k</mi> <mo>&NotEqual;</mo> <mi>i</mi> </mtd> </mtr> </mtable> </mfenced> <mrow> <mi>n</mi> <mo>+</mo> <mn>1</mn> </mrow> </munderover> <mrow> <mo>(</mo> <mi>p</mi> <mrow> <mo>(</mo> <msubsup> <mi>u</mi> <mi>k</mi> <mi>j</mi> </msubsup> <mo>=</mo> <mn>1</mn> <mo>)</mo> </mrow> <mo>-</mo> <mi>p</mi> <mrow> <mo>(</mo> <msubsup> <mi>u</mi> <mi>k</mi> <mi>j</mi> </msubsup> <mo>=</mo> <mo>-</mo> <mn>1</mn> <mo>)</mo> </mrow> <mo>)</mo> </mrow> </mrow> </mfrac> <mo>+</mo> <msubsup> <mi>L</mi> <mi>i</mi> <mi>j</mi> </msubsup> </mrow> </math>

So that there are

<math> <mrow> <msubsup> <mi>Ls</mi> <mi>i</mi> <mi>j</mi> </msubsup> <mo>=</mo> <mn>2</mn> <mi>ar c </mi> <mi>tanh</mi> <mrow> <mo>(</mo> <munderover> <mi>Π</mi> <mrow> <mi>t</mi> <mo>=</mo> <mn>1</mn> <mo>,</mo> <mi>t</mi> <mo>&NotEqual;</mo> <mi>i</mi> </mrow> <mrow> <mi>n</mi> <mo>+</mo> <mn>1</mn> </mrow> </munderover> <mi>tanh</mi> <mrow> <mo>(</mo> <mfrac> <msubsup> <mi>L</mi> <mi>t</mi> <mi>j</mi> </msubsup> <mn>2</mn> </mfrac> <mo>)</mo> </mrow> <mo>)</mo> </mrow> <mo>+</mo> <msubsup> <mi>L</mi> <mi>i</mi> <mi>j</mi> </msubsup> <mo>,</mo> </mrow> </math>

That is, for each bit, the longitudinal check relationship of the SPC code gives extrinsic information of

<math> <mrow> <mn>2</mn> <mi></mi> <mi>ar c</mi> <mi>tanh</mi> <mrow> <mo>(</mo> <munderover> <mi>Π</mi> <mrow> <mi>t</mi> <mo>=</mo> <mn>1</mn> <mo>,</mo> <mi>t</mi> <mo>&NotEqual;</mo> <mi>i</mi> </mrow> <mrow> <mi>n</mi> <mo>+</mo> <mn>1</mn> </mrow> </munderover> <mi>tanh</mi> <mrow> <mo>(</mo> <mfrac> <msubsup> <mi>L</mi> <mi>t</mi> <mi>j</mi> </msubsup> <mn>2</mn> </mfrac> <mo>)</mo> </mrow> <mo>)</mo> </mrow> <mo>,</mo> </mrow> </math>

The formula proves.

The invention also provides an improved method of the soft-decision iterative decoding method. The main purpose of the iterative decoding method is to make each bit continuously obtain confidence soft information from the outside by iteration, which can help the bit to make a decision. In the soft-decision iteration method given above, the bits of each LDPC code word pass through the longitudinal SPC check relationship, and new extrinsic information is obtained from the remaining LDPC code words, thereby helping the LDPC code decoder to converge to a correct code word. Since not all of the n +1 LDPC code codewords fail to be decoded. By the error detection capability of the LDPC code, it can be ascertained which of the n +1 codewords successfully converge to the correct codeword. With this ascertained information, the soft-decision iterative decoding method can be improved.

The main idea of the improved decoding method is to utilize the error detection capability of the LDPC decoder to improve the confidence coefficient of each bit of the LDPC code word judged to be successfully decoded to the maximum so as to improve the confidence coefficient which can be obtained by each bit of the error code word and accelerate the convergence of iterative decoding. That is, if the ith codeword conforms to the check equation constraint, let the confidence L of the jth bit in the ith LDPC codeword_i ^jIs of a size of

Symbol is

sgn (L_{i}^{j}) = sgn (L_{i}^{j}),

Wherein j is 1, 2, …, N is the code length of the LDPC code;

it can be easily found that the LDPC-SPC soft decision iterative method is equivalent to the sum-product algorithm decoding performed alternately in the horizontal and vertical directions. Therefore, similar to the sum-product algorithm, the formula for calculating the extrinsic information of the check relation in the longitudinal direction

<math> <mrow> <mn>2</mn> <mi>arctanh</mi> <mrow> <mo>(</mo> <munderover> <mi>Π</mi> <mrow> <mi>t</mi> <mo>=</mo> <mn>1</mn> <mo>,</mo> <mi>t</mi> <mo>&NotEqual;</mo> <mi>i</mi> </mrow> <mrow> <mi>n</mi> <mo>+</mo> <mn>1</mn> </mrow> </munderover> <mi>tanh</mi> <mrow> <mo>(</mo> <mfrac> <msubsup> <mi>L</mi> <mi>t</mi> <mi>j</mi> </msubsup> <mn>2</mn> </mfrac> <mo>)</mo> </mrow> <mo>)</mo> </mrow> </mrow> </math>

A similar simplification as the sum-product algorithm can be made. The invention adopts an offset-min-sum algorithm (Chen Jinghu; R.M.tanner; C.Jones, "Improved min-sum decoding algorithms for linear LDPC codes," InProc.ISIT' 05. Massachusetts: MITPress, pp.449-453, 2005) with better performance as a simplification method of a longitudinal method, wherein the offset value is selected to be 0.2 according to a large number of simulation results and combined with experience, and then the external information of the longitudinal check relationship is obtainedIs of a size of

<math> <mrow> <mo>|</mo> <msubsup> <mi>e</mi> <msub> <mi>i</mi> <mi>k</mi> </msub> <mi>j</mi> </msubsup> <mo>|</mo> <mo>=</mo> <mi>max</mi> <mrow> <mo>(</mo> <munderover> <mi>min</mi> <mfenced open='' close=''> <mtable> <mtr> <mtd> <mi>t</mi> <mo>=</mo> <mn>1</mn> </mtd> </mtr> <mtr> <mtd> <mi>t</mi> <mo>&NotEqual;</mo> <mi>i</mi> </mtd> </mtr> </mtable> </mfenced> <mrow> <mi>n</mi> <mo>+</mo> <mn>1</mn> </mrow> </munderover> <mrow> <mo>(</mo> <mo>|</mo> <msubsup> <mi>L</mi> <mi>t</mi> <mi>j</mi> </msubsup> <mo>|</mo> <mo>)</mo> </mrow> <mo>-</mo> <mn>0.2,0</mn> <mo>)</mo> </mrow> <mo>,</mo> </mrow> </math>

Symbol is

<math> <mrow> <mi>sgn</mi> <mo>=</mo> <mrow> <mo>(</mo> <msubsup> <mi>e</mi> <msub> <mi>i</mi> <mi>k</mi> </msub> <mi>j</mi> </msubsup> <mo>)</mo> </mrow> <mo>=</mo> <munderover> <mi>Π</mi> <mrow> <mi>t</mi> <mo>=</mo> <mn>1</mn> <mo>,</mo> <mi>t</mi> <mo>&NotEqual;</mo> <mi>i</mi> </mrow> <mrow> <mi>n</mi> <mo>+</mo> <mn>1</mn> </mrow> </munderover> <mi>sgn</mi> <mrow> <mo>(</mo> <msubsup> <mi>L</mi> <mi>t</mi> <mi>j</mi> </msubsup> <mo>)</mo> </mrow> <mo>,</mo> </mrow> </math>

Where j is 1, 2, …, N, N is the code length of the LDPC code, i_kRepresents the k-th error codeword, L, of the n +1 codewords_i ^jIs the confidence of the jth bit in the ith LDPC code word;

because the absolute value of the bit confidence of each correct code word is set to be infinite, when longitudinal soft information is calculated, only the absolute value of the bit confidence of the corresponding position in an error code word needs to be compared, and the correct code word only participates in the symbol operation of the confidence soft information of the bit at the corresponding position. Compared with the soft-decision iterative decoding method, the complexity of the improved soft-decision iterative decoding method is greatly reduced. The improved soft-decision iterative decoding method is different from the soft-decision iterative decoding method which is only the third step, and other steps are the same, wherein the specific processing method in the step 3 is as follows:

1) the confidence L of the jth bit in the ith LDPC codeword if the ith codeword complies with the LDPC code check equation constraints_i ^jIs of a size of

Symbol is

sgn (L_{i}^{j}) = sgn (L_{i}^{j}),

Wherein j is 1, 2, …, N is the code length of the LDPC code;

2) respectively calculating extrinsic information of each bit of the error codeword according to the longitudinal check relationship

It has a size of

Symbol is

<math> <mrow> <mi>sgn</mi> <mrow> <mo>(</mo> <msubsup> <mi>e</mi> <msub> <mi>i</mi> <mi>k</mi> </msub> <mi>j</mi> </msubsup> <mo>)</mo> </mrow> <mo>=</mo> <munderover> <mi>Π</mi> <mrow> <mi>t</mi> <mo>=</mo> <mn>1</mn> <mo>,</mo> <mi>t</mi> <mo>&NotEqual;</mo> <mi>i</mi> </mrow> <mrow> <mi>n</mi> <mo>+</mo> <mn>1</mn> </mrow> </munderover> <mi>sgn</mi> <mrow> <mo>(</mo> <msubsup> <mi>L</mi> <mi>t</mi> <mi>j</mi> </msubsup> <mo>)</mo> </mrow> <mo>,</mo> </mrow> </math>

Where j is 1, 2, …, N, N is the code length of the LDPC code, i_kRepresents the k-th error codeword, L, of the n +1 codewords_i ^jIs the confidence of the jth bit in the ith LDPC codeword.

It is another object of the present invention to provide a decoder for LDPC-SPC product codes that is compatible with the above method. According to the coding structure of the LDPC-SPC product code and combining the method, the invention provides a hard decision decoder and a soft decision iterative decoder which are respectively suitable for the hard decision decoding method and the soft decision iterative decoding method of the LDPC-SPC product code, and the following are respectively introduced:

a schematic diagram of a hard decision decoder is shown in fig. 7. The hard decision decoder includes: the LDPC code decoding module, the first storage module, the error code word statistic module and the hard decision recovery module. The LDPC code decoding module is used for decoding LDPC code words and outputting hard decision information of LDPC code information bits, namely decoding every n +1 LDPC code words in sequence, wherein the n +1 th LDPC code word is an SPC code word and outputting the hard decision information of the n +1 LDPC code information bits; the first storage module is used for storing the hard decision information of the LDPC code information bit, generally uses a dual-port RAM, and the size can be determined according to the actual requirement; the error code word counting module counts error code words in n +1 LDPC codes according to hard decision information, generally comprises a counter, the initial value is 0, and the flow direction of the information bits of the LDPC code words is determined by the counter, the specific flow direction is as shown in FIG. 7, if only one code word in the n +1 LDPC code words fails to be decoded and the code word is not an SPC code, the error code word enters a hard decision recovery module, otherwise, the information bits are output, and the decoding is finished; and deleting the wrong LDPC code words by the hard decision recovery module, performing modulo 2 sum on the rest n correct LDPC code words bit by bit in the column direction to recover the correct code words, outputting the recovered correct information bits, and finishing decoding.

The hard decision recovery block structure can be as shown in fig. 8, which is mainly divided into two parts, a modulo-2 adder block and a second storage block. The modulo-2 adder realizes the modulo-2 sum of two binary numbers without sign bits, is used for calculating the modulo-2 sum of the information bits of n LDPC code words except the error code word according to the longitudinal direction of the bits, and simultaneously outputs the n correct information bits; the second storage module is a dual-port RAM, the size of the dual-port RAM is the size of the LDPC code word information bits, and the second storage module is used for storing a temporary result of the modulo-2 adder, namely, performing modulo-2 addition with the next frame, and outputting a final accumulation result, namely, the recovered correct information bits.

A schematic diagram of a soft-decision iterative decoder is shown in fig. 9. The soft-decision iterative decoder includes: the device comprises an LDPC code decoding module, a first storage module, an error code word counting module, an SPC code soft decoding module and a hard decision recovery module. The LDPC code decoding module is used for decoding LDPC code words and outputting soft information and hard decision information of LDPC code information bits, namely for each bitSequentially decoding n +1 LDPC code words, wherein the n +1 th LDPC code word is an SPC code word, outputting soft information and hard decision information of n +1 LDPC code information bits, wherein the soft information is confidence L of each bit_i ^jWhere i is from 1 to N +1, j is from 1 to N, and N is the code length of the LDPC code. The first storage module is used for storing soft information and hard decision information of LDPC code information bits, generally uses a dual-port RAM, and the size can be determined according to actual needs. The error code word statistical module is used for counting error code words in n +1 LDPC codes, generally comprising a counter, the initial value is 0, and the flow direction of the LDPC code word information bits is determined by the counter, the specific flow direction is as shown in FIG. 9, if only one code word in the n +1 LDPC code words fails to be decoded and the code word is not an SPC code, the error code word statistical module enters a hard decision recovery module; if more than one code word in the n +1 LDPC code words fails to be decoded, entering an SPC code soft decoding module; if there is no codeword error or only the SPC code decoding fails, the correct information bits are output. SPC code soft decoding module for calculating the extrinsic information of error code word, using the above soft-decision iterative decoding method or its improved method to decode, retaining the soft information of error code word in n +1 LDPC codes, retaining the hard decision information, namely sign bit, of correct code word, then calculating the extrinsic information of each bit of error code word respectively

<math> <mrow> <msubsup> <mi>e</mi> <msub> <mi>i</mi> <mi>k</mi> </msub> <mi>j</mi> </msubsup> <mo>=</mo> <mn>2</mn> <mi>arctanh</mi> <mrow> <mo>(</mo> <munderover> <mi>Π</mi> <mrow> <mi>t</mi> <mo>=</mo> <mn>1</mn> <mo>,</mo> <mi>t</mi> <mo>&NotEqual;</mo> <msub> <mi>i</mi> <mi>k</mi> </msub> </mrow> <mrow> <mi>n</mi> <mo>+</mo> <mn>1</mn> </mrow> </munderover> <mi>tanh</mi> <mrow> <mo>(</mo> <mfrac> <msubsup> <mi>L</mi> <mi>t</mi> <mi>j</mi> </msubsup> <mn>2</mn> </mfrac> <mo>)</mo> </mrow> <mo>)</mo> </mrow> <mo>,</mo> </mrow> </math>

Wherein i_kRepresenting the k error code word in the n +1 code words, k is a positive integer, j represents the j bit in the k error code word, and the obtained external information is used as the prior information of the LDPC code decoding module to decode again, namely, the confidence coefficient of each bit of the error code word is updated

L_{i_{k}}^{j} = L_{i_{k}}^{j} + e_{i_{k}}^{j},

And then inputting the code into an LDPC code decoding module for iterative decoding until the maximum iteration times are reached or all code words are detected correctly. And the hard decision recovery module is used for recovering the error code word by using a method similar to hard decision decoding when one code word in the n LDPC codes has errors and the error code word is not an SPC code, namely deleting the error LDPC code word, performing modulo 2 sum on the rest n correct LDPC code words bit by bit in the column direction, obtaining the result as the recovered correct code word, and outputting the recovered correct information bits. The specific work flow of the decoder is as follows:

the receiving end firstly decodes n +1 LDPC codes in sequence, if no codeword error is found, all bits are output in sequence; if errors occur in only one code word, the n +1 LDPC codes are stored, and the error code words are recovered through hard decision; if 2 or more than 2 code words are found to be wrong, the wrong code words in the n +1 LDPC codes reserve soft information output by the LDPC code decoding module, the correct code words only reserve hard decision information, namely sign bits, and are decoded by the SPC code soft decoding module, and the obtained external information is used as the prior information of the LDPC code decoding module to be decoded again until the maximum iteration number is reached or all code words are detected correctly.

The hard decision recovery module in the soft decision iterative decoder is mainly composed of a modulo-2 adder module and a second storage module, wherein the modulo-2 adder module is used for calculating the modulo-2 sum of the information bits of n LDPC code words except the error code word according to the longitudinal direction of the bits and outputting the n correct information bits at the same time; the second storage module is used for storing a temporary result of the modulo-2 adder, namely, performing modulo-2 sum addition with the next frame, and outputting a final accumulation result, namely, the recovered correct information bit.

The technical effects of the invention are as follows:

firstly, an LDPC-SPC product code design scheme is provided, which can overcome the error floor of LDPC codes and has higher flexibility and larger coding gain than the BCH code concatenation method, mainly because BCH codes need to provide different code lengths and different error correction capabilities for LDPC codes of different code rates, difficulty in designing the concatenation code scheme and complexity of a coding and decoding system are increased, and LDPC-SPC product codes do not need to consider this problem; meanwhile, the coding redundancy of the BCH code needs to be paid is large, and the coding redundancy of the LDPC-SPC product code is equivalent to that only after the loss of the normalized signal-to-noise ratio

101 g (\frac{n}{n + 1}) dB,

When n takes a large value, the coding redundancy is negligible.

Secondly, a hard decision decoding method of the LDPC-SPC cascade code is provided, which is a decoding method with extremely low complexity and can help the LDPC code with an error floor to reduce the error floor.

Thirdly, the hard decision method of the LDPC-SPC concatenated code is analyzed, the bit error rate estimation method of the hard decision method is provided, the comparison between the estimation result and the simulation result is shown in FIG. 10, and it can be seen from the figure that the estimation can accurately accord with the simulation result, thereby saving a large amount of simulation time.

Fourthly, a soft-decision iterative decoding method of the LDPC-SPC concatenated code is provided and simplified, and the simulation result is shown in FIG. 13, and it can be seen from FIG. 13 that under the soft-decision decoding method, compared with the hard decision, the LDPC-SPC concatenated code can obtain more obvious coding gain, and more effectively reduce the error floor of the LDPC code.

Therefore, the LDPC-SPC product code provided by the invention can obtain larger coding gain with very small redundancy cost, and is a channel coding scheme suitable for delay-insensitive services.

Drawings

FIG. 1 is a graph of error performance of an (8064, 4032) LDPC code;

FIG. 2 is a diagram of the distribution of the number of error bits of 200 error code words counted by the error-leveling layer of the LDPC code (8064, 4032) under the normalized SNR of 1.5dB (I) and 1.6dB (II), respectively;

FIG. 3 is a statistical plot of the error bit positions of the (8064, 4032) LDPC code at normalized SNR of 1.5dB and 1.6dB, respectively;

FIG. 4 is a codeword pattern of the LDPC-SPC product code of the present invention;

FIG. 5 is a diagram illustrating the relationship between the positions of the error bits of the LDPC-SPC product code of the present invention;

FIG. 6 is a flow chart of a soft-decision iterative decoding method of the LDPC-SPC product code of the present invention;

fig. 7 is a schematic diagram of a hard decision decoder according to the present invention;

fig. 8 is a block diagram of a hard decision recovery module in a hard decision decoder according to embodiment 2 of the present invention;

fig. 9 is a schematic diagram of the structure of a soft-decision iterative decoder of the present invention;

fig. 10 is a diagram comparing the error rate and the estimation result of the LDPC-SPC code hard decision decoding method when n is 100;

FIG. 11 is a flow chart of LDPC-SPC product code encoding in embodiment 1 of the present invention;

fig. 12 is a simulation result diagram of bit error performance of the LDPC-SPC code hard decision decoding method when n is 200 in embodiment 1 of the present invention;

fig. 13 is a diagram of a simulation result comparing error rate performance of the LDPC-SPC code soft decision iterative decoding method and the LDPC-BCH code when n is 200 in embodiment 1 of the present invention.

Detailed Description

The invention is further illustrated by the following examples, without in any way limiting the scope of the invention, with reference to the accompanying drawings. Example 1: constructing and decoding LDPC-SPC product codes

The following detailed description describes a process of constructing and decoding an LDPC-SPC product code by using an LDPC code with a length of 8064 bits and a code rate of 1/2, where the decoding method includes a hard-decision decoding method and a soft-decision iterative decoding method:

this embodiment takes n 200, i.e. one redundant SPC codeword is inserted every 200 LDPC codes.

The encoding flow chart is shown in fig. 11, and the specific steps are as follows:

1. initialization: the information bit stream is framed, and the frame length is 4032 bits;

2. 200 information frames are sequentially passed through an SPC code encoder, each information frame is positioned at a corresponding position by the SPC code encoder

Modulo 2 and outputs the result, i.e. the information bits in the SPC code, after n-200 information frames,

wherein j ranges from 1 to 4032;

3. sequentially passing 200 information frames and 1 SPC information frame through an LDPC code encoder to obtain n + 1-201 LDPC code words, wherein the n + 1-th LDPC code word is a redundant SPC code word;

4. and outputting the coded code words in sequence.

Decoding is carried out at a receiving end, if the receiving end adopts hard decision decoding, the method comprises the following steps:

1. initialization: 200 LDPC code words and 1 SPC code word are decoded sequentially by the LDPC code decoding module, namely the ith LDPC code word is decoded

And entering an LDPC code decoding module for decoding, wherein i is from 1 to 201,

C_{{LDPC}_{201}} = C_{SPC},

obtaining hard decision results of decoding 201 LDPC codes;

2. according to the characteristic that the LDPC code decoding module can detect errors, various error patterns in 201 LDPC codes can be counted, and the specific processing steps are as follows:

a) if no code word decoding fails in the 201 LDPC code words, the decoding is finished;

b) if the decoding of more than 1 code word in the 201 LDPC code words fails, the decoding is finished;

c) if only one of the 201 LDPC code words fails to be decoded, two cases can be considered:

if the erroneous codeword is an LDPC code, proceed to step 3.

3-1 deleting the LDPC code words in error;

3-2, performing modulo-2 sum on the rest 200 correct LDPC code words bit by bit in the column direction, wherein the obtained result is the recovered correct code word;

3-3 outputs the recovered correct codeword.

If the receiving end uses soft-decision iterative decoding, the flowchart is shown in fig. 8, and in this embodiment, the improved soft-decision iterative decoding method described in the summary of the invention is used, and the maximum soft-decision iterative decoding time T is taken as 5, and the specific steps are as follows:

1. initialization: decoding 200 LDPC code words and 1 SPC code word sequentially through an LDPC code decoding module to obtain the confidence information L of the jth bit of the ith code word_i ^jWherein the number of bits in i from 1 to 201,

L_{{LDPC}_{201}}^{j} = L_{SPC}^{j};

2. according to the characteristic that the LDPC code decoding module can detect errors, counting error code words:

a) if no code word decoding fails in the 201 LDPC code words, decoding is finished, and a correct LDPC code is output;

b) if only one of the 201 LDPC code words fails to be decoded, two cases can be considered:

i. if the wrong code word is the SPC code, the SPC code can be directly deleted as the SPC code is the redundancy check code word, the first 200 correct LDPC codes are output, and the decoding is finished;

if the wrong codeword is an LDPC code, then a similar method as hard decision decoding is performed:

first, deleting the erroneous LDPC codeword;

secondly, performing modulo-2 sum on the rest 200 correct LDPC code words bit by bit in the column direction, wherein the obtained result is the recovered correct code word;

thirdly, outputting the recovered correct code word, and ending decoding;

c) if 2 or more than 2 code words in the 201 LDPC code words have errors, performing longitudinal decoding;

i. if the maximum iteration times of the soft decision decoding are reached, namely T is greater than T and is equal to 5, the decoding is finished;

if the maximum iteration number of soft decision decoding is not reached, namely T is less than or equal to T and is equal to 5, turning to the step 3;

3. longitudinal decoding: if the ith code word accords with the constraint of the check equation, the confidence L of each bit of the ith LDPC code word is made_i ^jIs of a size of

Symbol is

sgn (L_{i}^{j}) = sgn (L_{i}^{j}),

Where j is 1, 2, …, 4032.

4. Respectively calculating extrinsic information of each bit of the error code word according to the longitudinal check relation

It has a size of

Symbol is

Wherein j is 1, 2, …, 4032, i_kIndicating the k-th erroneous codeword, L, out of 201 codewords_i ^jIs the confidence of the jth bit in the ith LDPC code word;

5. updating bit confidence of error code word

L_{i_{k}}^{j} = L_{i_{k}}^{j} + e_{i_{k}}^{j},

Wherein j is 1, 2, …, 4032, i_kRepresenting 201 code words

The kth error codeword in (1), k being a positive integer;

6. and (4) sequentially sending the error code words after the confidence coefficient is updated to an LDPC code decoder for decoding, and then returning to the step 2.

In this embodiment, the LDPC-SPC product code with the above structure is subjected to error performance simulation of the LDPC-SPC concatenated code under the BIAWGN channel, wherein In order to increase the simulation speed, the decoding method of the LDPC code adopts an offset-min-sum algorithm (Chen jinhu; r.m.tanner; c.jones, "Improved min-sum decoding algorithms for irregular LDPC codes," In proc.isit' 05. Massachusetts: MIT Press, pp.449-453, 2005) suitable for hardware implementation, wherein the offset value is selected to be 0.2, and the maximum number of iterations is selected to be 37 times to adapt to actual parameters of the LDPC code decoder. When the number of erroneous LDPC code words exceeds 50, the simulation stops.

GF (2) with error correction capability t of 10 is also selected in the present embodiment¹²) The BCH codes perform comparative simulation of the error rate characteristic. GF (2)¹²) The minimum polynomial of (c) is as follows. If the error correction capability of the BCH code is t, the generator polynomial of the BCH code is equal to the product of the first t minimum polynomials. For example, when t is 2, the generator polynomial of the BCH code is g (x), g1(x), g2 (x). The error correction capability t is 10, which is based on the analysis of the characteristics of the error-leveling layer of the LDPC code, and most of the error bits in the LDPC error code word are below 10 bits when the error-leveling layer occurs, and the error bits exceeding 10 bits are generally not more than 10%.

Least polynomial

g₁(x)＝1+x+x⁴+x⁶+x¹²

g₂(x)＝1+x+x³+x⁴+x⁶+x¹⁰+x¹²

g₃(x)＝1+x²+x³+x⁶+x¹²

g₄(x)＝1+x+x³+x⁵+x⁶+x¹⁰+x¹²

g₅(x)＝1+x²+x⁴+x⁵+x⁶+x⁷+x⁸+x⁹+x¹²

g₆(x)＝1+x+x²+x⁵+x⁷+x⁸+x⁹+x¹¹+x¹²

g₇(x)＝1+x+x³+x⁶+x⁸+x¹⁰+x¹²

g₈(x)＝1+x+x²+x³+x⁴+x⁵+x⁹+x¹⁰+x¹²

g₉(x)＝1+x+x³+x⁴+x⁶+x⁸+x¹⁰+x¹¹+x¹²

g₁₀(x)＝1+x+x²+x⁵+x¹⁰+x¹¹+x¹²

The simulation result obtained by the hard decision decoding method is shown in fig. 12, and it can be seen from the figure that the error floor of the LDPC-SPC product code constructed in the present embodiment can be reduced by the hard decision decoding method.

The simulation result obtained by using the soft-decision iterative decoding method is shown in fig. 13, and it can be seen from the curve of fig. 13 that the LDPC-SPC product code constructed in this embodiment can obtain a very significant coding gain in addition to overcoming the error floor of the LDPC code by using the soft-decision iterative method. At a bit error rate of 10-7, the product code achieves a performance advantage of about 0.3dB over LDPC codes and over 0.4dB over LDPC-BCH concatenated codes.

Example 2: decoder

This embodiment only gives an implementation of the hard decision decoder of the LDPC-SPC product code constructed in embodiment 1. The implementation block diagram of the hard decision decoder is shown in fig. 7, and it can be divided into four parts, i.e., an LDPC decoding module, a first storage module, an error codeword counting module, and a hard decision recovery module.

The LDPC code decoding module is used for decoding the LDPC codeword, which is not described in detail in this embodiment, but is used for obtaining soft information and hard decision information of the LDPC code information bit, and in this embodiment, the hard decision decoding method only needs the hard decision information of the LDPC code information bit; the first storage module needs 201 dual-port RAMs with 4032bits for storing the hard decision information of the LDPC code information bits; the error code word statistic module consists of a counter, the initial value is 0, the maximum value is 201, and the flow direction of the LDPC code word information bits is determined by the counter:

1. if no code word decoding fails in the 201 LDPC code words, the decoding is finished, and correct information bits are output;

2. if the decoding of 2 or more than 2 code words in the 201 LDPC code words fails, the decoding is finished;

3. if only one of the 201 LDPC code words fails to be decoded, two cases can be considered:

if the erroneous codeword is an LDPC code, then a hard decision recovery module is entered.

Fig. 8 shows a block diagram of a hard decision recovery module, which is mainly divided into a modulo-2 adder module and a second storage module. The modulo-2 adder needs to be 4032bits bitwise modulo-2 and is used for calculating the modulo-2 sum of the bitwise longitudinal direction of 200 information bits except the error code word and simultaneously outputting the 200 correct information bits; the second storage module needs a dual-port RAM with a size of 4032bits for storing a temporary result of the modulo-2 adder, i.e. an addition modulo-2 and the next frame, and outputs a final accumulation result, i.e. the recovered correct information bits, after n is 200.

Although specific embodiments of the invention have been disclosed for illustrative purposes and the accompanying drawings, which are included to provide a further understanding of the invention and are incorporated by reference, those skilled in the art will appreciate that: various substitutions, changes and modifications are possible without departing from the spirit and scope of the present invention and the appended claims. Therefore, the present invention should not be limited to the disclosure of the preferred embodiments and the accompanying drawings.

Claims

1. An encoding method of an LDPC concatenated code, comprising the steps of:

1) framing the information bit stream;

2) making the bits of each n information frames at corresponding positions into modulo 2 sum, wherein n is a positive integer, to obtain the (n +1) th redundant frame

Wherein N is the length of the information frame and is a positive integer;

3) sequentially coding the n +1 information frames by using the LDPC code to obtain n +1 LDPC code words, wherein the n +1 LDPC code word is a redundant code word, the redundant code word is named as an SPC code, and the obtained LDPC cascade code is an LDPC-SPC product code, and the method comprises the following steps:

wherein c is_SPC ^jFor the jth bit of the SPC codeword,

respectively the jth of the first n LDPC code wordsA bit.

2. The encoding method according to claim 1, wherein: the value of n is 50 to 400.

3. A decoding method of LDPC-SPC product code as claimed in claim 1, comprising the steps of:

1) sequentially performing LDPC decoding on every n +1 LDPC code words, wherein the n +1 th LDPC code word is an SPC code word, and obtaining hard decision results of the n +1 LDPC code decoding;

2) counting error patterns in n +1 LDPC codes, and processing according to the following conditions a) to c):

c) if only one of the n +1 LDPC code words fails to be decoded, two cases are divided:

i. if the wrong code word is the SPC code, directly deleting the code word, outputting the first n correct LDPC codes, and ending the decoding;

if the wrong codeword is one of the first n LDPC codes, proceed to step 3);

3) deleting the wrong LDPC code words, performing modulo-2 sum on the rest n correct LDPC code words bit by bit in the column direction, outputting the restored correct code words and finishing decoding.

4. A decoding method of LDPC-SPC product code as claimed in claim 1, comprising the steps of:

1) sequentially carrying out LDPC code decoding on every n +1 LDPC code words, wherein the n +1 LDPC code word is an SPC code word, and obtaining hard decision results of the n +1 LDPC code decoding and confidence information L of each bit_i ^j，

Where i is from 1 to N +1, j is from 1 to N, N is the code length of the LDPC code,

L_{{LDPC}_{n + 1}}^{j} = L_{SPC}^{j};

setting the maximum iteration times T of decoding;

b) if only one of the n +1 LDPC code words fails to be decoded, two cases are divided:

if the wrong code word is one of the first n LDPC codes, deleting the wrong code word, then carrying out modulo 2 sum on the rest n correct LDPC code words bit by bit in the column direction, outputting the restored correct code word and finishing decoding;

c) if 2 or more than 2 code words in the n +1 LDPC code words have errors, the step 3) is carried out to carry out iterative longitudinal decoding, and the decoding is finished when the iteration times reach T;

3) separately calculating extrinsic information for each bit of an error codeword

4) updating confidence of each bit of an error codeword

L_{i_{k}}^{j} = L_{i_{k}}^{j} + e_{i_{k}}^{j};

5) And sequentially decoding the error code words with the updated confidence coefficients by using the LDPC codes, and then returning to the step 2).

5. The decoding method according to claim 4, wherein: the confidence L of the code word successfully decoded in the step 3)_i ^jIs of a size of

Symbol is

sgn (L_{i}^{j}) = sgn (L_{i}^{j}),

Where j is 1, 2, …, N, the extrinsic information of each bit of the error codeword

Is of a size of

<math> <mrow> <mo>|</mo> <msubsup> <mi>e</mi> <msub> <mi>i</mi> <mi>k</mi> </msub> <mi>j</mi> </msubsup> <mo>|</mo> <mo>=</mo> <mi>max</mi> <mrow> <mo>(</mo> <munderover> <munder> <mi>min</mi> <mrow> <mi>t</mi> <mo>=</mo> <mn>1</mn> </mrow> </munder> <mrow> <mi>t</mi> <mo>&NotEqual;</mo> <mi>i</mi> </mrow> <mrow> <mi>n</mi> <mo>+</mo> <mn>1</mn> </mrow> </munderover> <mrow> <mo>(</mo> <mo>|</mo> <msubsup> <mi>L</mi> <mi>t</mi> <mi>j</mi> </msubsup> <mo>|</mo> <mo>)</mo> </mrow> <mo>-</mo> <mn>0.2,0</mn> <mo>)</mo> </mrow> <mo>,</mo> </mrow> </math>

Symbol is

Where j is 1, 2, …, N.

6. A decoder for decoding the LDPC-SPC product code as recited in claim 1, comprising four parts of an LDPC code decoding module, a first storage module, an error codeword statistics module, and a hard decision recovery module, wherein:

the LDPC code decoding module decodes every n +1 LDPC code words in sequence, wherein the n +1 th LDPC code word is an SPC code word, and outputs the hard decision information of n +1 LDPC code information bits;

the first storage module is used for storing hard decision information;

the error code word counting module counts error code words in n +1 LDPC codes according to the hard decision information and determines the flow direction of the LDPC code word information bits: if only one code word in the n +1 LDPC code words fails to be decoded and the code word is not an SPC code, entering a hard decision recovery module, otherwise, outputting information bits;

and deleting the wrong LDPC code words by the hard decision recovery module, performing modulo 2 sum on the rest n correct LDPC code words bit by bit in the column direction, obtaining the result as the recovered correct code words, and outputting the recovered correct information bits.

7. The decoder of claim 6, wherein: the first storage module is a dual-port RAM; the error code word statistic module is a counter with an initial value of 0.

8. The decoder of claim 6, wherein: the hard decision recovery module mainly comprises a modulo-2 adder module and a second storage module, wherein the modulo-2 adder module is used for calculating the modulo-2 sum of the information bits of n LDPC code words except the error code word according to the longitudinal direction of the bits and outputting the n correct information bits at the same time; the second storage module is used for storing a temporary result of the modulo-2 adder, namely, performing modulo-2 sum addition with the next frame, and outputting a final accumulation result, namely, the recovered correct information bit.

9. A decoder for decoding the LDPC-SPC product code as recited in claim 1, comprising five parts of an LDPC code decoding module, a first storage module, an error codeword statistics module, an SPC code soft decoding module and a hard decision recovery module, wherein:

the LDPC code decoding module decodes every n +1 LDPC code words in sequence, wherein the n +1 LDPC code words are SPC code words, and outputs soft information and hard decision information of n +1 LDPC code information bits, wherein the soft information is confidence L of each bit_i ^jWherein i is from 1 to N +1, j is from 1 to N, and N is the code length of the LDPC code;

the first storage module is used for storing soft information and hard decision information of the LDPC code information bits;

the error code word counting module counts error code words in n +1 LDPC codes and determines the flow direction of the information bits of the LDPC code words: if only one code word in the n +1 LDPC code words fails to be decoded and the code word is not an SPC code, entering a hard decision recovery module; if more than one code word in the n +1 LDPC code words fails to be decoded, entering an SPC code soft decoding module; if no code word error exists or only the decoding of the SPC code fails, outputting correct information bits;

the hard decision recovery module deletes the wrong LDPC code words, then performs modulo 2 sum on the rest n correct LDPC code words bit by bit in the column direction, the obtained result is the recovered correct code words, and outputs the recovered correct information bits;

the SPC code soft decoding module reserves soft information of the code words with errors in the n +1 LDPC codes, and only reserves hard decision information, namely sign bits, of the correct code words; then separately calculating extrinsic information of each bit of the error code word

Wherein i_kRepresenting a k error code word in n +1 code words, k being a positive integer, j representing a j bit in the k error code word; the obtained external information is used as the prior information of the LDPC code decoding module to decode again, namely, the confidence coefficient of each bit of the error code word is updated

L_{i_{k}}^{j} = L_{i_{k}}^{j} + e_{i_{k}}^{j},

And then inputting the code into an LDPC code decoding module for iterative decoding until the maximum iteration times are reached or all code words are detected correctly.

10. The decoder of claim 9, wherein: the hard decision recovery module mainly comprises a modulo-2 adder module and a second storage module, wherein the modulo-2 adder module is used for calculating the modulo-2 sum of the information bits of n LDPC code words except the error code word according to the longitudinal direction of the bits and outputting the n correct information bits at the same time; the second storage module is used for storing a temporary result of the modulo-2 adder, namely, performing modulo-2 sum addition with the next frame, and outputting a final accumulation result, namely, the recovered correct information bit.