CN100546207C - A kind of dual-binary Turbo code encoding method based on the DVB-RCS standard - Google Patents
A kind of dual-binary Turbo code encoding method based on the DVB-RCS standard Download PDFInfo
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Abstract
Dual-binary Turbo code encoding method and decoder based on the DVB-RCS standard: (1) will receive the dibit system bits input pre-decode device of code word, obtain to the recurrence factor-alpha
1With the backward recursive factor-beta
1Initial value; (2) obtain log-likelihood ratio Λ
1(3) obtain external information L
E1(4) with external information L
E1Obtain prior information L through interweaving
A2(5) the dibit system that will receive code word imports interleaver; (6) result that will interweave imports the pre-decode device, obtains the forward recursive factor-alpha
2With the backward recursive factor-beta
2Initial value; (7) ask log-likelihood ratio Λ
2(8) ask external information L
E2(9) with external information L
E2Obtain prior information L through deinterleaving
A1(10) repeat above-mentioned steps (2)-(4) and step (7)-(9), until satisfying the termination of iterations coding guideline; (11) with log-likelihood ratio Λ
2Behind deinterleaver, carry out hard decision and obtain final decoding bit again.The present invention is easy to hardware and realizes, can adapt to plurality of optional code check and flexible block lengths, and power consumption is little, the error rate is low.
Description
Technical field
The present invention relates to a kind of dual binary turbo code decoder technology, particularly a kind of dual-binary Turbo code encoding method and decoder based on the DVB-RCS standard.
Background technology
Turbo code is a kind of parallel cascade codes that utilizes pseudo random interleaver and simple component code structure, and its performance is limit near Shannon under the white noise channel, and its yard decoded mode is the iterative decoding of soft input or soft output.So-called iteration is exactly that each decoder transmits external information mutually by the iteration order, and along with the increase of iterations, iterative decoding converges on the suboptimum decoding that maximum-likelihood decoding is a kind of low complex degree gradually.The discovery of Turbo code has changed for a long time channel by the history of speed as actual capacity, makes channel coding theorem and practice enter a brand-new stage.Begun to adopt Turbo code in the 3G (Third Generation) Moblie at present.
Traditional Turbo code encoder is the single-bit input, adopts the RSC sign indicating number as component code.This encoder needs to add " ending bit " when coding, this causes code efficiency to descend.Because the minimum free distance of traditional Turbo code is less, it has the error code flat bed when low error rate.Turbo code decoding algorithm commonly used has: Log-MAP algorithm, Max-Log-MAP algorithm and SOVA algorithm, and wherein the Log-MAP algorithm is an optimal algorithm, realizes but be difficult to hardware; Max-Log-MAP algorithm and SOVA algorithm are sub-optimal algorithm, more easily realize.
Summary of the invention
Technology of the present invention is dealt with problems and is: overcome the deficiencies in the prior art, a kind of dual-binary Turbo code encoding method and decoder based on the DVB-RCS standard is provided, it is easy to hardware and realizes, can adapt to plurality of optional code check and flexible block lengths, and power consumption is little, the error rate is low.
Technical solution of the present invention is: based on the dual-binary Turbo code encoding method of DVB-RCS standard, it is characterized in that being achieved as follows:
(1) will receive the dibit system bits y of code word
k S1And y
k S2Import the first pre-decode device, obtain the first forward recursive factor-alpha
1With the first backward recursive factor-beta
1Initial value, described initial value is used at each interative computation the first forward recursive factor in the first component decoder and the first backward recursive factor being carried out initialization, the span of k is 1~t herein, t represents pre-decode length;
(2) will receive the dibit system bits y of code word
k S1And y
k S2, the output of corresponding transmitting terminal first component coder check digit y
k P1, the first prior information L
A1And the first forward recursive factor-alpha of obtaining in the step (1)
1With the first backward recursive factor-beta
1Initial value input to the first component decoder, and obtain the first log-likelihood ratio Λ by the first component decoder
1, the wherein said first prior information L
A1When first step iterative decoding, be initialized as zero, in follow-up decode procedure from first deinterleaver;
(3) according to the first log-likelihood ratio Λ
1, the first prior information L
A1With the first system information L
S1Obtain the first external information L
E1
(4) with the first external information L
E1Obtain the second prior information L through second interleaver
A2
(5) will receive the dibit system bits y of code word
k S1And y
k S2, the y as a result after importing first interleaver and obtaining interweaving
k S3And y
k S4, the span of k is 1~N herein, N represents to receive the length of systematic code in the code word;
(6) y as a result after first interleaver is interweaved
k S3And y
k S4Import the second pre-decode device, obtain the second forward recursive factor-alpha
2With the second backward recursive factor-beta
2Initial value, described initial value is used at each interative computation the second forward recursive factor in the second component decoder and the second backward recursive factor being carried out initialization, the span of k is 1~t herein, t represents pre-decode length;
(7) will be through the dibit system bits y of the reception code word behind first interleaver
k S3And y
k S4, the output of corresponding transmitting terminal second component encoder check digit y
k P1, the second prior information L
A2And the second forward recursive factor-alpha of obtaining in the step (6)
2With the second backward recursive factor-beta
2Initial value input second component decoder, and obtain the second log-likelihood ratio Λ by the second component decoder
2, the wherein said second prior information L
A2When first step iterative decoding, be initialized as zero, in follow-up decode procedure from second interleaver;
(8) according to the second log-likelihood ratio Λ
2, the second prior information L
A2With the second system information L
S2Obtain the second external information L
E2
(9) with the second external information L
E2Obtain the first prior information L through first deinterleaver
A1
(10) decode procedure of repetition above-mentioned steps (2)-(4) and step (7)-(9) is until satisfying the termination of iterations coding guideline;
(11) with the second log-likelihood ratio Λ
2Behind second deinterleaver, carry out hard decision and obtain final decoding bit.
The present invention compared with prior art has following advantage: the present invention adopts two binary inputs, therefore under condition with identical constraint length, with respect to traditional Turbo code decoder, the memory that only needs half, and the required clock frequency of decoder also can reduce half, therefore hardware is easy to realize, and power consumption reduces greatly.The present invention of emulation experiment proof uses the Max-Log-MAP algorithm of suboptimum and deciphers the loss of having only 0.1-0.2dB with respect to the Log-MAP algorithm of using optimum.The present invention can adapt to plurality of optional code check (from 1/3 to 6/7) and unusual flexible block lengths (from 96 to 1728bit).
Description of drawings
Fig. 1 is a system schematic of the present invention;
Fig. 2 is that decoder hardware of the present invention is realized block diagram.
Embodiment
As shown in Figure 1, method of the present invention realizes being made of the first pre-decode device, the second pre-decode device, the first component decoder, second component decoder, first interleaver, second interleaver, first deinterleaver, second deinterleaver and hard decision device, and its concrete implementation step is:
(1) will receive the dibit system bits y of code word
k S1And y
k S2Import the first pre-decode device, obtain the first forward recursive factor-alpha
1With the first backward recursive factor-beta
1Initial value, described initial value is used at each interative computation the first forward recursive factor in the first component decoder and the first backward recursive factor being carried out initialization.
The first forward recursive factor-alpha in the first pre-decode device
1Computing formula be:
The first backward recursive factor-beta
1Computing formula be:
Wherein, S
kThe presentation code device is at k state constantly, and z presentation code device is designated as z=(x in k input constantly
k S1, x
k S2), z ∈ 00,01,10,11};
Y represents the code word that decoder receives;
Above-mentioned
Computing formula in: x
k pThe check digit that the presentation code device is exported constantly at k,
y
k S1And y
k S2Be illustrated respectively in first and second of systematic code that k imports decoder constantly,
y
k pBe illustrated in the check digit that k imports decoder constantly,
Above-mentioned k value between 1~t, t is a pre-decode length,
N
oBe noise one-sided power spectrum density.
(2) will receive the dibit system bits y of code word
k S1And y
k S2, the output of corresponding transmitting terminal first component coder check digit y
k P1, the first prior information L
A1And the first forward recursive factor-alpha of obtaining in the step (1)
1With the first backward recursive factor-beta
1Initial value input to the first component decoder, and obtain the first log-likelihood ratio Λ by the first component decoder
1, the wherein said first prior information L
A1When first step iterative decoding, be initialized as zero, in follow-up decode procedure from first deinterleaver.
The first log-likelihood ratio Λ in the first component decoder
1Computing formula be:
Wherein: S
kThe presentation code device is at k state constantly;
Wherein: z presentation code device is designated as z=(x in k input constantly
k S1, x
k S2), z ∈ 00,01,10,11};
x
k pThe check digit that the presentation code device is exported constantly at k;
y
k S1And y
k S2Be illustrated respectively in first and second of systematic code that k imports decoder constantly;
y
k pBe illustrated in the check digit that k imports decoder constantly;
Above-mentioned k value between 1~N, N is the length of systematic code in the code word;
N
oBe noise one-sided power spectrum density.
(3) according to the first log-likelihood ratio Λ
1, the first prior information L
A1With the first system information L
S1Obtain the first external information L
E1
The first external information L
E1Computing formula be:
Wherein: L
A1It is first prior information; Λ
1It is first log-likelihood ratio;
Wherein: y
k s=(y
k S1, y
k S2) systematic code that receives for decoder;
Z presentation code device is designated as z=(x in k input constantly
k S1, x
k S2), z ∈ 00,01,10,11};
Above-mentioned k value between 1~N, N is the length of systematic code in the code word;
N
oBe noise one-sided power spectrum density.
(4) with the first external information L
E1Obtain the second prior information L through second interleaver
A2The second interleaver implementation procedure is: press interleaving address with the first external information L
E1Write register, read the address in order then, obtains the second prior information L
A2
(5) will receive the dibit system bits y of code word
k S1And y
k S2, the y as a result after importing first interleaver and obtaining interweaving
k S3And y
k S4The first interleaver implementation procedure is: the address writes register with the systematic code that whole decoder receives in order, reads by interleaving address then, the y as a result after obtaining interweaving
k S3And y
k S4, k value between 1~N wherein, N is the length of systematic code in the code word.
(6) y as a result after first interleaver is interweaved
k S3And y
k S4Import the second pre-decode device, obtain the second forward recursive factor-alpha
2With the second backward recursive factor-beta
2Initial value, described initial value is used at each interative computation the second forward recursive factor in the second component decoder and the second backward recursive factor being carried out initialization.
The second forward recursive factor-alpha in the second pre-decode device
2Computing formula be:
The second backward recursive factor-beta
2Computing formula be:
In the above-mentioned formula:
S
kThe presentation code device is at k state constantly; Z presentation code device is designated as z=(x in k input constantly
k S1, x
k S2), z ∈ 00,01,10,11};
The sequence that the code word that the expression decoder receives obtains behind first interleaver;
Wherein: x
k pThe check digit that the presentation code device is exported constantly at k;
y
k S3And y
k S4Expression respectively
In first and second of systematic code; y
k pBe illustrated in the check digit that k imports decoder constantly;
Above-mentioned k value between 1~t, t is a pre-decode length;
N
oBe noise one-sided power spectrum density.
(7) will be through the dibit system bits y of the reception code word behind first interleaver
k S3And y
k S4, the output of corresponding transmitting terminal second component encoder check digit y
k P2, the second prior information L
A2And the second forward recursive factor-alpha of obtaining in the step (6)
2With the second backward recursive factor-beta
2Initial value input second component decoder, and obtain the second log-likelihood ratio Λ by the second component decoder
2, the wherein said second prior information L
A2When first step iterative decoding, be initialized as zero, in follow-up decode procedure from second interleaver.
The second log-likelihood ratio Λ in the second component decoder
2Computing formula be:
Wherein: S
kThe presentation code device is at k state constantly;
The sequence that the code word that the expression decoder receives obtains behind first interleaver;
Wherein: z presentation code device is designated as z=(x in k input constantly
k S1, x
k S2), z ∈ 00,01,10,11};
x
k pThe check digit that the presentation code device is exported constantly at k;
y
k S3And y
k S4Expression respectively
In first and second of systematic code; y
k pBe illustrated in the check digit that k imports decoder constantly;
Above-mentioned k value between 1~N, N is the length of systematic code in the code word;
N
oBe noise one-sided power spectrum density.
(8) according to the second log-likelihood ratio Λ
2, the second prior information L
A2With the second system information L
S2Obtain the second external information L
E2
The second external information L
E2Computing formula be:
Wherein: L
A2It is second prior information; Λ
2It is second log-likelihood ratio;
Wherein:
The sequence that the systematic code that receives for decoder obtains after through first interleaver;
Z presentation code device is designated as z=(x in k input constantly
k S1, x
k S2), z ∈ 00,01,10,11};
Above-mentioned k value between 1~N, N is the length of systematic code in the code word;
N
oBe noise one-sided power spectrum density.
(9) with the second external information L
E2Obtain the first prior information L through first deinterleaver
A1First deinterleaver is embodied as: press the deinterleaving address with the second external information L
E2Write register, read the address in order then, obtains the first prior information L
A1
(10) decode procedure of repetition above-mentioned steps (2)-(4) and step (7)-(9) is until satisfying the termination of iterations coding guideline;
(11) with the second log-likelihood ratio Λ
2Behind second deinterleaver, carry out hard decision and obtain final decoding bit.
The second deinterleaver implementation procedure is: press the deinterleaving address with the second log-likelihood ratio Λ
2Write register, read the address in order then, obtains final log-likelihood ratio information
Hard decision is to final log-likelihood ratio
{ 00,01,10, the data among the 11} are carried out size relatively to z ∈, and the pairing dibit of the maximum is judged as final decoding bit.
As shown in Figure 2, hardware of the present invention realizes mainly comprising ping-pong ram, component decoder, system information arithmetic unit, external information RAM, log-likelihood ratio RAM and six modules of hard decision device.
Ping-pong ram is used for storage and receives data, and first frame data that receive deposit ping-pong ram 1 earlier in, treat that the storage of first frame data finishes after, follow-up decoding module begins reading of data from ping-pong ram 1; If this moment, second frame data arrived, then it is deposited in ping-pong ram 2, follow-up decoding module is handled beginning after the data in the ping-pong ram 1 and is handled data in the ping-pong ram 2 continuously; If this moment, the 3rd frame data arrived, then it is deposited in ping-pong ram 1, repeat above-mentioned processing.The present invention guarantees that decoder handles the time of frame data and be at most the time that receives frame data, so this ping-pong ram can operate as normal.
The component decoder is used for realizing the first pre-decode device, the first component decoder, the second pre-decode device and the second component decoder of Fig. 1.Because the realization principle of back is all identical, just difference to some extent on input data and iterations, and back in use between on do not have overlapping, so can realize back four kinds of modules simultaneously with the time-multiplexed mode of one-component decoder employing.This implementation can be saved a large amount of resources.
The system information arithmetic unit is used for the system information L shown in the calculating chart 1
S1And L
S2
External information RAM is used to store external information L shown in Figure 1
E1And L
E2, because L
E1And L
E2Have the identical width and the degree of depth, and have precedence relationship in use, so can adopt time-multiplexed mode to store with same RAM.Described external information RAM is used to realize interleaver shown in Figure 12 and deinterleaver 1 simultaneously, and the specific implementation method is, with L
E1Or L
E2Write external information RAM by interleaving address, then in order the address read be prior information L
A2Or L
A1
Log-likelihood ratio RAM is used to store the log-likelihood ratio Λ that iteration finishes back component decoder output
2
The hard decision device is used for Λ that log-likelihood ratio RAM is stored
2Carry out hard decision, the output of this module be final decoding bit.
The implementation procedure of decoder of the present invention is: each interative computation was divided into for two steps to carry out, the first step from ping-pong ram, read receive by transmitting terminal first component coder (with reference among ETSI EN 301 790V1.4.1 (2005-09) about the introduction of Turbo encoder) the check digit check1 of output, and the systematic code that receives is read in the address in order, obtain system_natur, switch 1 closure, both are imported the component decoder, and the component decoder of this moment is realized the function of the first pre-decode device and the first component decoder and is exported the first log-likelihood ratio Λ
1, the systematic code that receives that simultaneity factor information arithmetic unit is read from ping-pong ram according to address in order calculates the first system information L
S1, with the first log-likelihood ratio Λ
1, the first system information L
S1With the first prior information L
A1Input summer obtains the first external information L
E1, with the first external information L
E1Input external information RAM, external information RAM exports the second prior information L
A2Second step was read the check digit check2 by the output of transmitting terminal second component encoder that receives from ping-pong ram, and read the systematic code that receives by interleaving address, obtain system_inter, switch 2 closures, with its input component decoder, this real component decoder is realized the function of the second pre-decode device and second component decoder and is exported the second log-likelihood ratio Λ
2, simultaneity factor information arithmetic unit calculates the second system information L according to the systematic code that receives of reading by interleaving address from ping-pong ram
S2, with the second log-likelihood ratio Λ
2, the second system information L
S2With the second prior information L
A2Input summer obtains the second external information L
E2, with the second external information L
E2Input external information RAM, external information RAM exports the first prior information L
A1Repeat said process until satisfying stopping criterion for iteration; Iteration is sent into the log-likelihood ratio that the component decoder is calculated at last in log-likelihood ratio RAM and the hard decision device after stopping successively, obtains final decoding bit.
Claims (6)
1, a kind of dual-binary Turbo code encoding method based on the DVB-RCS standard is characterized in that performing step is as follows:
(1) will receive the dibit system bits y of code word
k S1And y
k S2Import the first pre-decode device, obtain the first forward recursive factor-alpha
1With the first backward recursive factor-beta
1Initial value, described initial value is used at each interative computation the first forward recursive factor in the first component decoder and the first backward recursive factor being carried out initialization, the span of k is 1~t herein, t represents pre-decode length;
The first forward recursive factor-alpha in the described first pre-decode device
1Computing formula be:
The first backward recursive factor-beta
1Computing formula be:
Wherein, S
kThe presentation code device is at k state constantly, and z presentation code device is designated as z=(x in k input constantly
k S1, x
k S2), z ∈ 00,01,10,11};
Y represents the code word that decoder receives;
The natural logrithm form of expression state transition probability, computing formula is:
Above-mentioned
Computing formula in: x
k pThe check digit that the presentation code device is exported constantly at k,
y
k S1And y
k S2Be illustrated respectively in first and second of systematic code that k imports decoder constantly,
y
k pBe illustrated in the check digit that k imports decoder constantly,
Above-mentioned k value between 1~t, t is a pre-decode length,
N
oBe noise one-sided power spectrum density;
(2) will receive the dibit system bits y of code word
k S1And y
k S2, the output of corresponding transmitting terminal first component coder check digit y
k P1, the first prior information L
A1And the first forward recursive factor-alpha of obtaining in the step (1)
1With the first backward recursive factor-beta
1Initial value input to the first component decoder, and obtain the first log-likelihood ratio Λ by the first component decoder
1, the wherein said first prior information L
A1When first step iterative decoding, be initialized as zero, in follow-up decode procedure from first deinterleaver;
The first log-likelihood ratio Λ in the described first component decoder
1Computing formula be:
Wherein: S
kThe presentation code device is at k state constantly;
Wherein: z presentation code device is designated as z=(x in k input constantly
k S1, x
k S2), z ∈ 00,01,10,11};
x
k pThe check digit that the presentation code device is exported constantly at k;
y
k S1And y
k S2Be illustrated respectively in first and second of systematic code that k imports decoder constantly;
y
k pBe illustrated in the check digit that k imports decoder constantly;
Above-mentioned k value between 1~N, N is the length of systematic code in the code word;
N
oBe noise one-sided power spectrum density;
(3) according to the first log-likelihood ratio Λ
1, the first prior information L
A1With the first system information L
S1Obtain the first external information L
E1
The described first external information L
E1Computing formula be:
Wherein: L
A1It is first prior information; Λ
1It is first log-likelihood ratio;
Wherein: y
k s=(y
k S1, y
k S2) systematic code that receives for decoder;
Z presentation code device is designated as z=(x in k input constantly
k S1, x
k S2), z ∈ 00,01,10,11};
Above-mentioned k value between 1~N, N is the length of systematic code in the code word;
N
oBe noise one-sided power spectrum density;
(4) with the first external information L
E1Obtain the second prior information L through second interleaver
A2
(5) will receive the dibit system bits y of code word
k S1And y
k S2, the y as a result after importing first interleaver and obtaining interweaving
k S3And y
k S4, the span of k is 1~N herein, N represents to receive the length of systematic code in the code word;
(6) y as a result after first interleaver is interweaved
k S3And y
k S4Import the second pre-decode device, obtain the second forward recursive factor-alpha
2With the second backward recursive factor-beta
2Initial value, the described second forward recursive factor-alpha
2With the second backward recursive factor-beta
2Initial value be used for the second forward recursive factor in the second component decoder and the second backward recursive factor being carried out initialization at each interative computation, the span of k is 1~t herein, t represents pre-decode length;
The second forward recursive factor-alpha in the described second pre-decode device
2Computing formula be:
The second backward recursive factor-beta
2Computing formula be:
In the above-mentioned formula:
S
kThe presentation code device is at k state constantly; Z presentation code device is designated as z=(x in k input constantly
k S1, x
k S2), z ∈ 00,01,10,11};
The sequence that the code word that the expression decoder receives obtains behind first interleaver;
The natural logrithm form of expression state transition probability, its computing formula is:
Wherein: x
k pThe check digit that the presentation code device is exported constantly at k;
y
k S3And y
k S4Expression respectively
In first and second of systematic code; y
k pBe illustrated in the check digit that k imports decoder constantly;
Above-mentioned k value between 1~t, t is a pre-decode length;
N
oBe noise one-sided power spectrum density;
(7) will be through the dibit system bits y of the reception code word behind first interleaver
k S3And y
k S4, the output of corresponding transmitting terminal second component encoder check digit y
k P2, the second prior information L
A2And the second forward recursive factor-alpha of obtaining in the step (6)
2With the second backward recursive factor-beta
2Initial value input second component decoder, and obtain the second log-likelihood ratio Λ by the second component decoder
2, the wherein said second prior information L
A2When first step iterative decoding, be initialized as zero, in follow-up decode procedure from second interleaver;
The second log-likelihood ratio Λ in the described second component decoder
2Computing formula be:
Wherein: S
kThe presentation code device is at k state constantly;
The sequence that the code word that the expression decoder receives obtains behind first interleaver;
Wherein: z presentation code device is designated as z=(x in k input constantly
k S1, x
k S2), z ∈ 00,01,10,11};
x
k pThe check digit that the presentation code device is exported constantly at k;
y
k S3And y
k S4Expression respectively
In first and second of systematic code; y
k pBe illustrated in the check digit that k imports decoder constantly;
Above-mentioned k value between 1~N, N is the length of systematic code in the code word;
N
oBe noise one-sided power spectrum density;
(8) according to the second log-likelihood ratio Λ
2, the second prior information L
A2With the second system information L
S2Obtain the second external information L
E2The described second external information L
E2Computing formula be:
Wherein: L
A2It is second prior information; Λ
2It is second log-likelihood ratio;
Second system information
Computing formula be:
Wherein:
The sequence that the systematic code that receives for decoder obtains after through first interleaver;
Z presentation code device is designated as z=(x in k input constantly
k S1, x
k S2), z ∈ 00,01,10,11};
Above-mentioned k value between 1~N, N is the length of systematic code in the code word;
N
oBe noise one-sided power spectrum density;
(9) with the second external information L
E2Obtain the first prior information L through first deinterleaver
A1
(10) decode procedure of repetition above-mentioned steps (2)-(4) and step (7)-(9) is until satisfying the termination of iterations coding guideline;
(11) with the second log-likelihood ratio Λ
2Behind second deinterleaver, carry out hard decision and obtain final decoding bit.
2, the dual-binary Turbo code encoding method based on the DVB-RCS standard according to claim 1 is characterized in that: the second interleaver implementation procedure in the described step (4) is: press interleaving address with the first external information L
E1Write register, read the address in order then, obtains the second prior information L
A2
3, the dual-binary Turbo code encoding method based on the DVB-RCS standard according to claim 1, it is characterized in that: the first interleaver implementation procedure in the described step (5) is: the address writes register with the systematic code that whole decoder receives in order, read the y as a result after obtaining interweaving then by interleaving address
k S3And y
k S4, k value between 1~N wherein, N is the length of systematic code in the code word.
4, the dual-binary Turbo code encoding method based on the DVB-RCS standard according to claim 1 is characterized in that: the first deinterleaver implementation procedure in the described step (9) is: press the deinterleaving address with the second external information L
E2Write register, read the address in order then, obtains the first prior information L
A1
5, the dual-binary Turbo code encoding method based on the DVB-RCS standard according to claim 1 is characterized in that: the second deinterleaver implementation procedure in the described step (11) is: press the deinterleaving address with the second log-likelihood ratio Λ
2Write register, read the address in order then, obtains final log-likelihood ratio information
6, the dual-binary Turbo code encoding method based on the DVB-RCS standard according to claim 1 is characterized in that: the hard decision in the described step (11) is to final log-likelihood ratio
In data carry out size relatively, wherein z ∈ 00,01,10,11}, the pairing dibit of the maximum is judged as final decoding bit.
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