CN100533696C - Method for manufacturing semiconductor element - Google Patents
Method for manufacturing semiconductor element Download PDFInfo
- Publication number
- CN100533696C CN100533696C CNB2007100083131A CN200710008313A CN100533696C CN 100533696 C CN100533696 C CN 100533696C CN B2007100083131 A CNB2007100083131 A CN B2007100083131A CN 200710008313 A CN200710008313 A CN 200710008313A CN 100533696 C CN100533696 C CN 100533696C
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- Prior art keywords
- semiconductor element
- manufacture method
- colloid
- semiconductor chip
- mould
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1515—Shape
- H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
- H01L2924/15155—Shape the die mounting substrate comprising a recess for hosting the device the shape of the recess being other than a cuboid
- H01L2924/15156—Side view
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19107—Disposition of discrete passive components off-chip wires
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- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
A method for manufacturing semiconductor elements at least comprises: providing a die, coating a colloid on one surface of the die, providing at least one semiconductor chip, wherein the semiconductor chip is provided with a first side and a second side which are opposite to each other and the first side of the semiconductor chip is pressed in one portion of the colloid, exposing the second side of the semiconductor chip to form a sticking layer coated on the second side of the semiconductor chip and on the exposed portion of the colloid, forming a metal heat radiation base on the sticking layer, removing the colloid and the die, arranging a circuit board on the exposed portion of the sticking layer, providing a plurality of lead wires to electrically connect the circuit board and the semiconductor chip and forming a colloid sealing layer to completely cover the semiconductor chip, the lead wires and the exposed portion of the sticking layer.
Description
Technical field
The manufacture method of the relevant a kind of semiconductor element of the present invention, and the manufacture method of the metal cooling seat of relevant a kind of semiconductor element particularly.
Background technology
Present semiconductor element, for example transistor, integrated circuit or light-emitting diode (Light-emittingDiode; LED), laser diode (Laser Diode; LD) or solar cell photoelectric cells such as (Solar Cell), encapsulation is used the metal derby mode except that flip-chip (Flip-chip) and substrate engages, and all must use colloid or tin cream to carry out engaging of chip and support or base.
When being applied in big small-sized backlight or light fixture, all need use a large amount of semiconductor chips that enough brightness and illumination just can be provided.Yet, when under high input power condition, operating, the temperature of the assembly of being made up of various semiconductor spare parts and photoelectric cell can fast rise, not only can influence the operation quality and the life-span of assembly, also may cause photoelectric cell Yin Gaowen wherein and burns.
The problem that the temperature that is faced when operating for solution semiconductor element assembly raises, modes such as many at present plug-in fans of use or increase heating panel area reduce the temperature of assembly.Yet in the mode of plug-in fan, the vibrations that the running of fan produced will cause the light source stability difference and cause light source scintillation, and electric fan running needs to consume extra power, in addition, plug-in fan with increase heating panel and make that also system bulk greatly increases.On the other hand, increase in the mode of heating panel area, though radiating seat can adopt the metal of high thermal conductivity coefficient, yet photoelectric cell is the colloid that is mixed with metal with the media that engages between the radiating seat, but the conductive coefficient of colloid is far below simple metal, therefore the heat that will be produced in the time of will causing the device running is accumulated on the joint interface mostly, cause radiating seat can't bring into play its heat sinking function really, and the heat dissipation that causes radiating seat is clear, causes photoelectric cell to damage easily under long period of operation or can't operate under big input power condition.
In addition, semiconductor chip fix with colloid and tin cream or the technology with upside-down mounting chip encapsulation in, all need to be heated to more than 150 ℃, thus, in the process that adds the heat fixation semiconductor chip, easily element characteristic is caused damage.
Therefore, along with the raising day by day of the application demand of semiconductor element on various assemblies, press for and a kind ofly can technology simple and easy to implement produce semiconductor element with high heat dissipation efficiency.
Summary of the invention
Therefore, the purpose of this invention is to provide a kind of manufacture method of semiconductor element, it is to be coated with colloid on mould or semiconductor chip, and semiconductor chip is installed on the mould.Thus, can solve adhesive tape and mould and paste irregular problem, also can avoid bubble between adhesive tape and the mould pasted, to produce.Therefore, can effectively reduce the degree of difficulty of the deposition procedures of metal cooling seat, and can promote the operation yield.
Another object of the present invention provides a kind of manufacture method of semiconductor element, by colloid directly is coated on semiconductor chip or the mould, can make semiconductor chip be fixed on the mould smoothly, can directly metal cooling seat be deposited on the bottom surface of semiconductor chip thus, thereby semiconductor chip need not can be arranged on the radiating seat by colloid or tin cream.Therefore, not only can be rapidly and reduce the temperature of running element effectively, to guarantee the operation quality of element, prolong the life-span of element.
Another purpose of the present invention provides a kind of manufacture method of semiconductor element, is by colloid semiconductor chip to be fixed on the mould, with direct plated metal radiating seat on the bottom surface of semiconductor chip.Because colloid can be smooth and bubble-freely be coated on the mould of arbitrary shape, therefore can produce the radiating seat of arbitrary shape, to satisfy product demand miscellaneous.In addition, therefore the cost of colloid can reduce the technology cost far below adhesive tape.
A further object of the present invention provides a kind of manufacture method of semiconductor element, can under the situation of suitable low temperature semiconductor chip be fixed on the metal cooling seat, therefore can avoid the light and the electrical characteristics of element are caused damage.
According to above-mentioned purpose of the present invention, a kind of manufacture method of semiconductor element is proposed, comprise at least: a mould is provided; The coating colloid is on a surface of mould; At least one semiconductor chip is provided, and wherein this semiconductor chip has the first relative side and second side, and first side pressure of semiconductor chip is located in the part of colloid, and second side of semiconductor chip is exposed; Form on the expose portion that an adhesion layer covers second side of semiconductor chip and colloid; Form a metal cooling seat on adhesion layer; Remove colloid and mould; The expose portion of circuit board in adhesion layer is set; Provide a plurality of leads to electrically connect circuit board and semiconductor chip; And form the expose portion that an adhesive layer covers semiconductor chip, lead and adhesion layer fully.
According to a preferred embodiment of the present invention, the material of above-mentioned colloid can be macromolecular material, silica type material, epoxy resin material or acryl class material.
According to purpose of the present invention, a kind of manufacture method of semiconductor element is proposed, comprise at least: at least one semiconductor chip is provided, and wherein this semiconductor chip has the first relative side and second side; The coating colloid is on first side of semiconductor chip; One mould is provided, and first side of semiconductor chip is attached on the surface of mould, and second side of semiconductor chip is exposed; Form on the expose portion on surface of the expose portion of second side that an adhesion layer covers semiconductor chip, colloid and mould; Form a metal cooling seat on adhesion layer; And remove colloid and mould.
According to a preferred embodiment of the present invention, on be set forth in when being sticked semiconductor chip, also comprise at least: at least one circuit board is provided, and wherein this circuit board comprises an insulating barrier and a conductive layer that piles up mutually at least; And be coated with above-mentioned colloid on circuit board, and make colloid envelope conductive layer fully, and insulating layer exposing is gone out.
Description of drawings
Figure 1A to Fig. 9 B is profile and the corresponding top view of demonstration according to the production process of a kind of semiconductor element of a preferred embodiment of the present invention.
Embodiment
The present invention discloses a kind of manufacture method of semiconductor element, utilizes the auxiliary of colloid, can be directly at the bottom surface of semiconductor chip plated metal radiating seat.Owing between the bottom surface of semiconductor chip and the metal cooling seat and need not utilize colloid or tin cream to engage, therefore can promote the heat dissipation of semiconductor chip widely.In order to make narration of the present invention more detailed and complete, can and cooperate diagram with reference to following description with reference to Figure 1A to Fig. 9 B.
Please refer to Figure 1A to Fig. 9 B, it is profile and the corresponding top view of demonstration according to the production process of a kind of semiconductor element of a preferred embodiment of the present invention.At first, one or more semiconductor chips are provided, wherein semiconductor chip can for example be transistor, monolithic integrated circuit (Monolithic IC) or optoelectronic device chip, for example central processing unit chip (CPU), light-emitting diode chip for backlight unit, laser diode chip or solar cell (Solar Cell).In one embodiment of this invention, semiconductor chip has electrically two opposite electrodes, and this two electrode can be positioned at the same side of semiconductor chip or homonymy not, optoelectronic device chip 100a shown in Figure 1A and the optoelectronic device chip 100b shown in Figure 1B.Wherein, the two electrical opposite electrode 102a and the 104a that are had of optoelectronic device chip 100a all is located on the same side of optoelectronic device chip 100a; The two electrode 102b that optoelectronic device chip 100b is had then are located at respectively on relative two sides of optoelectronic device chip 100b with 104b.When electrode 102a/102b electrically be the N type time, the electrical of electrode 104a/104b is the P type; And when electrode 102a/102b electrically be the P type time, electrode 104a/104b's electrically then is the N type.Then, colloid 106 is coated on optoelectronic device chip 100a and 100b has on the side of at least one electrode, shown in Figure 1A and Figure 1B.In the present invention, colloid 106 has stickiness, and the material of colloid 106 can be for example macromolecular material (Polymer), silica type (Silica) material, epoxy resin (Epoxy) class material, phenolic resins (Phenolic) class material, acryl (Acrylic) class material or photoresistance (Photoresist) class material.Because colloid 106 is non-solid matter, when therefore being coated on the optoelectronic device chip 100a/100b, can avoid bubble to be created in the interface of optoelectronic device chip 100a/100b and colloid 106.
In the present invention, when semiconductor chip is transistor or monolithic integrated circuit, semiconductor chip can be made up of the silicon series material, perhaps be made up of compound semiconductor materials, wherein compound semiconductor materials can for example be gallium nitride series (GaN-Based) material, AlGaInP series (AlGaInP-Based) material, vulcanized lead series (PbS-Based) material or silicon-carbide series (SiC-Based) material.On the other hand, when semiconductor chip is optoelectronic device chip, optoelectronic device chip can be made up of the silicon series material, perhaps be made up of compound semiconductor materials, wherein compound semiconductor materials can for example be gallium nitride series material, AlGaInP series material, vulcanized lead series material or silicon-carbide series material.
In following example embodiment, semiconductor chip is with three optoelectronic device chip 100b technology of the present invention to be described as an example.
Simultaneously, provide mould 108, shown in Fig. 2 A and Fig. 2 B.In the present invention, mould can have flat surfaces, plane formula substrate for example, perhaps can be according to product demand the shape of designing mould, and then obtain the mould that the surface has the D structure thing.In this example embodiment, according to product demand, the surface 112 of mould 108 convexes with D structure thing 110, shown in Fig. 2 A.
Then, the side that optoelectronic device chip 100b is coated with colloid 106 is sticked on the D structure thing 110 on the surface 112 of mould 108, and make with respect to the opposite side of the optoelectronic device chip 100b of this side that is sticked up and come out, shown in the top view of the profile of Fig. 3 A and corresponding Fig. 3 B.
In another embodiment of the present invention, colloid 106 also can be coated on the surface 112 of mould 108 earlier, again the side pressure with at least one electrode of these optoelectronic device chips 100b is located in the part of colloid 106, and the opposite side with respect to the optoelectronic device chip 100b of this side that is sticked is come out.Because colloid 106 is non-be solid-state, therefore can smooth and bubble-freely be coated on the surface 112 of mould 108 of arbitrary shape, technology obviously uses adhesive tape to be simple and easy to execution.
Treat that optoelectronic device chip 100b is sticked behind the surface 112 of mould 108, directly utilize for example evaporation (Evaporation) depositional mode, sputter (Sputtering) depositional mode or electroless-plating (Electroless Plating) mode, form on the exposed region on surface 112 of the expose portion of exposed surface that adhesion layer 114 covers optoelectronic device chip 100b, colloid 106 and mould 108.The material of adhesion layer 114 is preferably the metal material of selecting the tool tack for use.In the present invention, the material of adhesion layer 114 can for example be selected tin indium oxide (ITO), tantalum nitride (TaN), titanium nitride (TiN), nickel (Ni), chromium (Cr), titanium (Ti), tantalum (Ta), aluminium (Al), indium (In), nickel alloy, evanohm, titanium alloy, tantalum alloy, aluminium alloy or indium alloy for use.The thickness of adhesion layer 114 is preferably less than 10 μ m.Subsequently, can directly make the radiating seat of semiconductor chip, perhaps can the reflector optionally be set on semiconductor chip according to product demand.For example, shown in the top view of the profile of Fig. 4 A and corresponding Fig. 4 B, can utilize vapor deposition method, sputter-deposited method, wireless plating technology or galvanoplastic formation metallic reflector 116 to cover on the adhesion layer 114 of optoelectronic device chip 100b top, wherein the material of metallic reflector 116 can adopt the preferable metal of reflectivity, for example be the alloy of aluminium (Al), silver (Ag), gold (Au), copper (Cu), rhodium (Rh), platinum (Pt), chromium, nickel, titanium or above-mentioned metal, and can be single metal level or multilayer composite metal layer.In the present invention, the thickness of metallic reflector 116 is preferably less than 10 μ m.
Next, utilize for example plating mode or electroless-plating mode, form the thicker metal of one deck and cover on the metallic reflector 116, with as metal cooling seat 118, shown in the top view of the profile of Fig. 5 A and Fig. 5 B.Because the present invention adopts plating mode or electroless-plating mode to make metal cooling seat 118, so metal cooling seat 118 is in fact only grown up on metallic reflector 116.In the present invention, the material of metal cooling seat 118 is preferably and adopts the good metal of thermal diffusivity, for example copper or copper alloy, the perhaps alloy of iron/nickel alloy, nickel, aluminium, tungsten or these metals.Metal cooling seat 118 has bigger thickness usually, and for example thickness is preferable can be greater than 10 μ m, so that bigger amount of thermal conduction and thermal capacity to be provided.
After finishing the making of metal cooling seat 118, remove colloid 106 and mould 108, be subjected to the part that colloid 106 covers originally and expose optoelectronic device chip 100b, and expose adhesion layer 114 simultaneously, shown in the top view of the profile of Fig. 6 A and Fig. 6 B.Then, can optionally cut, and form the metal cooling seat 118 of suitable size according to the actual product demand.
Next,, one or more circuit boards 124 are set, shown in the top view of the profile of Fig. 7 A and Fig. 7 B according to product demand.Wherein, circuit board 124 comprises insulating barrier 120 and the conductive layer 122 that is stacked in regular turn on the adhesion layer 114 at least.Insulating barrier 120 is between adhesion layer 114 and conductive layer 122, with electrical isolation adhesion layer 114 and conductive layer 122.Cooperate the variation of the shape of mould 108, the conductive layer 122 of circuit board 124 can have arbitrary graphic pattern, shown in Fig. 7 B.
Though in above-mentioned example embodiment, circuit board 124 just is provided with after mould 108 and colloid 106 all remove.Yet, the present invention is not limited to above-mentioned, in another embodiment of the present invention, in the time of can on the side of optoelectronic device chip 100b, being coated with colloid 106, on circuit board 124, be coated with colloid 106 simultaneously, and make colloid 106 envelope the conductive layer 122 of circuit board 124 fully, contact with conductive layer 122 and produce with the adhesion layer 114 of the conduction of avoiding follow-up formation and electrically conduct.Insulating barrier 120 is not entirely colloid 106 and covers and expose.Then, as optoelectronic device chip 100b, are located on the surface 112 of mould 108 circuit board 124 is glutinous by colloid 106, and subsequent deposition is covered simultaneously at the adhesion layer 114 on the surface 112 of mould 108 on the expose portion of insulating barrier 120 of circuit board 124.With above-mentioned example embodiment, carry out subsequent handling for another example.
In another embodiment of the present invention, if colloid 106 is to be coated on earlier on the surface 112 of mould 108, then can be when pressure be established optoelectronic device chip 100b, simultaneously circuit board 124 is pressed and be located in another part of colloid 106, and conductive layer 122 is coated in the colloid 106 fully, and insulating barrier 120 is exposed, contact with conductive layer 122 and produce with the adhesion layer 114 of the conduction of avoiding follow-up formation and electrically conduct.Thus, subsequent deposition is covered on the expose portion of insulating barrier 120 of circuit board 124 simultaneously at the adhesion layer 114 on the surface 112 of mould 108.With above-mentioned example embodiment, carry out subsequent handling for another example.
After treating that circuit board 124 setting is finished, several leads 126 can be set, the different electrical electrode 102b that makes optoelectronic device chip 100b and 104b respectively with conductive layer 122 electric connections of corresponding electrical circuit board 124.Several outer leads 128 are set again, and these outer leads 128 are connected with same polarity person in the circuit board 124, shown in the top view of the profile of Fig. 8 A and Fig. 8 B.Thus, by lead 126 and outer lead 128, can make the smooth and outside line electric connection of optoelectronic device chip 100b.
Then, can carry out the sealing program, to form adhesive layer 130, adhesive layer 130 adhesion layer 114 that covers optoelectronic device chip 100b, all leads 126 fully and expose wherein, and envelope outer lead 128 and lead 126 engaging portion, and the circuit board 124 of cover part, and finish the making of semiconductor element 132 is shown in the top view of the profile of Fig. 9 A and Fig. 9 B.
By the invention described above preferred embodiment as can be known, an advantage of the present invention is exactly because the manufacture method of semiconductor element of the present invention is to be coated with colloid on mould or semiconductor chip, and semiconductor chip is installed on the mould.Therefore, can solve adhesive tape and mould and paste irregular problem, also can avoid bubble between adhesive tape and the mould pasted, to produce.So can effectively reduce the degree of difficulty of the deposition procedures of metal cooling seat, and can promote the operation yield.
By the invention described above preferred embodiment as can be known, another advantage of the present invention be exactly because the manufacture method of semiconductor element of the present invention by colloid directly is coated on semiconductor chip or the mould, can make semiconductor chip be fixed on the mould smoothly, can directly metal cooling seat be deposited on the bottom surface of semiconductor chip thus, thereby semiconductor chip need not can be arranged on the radiating seat by colloid or tin cream.Therefore, not only can be rapidly and reduce the temperature of running element effectively, to guarantee the operation quality of element, prolong the life-span of element.
By the invention described above preferred embodiment as can be known, another advantage of the present invention is exactly because the manufacture method of semiconductor element of the present invention is by colloid semiconductor chip to be fixed on the mould, with direct plated metal radiating seat on the bottom surface of semiconductor chip.Because colloid can be smooth and bubble-freely be coated on the mould of arbitrary shape, therefore can produce the radiating seat of arbitrary shape, to satisfy product demand miscellaneous.In addition, therefore the cost of colloid can reduce the technology cost far below adhesive tape.
By the invention described above preferred embodiment as can be known, an advantage more of the present invention is exactly because the manufacture method of semiconductor element of the present invention is that colloid is uniformly coated on the mould or semiconductor chip of arbitrary shape, through after evaporation, plating or the electroless plated metal technology, can produce the metallic reflector and the metal cooling seat of arbitrary shape one-body moldedly, therefore can significantly increase the functional and using value of product.
By the invention described above preferred embodiment as can be known, an advantage more of the present invention is exactly because the manufacture method of semiconductor element of the present invention can be under the situation of suitable low temperature, for example be lower than under 30 ℃, semiconductor chip is fixed on the metal cooling seat, therefore can avoids the light and the electrical characteristics of element are caused damage.
Though the present invention discloses as above with a preferred embodiment; yet it is not in order to limit the present invention; any those having an ordinary knowledge in this technical field; without departing from the spirit and scope of the present invention; when can doing various changes that are equal to and retouching, so protection scope of the present invention is when looking accompanying being as the criterion that the application's claim scope defined.
Claims (20)
1. the manufacture method of a semiconductor element comprises at least:
One mould is provided;
The coating colloid is on a surface of this mould;
At least one semiconductor chip is provided, and wherein this semiconductor chip has one first relative side and one second side, and this first side pressure of this semiconductor chip is located in the part of this colloid, and this second side of this semiconductor chip is exposed;
Form on the expose portion that an adhesion layer covers this second side of this semiconductor chip and this colloid;
Form a metal cooling seat on this adhesion layer; And
Remove this colloid and this mould.
2. the manufacture method of semiconductor element as claimed in claim 1 is characterized in that this surface of this mould has a D structure thing.
3. the manufacture method of semiconductor element as claimed in claim 1, this surface that it is characterized in that this mould is a plane.
4. the manufacture method of semiconductor element as claimed in claim 1, the material that it is characterized in that this colloid is macromolecular material, silica type material, epoxy resin material, phenolic resins class material, acryl class material or photoresistance class material.
5. the manufacture method of semiconductor element as claimed in claim 1, the material that it is characterized in that this adhesion layer is tin indium oxide, tantalum nitride, titanium nitride, nickel, chromium, titanium, tantalum, aluminium, indium, nickel alloy, evanohm, titanium alloy, tantalum alloy, aluminium alloy or indium alloy.
6. the manufacture method of semiconductor element as claimed in claim 1, the thickness that it is characterized in that this adhesion layer is less than 10 μ m.
7. the manufacture method of semiconductor element as claimed in claim 1, the step that it is characterized in that forming this adhesion layer is to utilize vapor deposition method, sputter-deposited method or wireless plating technology.
8. the manufacture method of semiconductor element as claimed in claim 1, the material that it is characterized in that this metal cooling seat is copper, copper alloy, iron/nickel alloy, nickel, aluminium, tungsten, nickel alloy, aluminium alloy or tungsten alloy.
9. the manufacture method of semiconductor element as claimed in claim 1, the thickness that it is characterized in that this metal cooling seat is greater than 10 μ m.
10. the manufacture method of semiconductor element as claimed in claim 1, the step that it is characterized in that forming this metal cooling seat is to utilize plating mode or electroless-plating mode.
11. the manufacture method of semiconductor element as claimed in claim 1 is characterized in that between the step of the step that forms this adhesion layer and this metal cooling seat of formation, comprises at least that also forming a metallic reflector covers on this adhesion layer.
12. the manufacture method of semiconductor element as claimed in claim 11, the thickness that it is characterized in that this metallic reflector is less than 10 μ m.
13. the manufacture method of semiconductor element as claimed in claim 11, the step that it is characterized in that forming this metallic reflector is to utilize vapor deposition method, sputter-deposited method, wireless plating technology or galvanoplastic.
14. the manufacture method of semiconductor element as claimed in claim 11, the material that it is characterized in that this metallic reflector is the alloy of aluminium, silver, gold, copper, rhodium, platinum, chromium, nickel, titanium or above-mentioned metal.
15. the manufacture method of semiconductor element as claimed in claim 1 is characterized in that also comprising at least when pressure is established this semiconductor chip:
At least one circuit board is provided, and wherein this circuit board comprises an insulating barrier and a conductive layer that piles up mutually at least; And
This conductive layer of this circuit board is pressed in another part of being located at this colloid fully, and this insulating layer exposing is gone out, wherein this adhesion layer covers on the expose portion of this insulating barrier of this circuit board.
16. the manufacture method of semiconductor element as claimed in claim 15 is characterized in that after the step that removes this colloid and this mould, comprises at least that also a plurality of leads are set electrically connects this conductive layer and this semiconductor chip.
17. the manufacture method of semiconductor element as claimed in claim 16, it is characterized in that after the step that those leads are set, at least comprise that also forming an adhesive layer covers the expose portion of this semiconductor chip, those leads and this adhesion layer fully, and cover the engaging zones of those leads and this conductive layer.
18. the manufacture method of semiconductor element as claimed in claim 1, it is characterized in that after the step that removes this colloid and this mould, at least comprise also at least one circuit board being set on the part of this adhesion layer that exposes that wherein this circuit board comprises an insulating barrier and a conductive layer that is stacked in regular turn on this adhesion layer at least.
19. the manufacture method of semiconductor element as claimed in claim 18 is characterized in that after the step that this circuit board is set, and comprises at least that also a plurality of leads are set electrically connects this conductive layer and this semiconductor chip.
20. the manufacture method of semiconductor element as claimed in claim 19, it is characterized in that after the step that those leads are set, at least comprise that also forming an adhesive layer covers the expose portion of this semiconductor chip, those leads and this adhesion layer fully, and cover the engaging zones of those leads and this conductive layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2007100083131A CN100533696C (en) | 2007-01-17 | 2007-01-17 | Method for manufacturing semiconductor element |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2007100083131A CN100533696C (en) | 2007-01-17 | 2007-01-17 | Method for manufacturing semiconductor element |
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| CN101226884A CN101226884A (en) | 2008-07-23 |
| CN100533696C true CN100533696C (en) | 2009-08-26 |
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| CNB2007100083131A Expired - Fee Related CN100533696C (en) | 2007-01-17 | 2007-01-17 | Method for manufacturing semiconductor element |
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