CN100527439C - Flash storage structure and its manufacturing method - Google Patents
Flash storage structure and its manufacturing method Download PDFInfo
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- CN100527439C CN100527439C CNB2005101184107A CN200510118410A CN100527439C CN 100527439 C CN100527439 C CN 100527439C CN B2005101184107 A CNB2005101184107 A CN B2005101184107A CN 200510118410 A CN200510118410 A CN 200510118410A CN 100527439 C CN100527439 C CN 100527439C
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- flash memory
- silicon nitride
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- semiconductor substrate
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- 238000003860 storage Methods 0.000 title abstract description 3
- 238000004519 manufacturing process Methods 0.000 title 1
- 238000000034 method Methods 0.000 claims abstract description 9
- 239000000758 substrate Substances 0.000 claims description 66
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 49
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 45
- 229910052710 silicon Inorganic materials 0.000 claims description 43
- 239000010703 silicon Substances 0.000 claims description 43
- 239000004065 semiconductor Substances 0.000 claims description 37
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 23
- 150000003376 silicon Chemical class 0.000 claims description 20
- 238000002360 preparation method Methods 0.000 claims description 18
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 12
- 229920005591 polysilicon Polymers 0.000 claims description 12
- 239000013078 crystal Substances 0.000 claims description 11
- 239000002159 nanocrystal Substances 0.000 claims description 10
- KWYUFKZDYYNOTN-UHFFFAOYSA-M Potassium hydroxide Chemical compound [OH-].[K+] KWYUFKZDYYNOTN-UHFFFAOYSA-M 0.000 claims description 9
- 230000015572 biosynthetic process Effects 0.000 claims description 8
- 238000005530 etching Methods 0.000 claims description 8
- 229910052751 metal Inorganic materials 0.000 claims description 8
- 239000002184 metal Substances 0.000 claims description 8
- 230000008569 process Effects 0.000 claims description 8
- 229910000577 Silicon-germanium Inorganic materials 0.000 claims description 6
- 239000000463 material Substances 0.000 claims description 3
- 229910001092 metal group alloy Inorganic materials 0.000 claims description 3
- 229910021332 silicide Inorganic materials 0.000 claims description 3
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims description 3
- 239000002800 charge carrier Substances 0.000 description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 3
- 230000004888 barrier function Effects 0.000 description 3
- 238000005468 ion implantation Methods 0.000 description 3
- RJCRUVXAWQRZKQ-UHFFFAOYSA-N oxosilicon;silicon Chemical compound [Si].[Si]=O RJCRUVXAWQRZKQ-UHFFFAOYSA-N 0.000 description 3
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 2
- 230000008901 benefit Effects 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 150000004767 nitrides Chemical class 0.000 description 2
- 239000011800 void material Substances 0.000 description 2
- 230000008859 change Effects 0.000 description 1
- 229910017052 cobalt Inorganic materials 0.000 description 1
- 239000010941 cobalt Substances 0.000 description 1
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000001459 lithography Methods 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
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Abstract
A flash storage structure consists of a base plate with V shaped groove, the first doped region set in base plate, two second doped region set at two sides of said V shaped groove in base plate, a dielectric stacked structure being set on surface of base plate and being set with multiple catch position, and a conductive layer set at surface of dielectric stacked structure above said V shaped groove. The method for preparing said V shaped groove is also disclosed.
Description
Technical field
The present invention relates to a kind of flash memory structure and preparation method thereof, particularly a kind of flash memory structure and preparation method thereof with V-type cross section.
Background technology
Flash memory has been widely used on the data storing of electronic products such as mobile computer, electronic organizers, mobile phone, digital camera, digital recording pen and MP3 player owing to have low power consumption, access rapidly and the data that deposit in advantage such as also can not disappear after outage.A kind of typical flash memory has silicon-silica-silicon-nitride and silicon oxide-silicon (SONOS) structure, and it has thin memory cell and makes advantages such as easy, thereby has been widely used among the flash memory.
Fig. 1 illustration one existing SONOS (silicon-silica-silicon-nitride and silicon oxide-silicon) type flash memory cells 10.This flash memory 10 comprises a silicon substrate 12, two doped regions 14 and 16, one tunnel oxide 22, a silicon nitride layer 24, an oxide layer 26 and a polysilicon layer 28, and wherein this tunnel oxide 22, this silicon nitride layer 24 and this oxide layer 26 constitute silicon monoxide-silicon-nitride and silicon oxide (ONO) dielectric stack structure 20.This nitride layer 24 can be caught electronics or the hole of passing this tunnel oxide 22.This oxide layer 26 is in order to avoid memory during writing or erasing, and electronics or hole break away from this nitride layer 24 and enter this polysilicon layer 28.
When this polysilicon layer 28 (as grid) during by positive charge, the electronics in this silicon substrate 12 can be injected among this silicon nitride layer 24.On the contrary, when this polysilicon layer 28 is charged by negative sense, the portions of electronics in this silicon nitride layer 24 can be ostracised and inject this silicon substrate 12 and in this silicon nitride layer 24 in the formation hole.Sink into the limit voltage that electronics in this silicon nitride layer 24 and hole change this flash memory cells 10, and different limit voltages is represented this flash memory cells 10 storage data position " 0 " or " 1 ".
Summary of the invention
Main purpose of the present invention provides a kind of flash memory structure with V-type cross section and preparation method thereof, and its structure has higher density of memory cells and its technology has preferable ladder coverage property.
For reaching above-mentioned purpose, the present invention discloses a kind of flash memory structure and preparation method thereof.This flash memory structure comprises the conductive layer that dielectric stack structure and on the inclined-plane of second doped region in first doped region that a semiconductor substrate, with a V-type groove is arranged at the below of V-type groove in this semiconductor substrate, two semiconductor substrates that are arranged at these V-type groove both sides, at least one V-type groove that is arranged at this semiconductor substrate is arranged at the dielectric stack body structure surface of this V-type groove top.This semiconductor substrate can be silicon substrate, and the inclined-plane of this V-type groove is positioned at (111) crystal plane of this silicon substrate.This dielectric stack structure comprises a plurality of charge carrier catching positions (trapping sites) and is folded in wherein.
This dielectric stack structure example is as being that the silicon nitride layer and that first oxide layer, that is arranged at this semiconductor substrate surface is arranged at this first oxide layer surface is arranged at second oxide layer on this silicon nitride layer surface, or comprises that more a polysilicon layer is folded in the middle of the silicon nitride layer with as catching position.Moreover, this dielectric stack structure also can comprise silicon nitride layer, a plurality of nanocrystal and that is formed at this silicon nitride layer surface that first oxide layer, that is arranged at this semiconductor substrate surface is arranged at this first oxide layer surface and be arranged at second oxide layer on this silicon nitride layer, wherein nanocrystal is as the charge carrier catching position, and its material can be silicon, germanium silicide, metal, metal alloy or metal silicide etc.
The preparation method of this flash memory comprise form one first doped region in the semiconductor substrate, form a V-type groove in the semiconductor substrate of this first doped region top, form two second doped regions in the semiconductor substrate of these V-type groove both sides, form a dielectric stack structure on the V-type groove of this semiconductor substrate surface and form the steps such as dielectric stack body structure surface of a conductive layer in this V-type groove top, wherein the dielectric stack structure has a plurality of catching positions and is folded in wherein.The formation step of this V-type groove comprises formation one screen and is opened in this screen, carries out an etch process in this semiconductor substrate surface, formation one, and the semiconductor substrate of this opening below of its etching is to form this V-type groove and to remove this screen.Preferably, this screen is an oxide layer, and the etching solution that this etch process uses comprises potassium hydroxide.This semiconductor substrate can be silicon substrate, and (100) crystal plane of this silicon substrate is towards the below, and the inclined-plane of this V-type groove is positioned at (111) crystal plane of this silicon substrate.
Compared to existing skill, flash memory structure of the present invention has higher density of memory cells and its technology has preferable ladder coverage property.Flash memory structure of the present invention has the flash memory cells of two shared grids and drain electrode, and carrier channels and capture region distribute be not adopt existing horizontal design and with the inclination mode be arranged at respectively in this semiconductor substrate with this semiconductor substrate on the dielectric stack structure in, the therefore density of memory cells of flash memory structure of the present invention in can the unit's of lifting silicon area.In addition, because the upper opening of this V-type groove is greater than its bottom, so the present invention has preferable ladder coverage property when preparing this dielectric stack structure and this conductive layer by deposition technique, and can not form interior void.
Description of drawings
Fig. 1 illustration one existing SONOS type flash memory cells;
The preparation method of Fig. 2 to Fig. 7 illustration flash memory structure of the present invention;
Fig. 8 is the schematic perspective view of flash memory structure of the present invention;
Fig. 9 illustration is utilized the NOR type flash memory of flash memory structure design of the present invention;
The flash memory structure of Figure 10 illustration another embodiment of the present invention; And
The flash memory structure of Figure 11 illustration another embodiment of the present invention;
Description of reference numerals
10 flash memory cells, 12 silicon substrates
14 doped regions, 16 doped regions
18 carrier channels, 20 dielectric stack structures
22 tunnel oxides, 24 silicon nitride layers
26 oxide layers, 28 polysilicon layers
50 flash memory structures, 52 silicon substrates
54 first doped regions, 56 screens
58 openings, 60 V-type grooves
62 inclined-planes, 64 carrier channels
66 charge carrier capture areas, 72 second doped regions
74 second doped regions 76 the 3rd doped region
78 conductive layers, 80 dielectric stack structures
82 first oxide layers, 84 silicon nitride layers
86 second oxide layers, 88 insulating barriers
90 dielectric stack structures, 92 first oxide layers
94 first silicon nitride layers, 96 silicon-containing layers
98 second silicon nitride layers, 100 second oxide layers
110 flash memory structures, 120 dielectric stack structures
122 oxide layers, 124 silicon nitride layers
126 cover layers, 128 nanocrystals
130 flash memory structures
Embodiment
The preparation method of Fig. 2 to Fig. 7 illustration flash memory structure 50 of the present invention.At first, carry out a n+ ion implantation technology to form one first doped region 54 in a silicon substrate 52, it injects energy preferably between 20 to 30 electron-volts (keV), about 1600 to 2000 dusts (angstrom) of the degree of depth.Afterwards, form a screen 56, utilize lithography process to form an opening 58 among this screen 56, as shown in Figure 3 again in these silicon substrate 52 surfaces.(100) crystal plane of this silicon substrate 52 is towards the below, and this screen 56 one silica layer preferably.
With reference to figure 4, carry out an etch process, the silicon substrate 52 of these opening 58 belows of etching is removed this screen 56 again to form a V-type groove 60.The spy's, the etching solution that this etch process uses comprises potassium hydroxide, and the inclined-plane 62 of this V-type groove 60 is positioned on (111) crystal plane of this silicon substrate 52.Because this etching solution etch-rate to (100) crystal plane of this silicon substrate 52 in the time of 80 ℃ is 0.6 micron/minute, etch-rate to (111) crystal plane is 0.006 micron/minute, therefore this etch process is direction interdependent (orientation-independent) etching, can independently form the V-type groove 60 on (111) crystal plane that this inclined-plane 62 is positioned at this silicon substrate 52.
Be arranged between two second doped regions in the semiconductor substrate with this V-type groove below
With reference to figure 5 (a), carry out a n
+Ion implantation technology is to form two second doped regions 72 and 74 in the silicon substrate 52 of these V-type groove 60 both sides.Preferably, the present invention also can utilize n
+Or n
-Ion implantation technology optionally forms one the 3rd doped region 76 in these first doped region, 54 tops, these V-type groove 60 belows and this second doped region 72 and 74 s' silicon substrate 52, in order to guiding induced current (induced current), shown in Fig. 5 (b).Profess it, this first doped region 54 is as transistor drain, and this second doped region 72,74 is as source electrode.
With reference to figure 6, form in regular turn one first oxide layer 82 in these silicon substrate 52 surfaces, form a silicon nitride layer 84 in the surface of this first oxide layer 82 and form one second oxide layer 86 in the surface of this silicon nitride layer 84, so can form a dielectric stack structure 80 in the surface of this silicon substrate 52.Afterwards, form a conductive layer 78 that constitutes by polysilicon, promptly finish SONOS type flash memory structure 50 in the surface of the dielectric stack structure 80 of these V-type groove 60 tops.Profess it, this flash memory structure 50 comprises the charge carrier capture area 66 of 62 tops, two inclined-planes that are positioned at groove 60.That is this flash memory structure 50 has a plurality of catching positions, is arranged at respectively in the silicon nitride layer 84 of the dielectric stack structure 80 on the inclined-plane 62 of this V-type groove 60.
Fig. 8 is the schematic perspective view of this flash memory structure 50, and some of silicon substrates 52 are hollowed out so that structure is easier to be understood at this, and this hollow structure is not the structure that produces according to the present invention.Fig. 9 illustration is utilized the NOR type flash memory of these flash memory structure 50 designs.The flash memory structure 50 that Fig. 8 shows comprises two silicon-silica-silicon-nitride and silicon oxide-silicon (SONOS) type flash memory cells, the dashed region of its corresponding diagram 9.Two SONOS type flash memory cells are shared drain electrode (i.e. this first doped region 54) and grid (i.e. this conductive layer 78), and the carrier channels of the two is arranged at the below on two inclined-planes 62 of this V-type groove 60 respectively in the inclination mode.Profess it, the flash memory structure 50 of Fig. 8 is the circuit connecting mode of NOR type flash memory corresponding shown in Figure 9 directly.Bit line 1 is connected to this second doped region 74, and bit line 2 is connected to this second doped region 72, and wherein two second doped regions 74 and 72 are respectively as the source electrode of two SONOS type flash memory cells.Contact wire penetrates an insulating barrier 88 and is connected in this first doped region 54 (drain electrode links to each other), and an end of this contact wire is connected to a drain contact at last.
Compared to existing skill, the flash memory structure of present embodiment has higher density of memory cells (doubling approximately) and its technology has preferable ladder coverage property.The flash memory structure of present embodiment has the SONOS type flash memory cells of two shared grids and drain electrode, and the carrier channels of flash memory cells and capture region distribute be not adopt existing horizontal design and with the inclination mode be arranged at respectively among this silicon substrate with this silicon substrate on the interface stacked structure among, so the density of memory cells of the flash memory structure of present embodiment in can the unit's of lifting silicon area.In addition, because the upper opening of this V-type groove is greater than its bottom, therefore have preferable ladder coverage property when the present invention prepares this dielectric stack structure and this polysilicon conducting layers by deposition technique, especially when the deposit multilayer structure, and can not form interior void.
In addition, though flash memory structure of the present invention is embodiment with SONOS type flash memory structure, be not limited to this.The flash memory structure 110 of Figure 10 illustration another embodiment of the present invention, it has a dielectric stack structure 90.The preparation method of this dielectric stack structure 90 can be and forms one first oxide layer 92, one first silicon nitride layer 94, a polysilicon layer 96 (or germanium silicide layer), one second silicon nitride layer 98 and one second oxide layer 100 in regular turn, wherein this polysilicon layer 96 is as capture region, and this first oxide layer 92 is formed at the surface of this semiconductor substrate 52.
The flash memory structure 130 of Figure 11 illustration another embodiment of the present invention, it has one and can be the dielectric stack structure 120 that is gripped with a plurality of catching positions in insulating barrier.The preparation method of this dielectric stack structure 120 can be and forms an oxide layer 122, a silicon nitride layer 124, a plurality of nanocrystal 128 and a cover layer 126 in regular turn.In addition, this cover layer 126 can be an oxide layer or silicon nitride layer gives, and the material of this nanocrystal 128 can be silicon, germanium silicide, metal, metal alloy or metal silicide, and wherein metal for example is low resistance metals such as cobalt, nickel, tungsten.
Technology contents of the present invention and technical characterstic disclose as above, yet those skilled in the art still may be based on teaching of the present invention and announcements and done all replacement and modifications that does not deviate from spirit of the present invention.Therefore, protection scope of the present invention should be not limited to those disclosed embodiments, and should comprise various do not deviate from replacement of the present invention and modifications, and is contained by appended claims.
Claims (18)
1. flash memory structure comprises:
The semiconductor substrate has a V-type groove;
One first doped region is provided with in the semiconductor substrate of this V-type groove below at least;
Two second doped regions are arranged in the semiconductor substrate of these V-type groove both sides and by this V-type groove and separate;
One dielectric stack structure, it has a plurality of catching positions, and is arranged at the V-type groove surfaces of this semiconductor substrate at least; And
One conductive layer is arranged at the dielectric stack body structure surface of this V-type groove top.
2. according to the flash memory structure of claim 1, wherein this dielectric stack structure comprises:
One first oxide layer is arranged at this semiconductor substrate surface;
One silicon nitride layer is arranged at this first oxide layer surface, and wherein these a plurality of catching positions are arranged among this silicon nitride layer; And
One second oxide layer is arranged at this silicon nitride layer surface.
3. according to the flash memory structure of claim 1, wherein this dielectric stack structure comprises:
One first oxide layer is arranged at this semiconductor substrate surface;
One first silicon nitride layer is arranged at this first oxide layer surface;
One silicon-containing layer is arranged at this first silicon nitride layer surface, and wherein this silicon-containing layer is polysilicon layer or germanium silicide layer, and these a plurality of catching positions are arranged among this silicon-containing layer;
One second silicon nitride layer is arranged at this silicon-containing layer surface; And
One second oxide layer is arranged at this second silicon nitride layer surface.
4. according to the flash memory structure of claim 1, wherein this dielectric stack structure comprises:
One oxide layer is arranged at this semiconductor substrate surface;
One silicon nitride layer is arranged at this oxide layer surface;
A plurality of nanocrystals are arranged at this silicon nitride layer surface, and wherein these a plurality of catching positions are made of these a plurality of nanocrystals; And
One cover layer, it covers this nanocrystal and this silicon nitride layer, and wherein this cover layer is oxide layer or silicon nitride layer.
5. according to the flash memory structure of claim 4, wherein the material of this nanocrystal is silicon, germanium silicide, metal, metal alloy or metal silicide.
6. according to the flash memory structure of claim 1, wherein this semiconductor substrate is a silicon substrate, and this V-type groove has (111) crystal plane that an inclined-plane is positioned at this silicon substrate.
7. according to the flash memory structure of claim 1, wherein this first doped region is drain electrode.
8. according to the flash memory structure of claim 1, wherein this second doped region is a source electrode.
9. according to the flash memory structure of claim 1, wherein this conductive layer is a grid.
10. according to the flash memory structure of claim 1, it comprises one the 3rd doped region in addition, is arranged between two second doped regions in the semiconductor substrate with this V-type groove below.
11. the preparation method of a flash memory comprises the following step:
Form one first doped region in the semiconductor substrate;
Form a V-type groove in the semiconductor substrate of this first doped region top;
Form two second doped regions in the semiconductor substrate of these V-type groove both sides, described two second doped regions are separated by this V-type groove;
Form one and have the V-type groove surfaces of the dielectric stack structure of a plurality of catching positions in this semiconductor substrate; And
Form the dielectric stack body structure surface of a conductive layer in this V-type groove top.
12. according to the preparation method of the flash memory of claim 11, wherein the formation of this V-type groove comprises the following step:
Form a screen in this semiconductor substrate surface;
Forming one is opened in this screen;
Carry out an etch process, the semiconductor substrate of this opening below of etching is to form this V-type groove; And
Remove this screen.
13. according to the preparation method of the flash memory of claim 12, wherein the etching solution that uses of this etch process comprises potassium hydroxide.
14. according to the preparation method of the flash memory of claim 12, wherein this semiconductor substrate is a silicon substrate, this V-type groove has (111) crystal plane that an inclined-plane is positioned at this silicon substrate, and (100) crystal plane of this silicon substrate is towards the below.
15. according to the preparation method of the flash memory of claim 12, wherein this screen is an oxide layer.
16. according to the preparation method of the flash memory of claim 11, wherein the formation of this dielectric stack structure comprises the following step:
Form one first oxide layer in this semiconductor substrate surface;
Form a silicon nitride layer in this first oxide layer surface; And
Form one second oxide layer in this silicon nitride layer surface.
17. according to the preparation method of the flash memory of claim 11, wherein the formation of this dielectric stack structure comprises the following step:
Form one first oxide layer in this semiconductor substrate surface;
Form one first silicon nitride layer in this first oxide layer surface;
Form a silicon-containing layer in this first silicon nitride layer surface, wherein this silicon-containing layer is polysilicon layer or germanium silicide layer;
Form one second silicon nitride layer in this silicon-containing layer surface; And
Form one second oxide layer in this second silicon nitride layer surface.
18. root is according to the preparation method of the flash memory of claim 11, wherein the formation of this dielectric stack structure comprises the following step:
Form an oxide layer in this semiconductor substrate surface;
Form a silicon nitride layer in this oxide layer surface;
Form a plurality of nanocrystals in this silicon nitride layer surface; And
Form a cover layer on this silicon nitride layer, wherein this cover layer is oxide layer or silicon nitride layer.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2005101184107A CN100527439C (en) | 2005-10-28 | 2005-10-28 | Flash storage structure and its manufacturing method |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2005101184107A CN100527439C (en) | 2005-10-28 | 2005-10-28 | Flash storage structure and its manufacturing method |
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| CN100527439C true CN100527439C (en) | 2009-08-12 |
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| US8138049B2 (en) | 2009-05-29 | 2012-03-20 | Silergy Technology | Fabrication of lateral double-diffused metal oxide semiconductor (LDMOS) devices |
| CN110517948B (en) * | 2019-07-26 | 2021-12-21 | 中国科学院微电子研究所 | Method for extending InP semiconductor on silicon substrate and semiconductor device manufactured by same |
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