CN100512061C - Device using time slot add-drop method to monitor mixed speed image, voice and data - Google Patents
Device using time slot add-drop method to monitor mixed speed image, voice and data Download PDFInfo
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Abstract
This invention discloses a device for monitoring velocity mixed images, phones and data including two time slot current transmission modules connected with each other at work and realizing mixed velocity transmission of data, video an audio, an image coding module with a phone code-decode device transmitting the compressed coded image and phone signals to the monitor center by said module and decoding the outbound compressed digit phones from the monitor center to output the analog audio signals and an image decode module with a phonetic code-decode device converting the digital images and phonetic decodes transferred to the center by the code module to analog signals output, coding the analog phonetic signals of the center, downing the coded data to an image code module of the terminal office thus realizing multifunction realtime monitor when transmission resources are busy.
Description
Technical field
The present invention relates to a kind of image, voice and data slot add-drop and put, relate in particular to a kind of device that adopts time slot add-drop method to mix fast image, voice and data monitoring.
Background technology
The transfer resource of mobile base station is comparatively nervous, and general BTS only possesses 1～2 pair of E1 transmission line, and supervisory control system in the past can only provide data monitoring, does not have image and voice monitoring function.(promptly an end carries out the encoding and decoding of the coding and the voice of data acquisition, image to the point-to-point networking mode of the many employings of traditional remote image monitoring system, the other end carries out data extract, picture decoding and encoding and decoding speech), speed is all fixed in the time of the image transmission, can't be implemented in the wire rate adjustment, and can't realize that the high, low speed image mixes the speed transmission.This networking mode is very dumb, the equipment cost height, transmission resource waste is comparatively serious, be difficult to adapt to the transfer resource anxiety and the user requires image, voice monitoring than higher occasion (as requiring to upload simultaneously the image of a plurality of end office (EO)s in base station monitoring, the monitoring of wireless office in same E1 circuit, and can be online the image of certain end office (EO) of high-speed transfer) to image rate.
Summary of the invention
The objective of the invention is in order to have overcome as above shortcoming of the prior art, a kind of device that adopts time slot add-drop method to mix fast image, voice and data monitoring is provided, during this device composition system as required each end office (EO) dynamically take transmission time slot, it can be with each picture signal dynamically with at a high speed or low speed transmissions.
For achieving the above object, a kind of employing time slot add-drop method of the present invention mixes fast image, the device of voice and data monitoring, when being included in operating state, it is connected with each other, realize data, video, audio frequency mixes two time interval insertion transport modules of speed transmission, and one end link to each other with a described time interval insertion transport module, with image, Speech Signal Compression coding back reaches Surveillance center by the time interval insertion transport module, the compressed digital voice that also Surveillance center passed are down decoded simultaneously, the image coding module that contains audio coder ﹠ decoder (codec) of output simulated audio signal, and one end link to each other with described another piece time interval insertion transport module, image coding module is reached the digital picture of Surveillance center, tone decoding is converted to analog signal output, the analog voice signal of Surveillance center is encoded, the picture decoding module that contains audio coder ﹠ decoder (codec) of the image coding module of the data behind the coding by reaching end office (EO) under the time interval insertion transport module, described two time interval insertion transport modules comprise two-way E1 interface circuit connected to one another, the Time Slot Switching Circuit that is connected with described two-way E1 interface circuit, the High level data link control processor that is connected with Time Slot Switching Circuit and second logical circuit, the central processing unit that is connected with second logical circuit, UART Universal Asynchronous Receiver Transmitter that is connected with central processing unit and serial electric erasable programmable memory device, the digital PLL circuit that is connected with one road E1 interface circuit, first logical circuit that one end is connected with digital PLL circuit, the various clocks of described logical device 1 output are given Time Slot Switching Circuit, the E1 interface circuit, the High level data link control processor circuit, the UART Universal Asynchronous Receiver Transmitter circuit, the image encoding plate that image coding module is included, the included picture decoding plate of picture decoding module provides work clock, described UART Universal Asynchronous Receiver Transmitter is connected with the configuration order that a configuration serial ports is used to receive the PC webmaster, or to PC webmaster transmission return command, described central processing unit is connected with an image encoding plate or picture decoding board communications and is used for system operational parameters is transmitted so that On-line Control whole system image operating rate and finishing resets to image encoding plate or the relevant of picture decoding plate to image encoding plate or picture decoding plate with serial ports, the transmission of control commands such as switching, described second logical circuit are connected with three transparent serial ports and are used for to the transparent transmitting-receiving of the remote data that has serial equipment that links to each other with the time interval insertion transport module.
Described image coding module comprises the image encoder of receiver, video input signal, one end is connected the logic control circuit that the other end is connected with time interval insertion transport module first logical circuit by the special-purpose gang socket of the image module of time interval insertion transport module with the X21 interface with image encoder, one end is connected the other end and is connected with time interval insertion transport module central processing unit by the special-purpose gang socket of the image module of time interval insertion transport module with logic control circuit, when work, utilize communication serial port to realize the data processor of message mutually, the audio coder ﹠ decoder (codec) that the special-purpose gang socket of image module by the time interval insertion transport module is connected with second logical circuit of time interval insertion transport module, the described socket that is connected with first logical circuit will send to image coding module from the clock signal of time interval insertion transport module first logical circuit and receive simultaneously from image coding module processed video encoding stream, the described socket that is connected with second logical circuit will send to audio coder ﹠ decoder (codec) in the mode of high speed data lines from the speech message of Surveillance center, receive from the voice of this audio coder ﹠ decoder (codec) simultaneously and utilize the logic control circuit of time interval insertion transmission veneer to handle it to send to Surveillance center by the E1 interface after the back exchanges to predetermined time slot by switching network.
Described picture decoding module comprises the image decoder of receiver, video output signal, one end is connected the logic control circuit that the other end is connected with time interval insertion transport module first logical circuit by the special-purpose gang socket of the image module of time interval insertion transport module by the X21 interface with image decoder, one end is connected the other end and is connected with time interval insertion transport module central processing unit by the special-purpose gang socket of the image module of time interval insertion transport module with logic control circuit, when work, utilize communication serial port to realize the data processor of message mutually, the audio coder ﹠ decoder (codec) that the special-purpose gang socket of image module by the time interval insertion transport module is connected with second logical circuit of time interval insertion transport module, the described socket that is connected with first logical circuit will send to the picture decoding module from the clock signal of time interval insertion module first logical circuit simultaneously will delivering to the picture decoding module from far-end image coding module processed video stream and carry out picture decoding by E1 circuit transmission, the described gang socket that is connected with second logical circuit will send to audio coder ﹠ decoder (codec) in the mode of HW from the speech message of distant station, receive from the voice of this audio coder ﹠ decoder (codec) simultaneously and utilize the logic control circuit of this veneer to handle it to send to distant station by the E1 interface after the back exchanges to predetermined time slot by switching network.
Described first logical circuit is the erasable programmable device, and described second logical circuit is the erasable programmable device.The described transparent serial ports that is connected with second logical circuit is parallel serial ports.
Adopt the method for the invention and device, compared with prior art, can realize image, the voice of the occasion of transfer resource anxiety, the multi-functional real-time monitoring of data, and on same E1 circuit, transmit the image of a plurality of different rates simultaneously, make full use of the available resources in the transmission channel, reach the effect of flexible networking, saved valuable transfer resource.
Purpose of the present invention, feature and advantage will be in conjunction with the embodiments, are described further with reference to accompanying drawing.
Description of drawings
Fig. 1 is the theory diagram of image coding module of the present invention;
Fig. 2 is the theory diagram of picture decoding module of the present invention;
Fig. 3 is a time interval insertion transport module theory diagram of the present invention;
Fig. 4 is that branch of the present invention is inserted schematic diagram;
Fig. 5 is the point-to-point networking mode 1 that the present invention adopts the E1 special line;
Fig. 6 is the point-to-point networking mode 2 that the present invention adopts the E1 special line;
Fig. 7 is the networking mode that the present invention adopts 1 point-to-multipoint of E1 special line;
Fig. 8 is the point-to-point networking mode that the present invention adopts time interval insertion;
Fig. 9 is the networking mode that the present invention adopts 1 point-to-multipoint of time interval insertion;
Figure 10 is the multi-multipoint dynamic image speed networking mode that the present invention adopts the E1 special line.
Embodiment
With reference to Fig. 1, a kind of employing time slot add-drop method of the present invention mixes fast image, the image coding module of the device of voice and data monitoring comprises the image encoder of receiver, video input signal, one end is connected the logic control circuit that the other end is connected with time interval insertion transport module first logical circuit by the special-purpose gang socket of the image module of time interval insertion transport module with the X21 interface with image encoder, one end is connected the other end and is connected with time interval insertion transport module central processing unit by the special-purpose gang socket of the image module of time interval insertion transport module with logic control circuit, when work, utilize communication serial port to realize the data processor of message mutually, the audio coder ﹠ decoder (codec) that the special-purpose gang socket of image module by the time interval insertion transport module is connected with second logical circuit of time interval insertion transport module, the described socket that is connected with first logical circuit will be from the 4MHZ of time interval insertion transport module first logical circuit, the clock signal of 8KHZ sends to image coding module and receives simultaneously from image coding module according to the video encode stream after the format analysis processing H.261, the described socket that is connected with second logical circuit will be from the speech message of Surveillance center with high speed data lines (Highway, HW) mode sends to audio coder ﹠ decoder (codec), receives from the voice of this audio coder ﹠ decoder (codec) of same unit simultaneously and utilize the logic control circuit of time interval insertion transmission veneer to handle it to send to Surveillance center by the E1 interface after the back exchanges to predetermined time slot by switching network.Image coding module reaches image, Speech Signal Compression coding back Surveillance center, also the compressed digital voice that pass under the Surveillance center is decoded simultaneously by the time interval insertion transport module, the output simulated audio signal.The encoding and decoding speech part all realizes with hardware, adopts exchanger user circuit interface CODEC chip, and pcm interface is provided, and takies 1 time slot of corresponding HW line (HWAI, HWAO); Image section adopts the VP family chip of MITEL company to finish the encoding compression of image, and X.21 interface is provided, and realizes X.21 interface to the conversion of pcm interface with hardware, take corresponding HW line (one, the time slot of 1-26 HWVO).Consider in use have reset, operation such as coding parameter adjustment, this module also provides serial line interface that the singlechip CPU in the coding module is linked to each other with the singlechip CPU of time interval insertion veneer by special-purpose 40PIN socket, directly communicates.With the cooperative time interval insertion transport module of image encoding veneer will be by special use the image that sends from image encoding veneer image coding circuit and encoding and decoding speech circuit of 40PIN socket, speech data and the exchange be scheduled at switching network synchronously of the monitor data of sending here from other collecting units of scene that transparent serial ports is received and the logic control circuit 2 of HDLC control data on time interval insertion transport module veneer, each data is exchanged to same above the HW according to the requirement that sets in advance, send on the E1 circuit by the E1 interface circuit then.
Fig. 2 is the theory diagram of picture decoding module of the present invention, described image coding module comprises the image decoder of receiver, video output signal, one end is connected the logic control circuit that the other end is connected with time interval insertion transport module first logical circuit by the special-purpose gang socket of the image module of time interval insertion transport module by the X21 interface with image decoder, one end is connected the other end and is connected with time interval insertion transport module central processing unit by the special-purpose gang socket of the image module of time interval insertion transport module with logic control circuit, when work, utilize communication serial port to realize the data processor of message mutually, the audio coder ﹠ decoder (codec) that the special-purpose gang socket of image module by the time interval insertion transport module is connected with second logical circuit of time interval insertion transport module, the described socket that is connected with first logical circuit will be from the 4MHZ of time interval insertion module first logical circuit, what the clock signal of 8KHz sent to that the picture decoding module simultaneously will be by E1 circuit transmission carries out picture decoding according to the dynamic image distribution after the format analysis processing H.261 to the picture decoding module from the far-end image coding module, the described gang socket that is connected with second logical circuit will send to audio coder ﹠ decoder (codec) in the mode of HW from the speech message of distant station, receive from the voice of this audio coder ﹠ decoder (codec) simultaneously and utilize the logic control circuit of this veneer to handle it to send to distant station by the E1 interface after the back exchanges to predetermined time slot by switching network.
The picture decoding module is converted to analog signal output with digital picture, the tone decoding that image coding module reaches Surveillance center, the analog voice signal of Surveillance center is encoded, and the data behind the coding are by reaching the image coding module of end office (EO) under the time interval insertion transport module.The picture decoding module is divided into picture decoding and encoding and decoding speech two parts.The encoding and decoding speech part all realizes with hardware, and pcm interface is provided, and takies 1 time slot of corresponding HW line (HWAI, HWAO); Image section adopts the VP family chip of MITEL company to finish the decoding compressed of image, and X.21 interface is provided, and realizes X.21 interface to the conversion of pcm interface with hardware, take corresponding HW line (one, 26 time slots HWVO).Considering in use has operation such as reset, and this module also provides serial ports that the singlechip CPU in the decoder module is linked to each other with the singlechip CPU of time interval insertion veneer by special-purpose 40PIN socket, directly communicates.The time interval insertion transport module veneer of working together with the picture decoding veneer will by the E1 circuit transmit from the far-end image encoded, voice, monitor data, the HDLC control data receives by the E1 interface, be converted to the HW signal, the exchange of being scheduled at switching network again, will be from the exchanges data of the different time-gap of the HW on the E1 interface different HW to the time interval insertion transport module veneer, these different HW are connected to the logic control circuit 2 on the time interval insertion transport module veneer except that the HDLC data, through after the logical process, image, speech data sends to picture decoding module veneer image decoding circuit with the form of the HW 40PIN socket by special use and the encoding and decoding speech circuit is handled; Monitor data is exported by the corresponding transparent serial ports on the time interval insertion transport module veneer in the mode of serial; HDLC data HW directly delivers on the time interval insertion transport module veneer high-level data link agreement processor controls and handles.
The main chip of table 1 image coding and decoding module
| Numbering | Title | Specifications and | Company | |
| 1 | The PHILIPS video encoder | SAA7185WP | PHILIPS | |
| 2 | Video format converter | VP520SA/VP520SCG | MITEL | |
| 3 | The video demodulation multiplexer | VP2614CG | MITEL | |
| 4 | H.261, paster touches a yard device | VP2615CG | MITEL | |
| 5 | The paster codec | TP3067WM | ST | |
| 6 | Monolithic processor | P89C51UBPN//AT89C51-20PC | ATEML | |
| 7 | Paster is encoder H.261 | VP2611 | MITEL | |
| 8 | Video multiplexer | VP2612CG | MITEL | |
| 9 | The PHILIPS Video Decoder | SAA7111WP | PHILIPS |
Fig. 3 is a time interval insertion transport module theory diagram of the present invention, and Fig. 4 is that branch of the present invention is inserted schematic diagram,
The time interval insertion module by a special block power supply plate finish-48 direct currents to+5V ,-conversion of 5V, 12V, wherein+5V ,-the 5V power supply supplies with included image encoding plate or the included picture decoding plate of picture decoding module of image coding module; The 12V power supply is given the fan power supply of image encoding unit or picture decoding unit; The time interval insertion module is only from power panel extraction+5V power supply, and veneer PCB has designed special bus plane and stratum during design, becomes the 3.3V power supply by LDO voltage adjuster general+5V power source conversion, is to isolate mutually simultaneously between the power supply of transparent serial ports 0/1/2.Therefore the design of the PCB one-board power supply layer of time interval insertion module and stratum the time, that carries out on bus plane and stratum specially cuts apart, and each components and parts of time interval insertion module extract the power supply of oneself needs separately from bus plane like this.
Digital PLL circuit will shake synchronously from the E1 circuit 0.5K clock that the E1 line interface extracts is phase-locked, produce the clock signal of 4M, 2M, 8KHZ and enter Erasable Programmable Logic Device 1.After the operations such as Erasable Programmable Logic Device 1 will carry out synchronously from the clock of 4M, the 2M of digital PLL circuit, 8KHZ, frequency division, displacement, export various clocks and work clock is provided for Time Slot Switching Circuit, E1 interface circuit, High level data link control processor circuit, UART Universal Asynchronous Receiver Transmitter circuit, image encoding plate, picture decoding plate.Wherein time interval insertion transmission veneer links to each other for clock that image encoding plate, picture decoding plate the provide X11 socket by time interval insertion transmission veneer and finishes the transmission of signal with image encoding plate, picture decoding plate.
Central processing unit is sent out all and can be read the various configuration informations that are stored in the serial electric erasable programmable memory device by P1.6, two pin Simulation with I of P1.7 2C bus of central processing unit when time interval insertion transmission Board Power up initialization and operate as normal, and central processing unit can be by the P1.6 of central processing unit, the relevant position that two pin Simulation with I of P1.7 2C bus is stored in new configuration information the serial electric erasable programmable memory device when the network management configuration order of receiving from PC.
When the initialization of time interval insertion transmission Board Power up, central processing unit can send transparent serial ports gating signal by the I/O pin of multiplexing address data bus by Erasable Programmable Logic Device 2, so that transparent serial ports 0/1/2 can operate as normal; Transparent serial ports 0/1/2 directly links to each other with the equipment that has serial ports of outside with the X14/X15/X16 socket on the time interval insertion transmission veneer, aliunde serial data received into deliver to Erasable Programmable Logic Device 2 and carry out producing after the Synchronous Processing data flow that meets E1 circuit form, Erasable Programmable Logic Device 2 data flow that will the meet E1 circuit form STI6 pin of delivering to Time Slot Switching Circuit carries out time gas exchange then, delivers to two-way E1 interface respectively by STO0/STO1 and sends to the E1 circuit and receive for the other side.The E1 signal that while two-way E1 interface receives links to each other with the STI0/STI1 of switched circuit, to exchange to the STO6 of switched circuit by the signal the inside that the E1 interface circuit receives from the transparent rs 232 serial interface signal of opposite end by time gas exchange, STO6 directly links to each other with the I/O pin of Erasable Programmable Logic Device 2, the serial data that Erasable Programmable Logic Device 2 is sent switched circuit here separates, and delivers to transparent serial ports 0/1/2 by the I/O pin of self respectively; Transparent serial ports 0/1/2 is given the serial data that receives the equipment that has serial ports of the outside that links to each other with the X14/X15/X16 socket by the X14/X15/X16 socket on the time interval insertion transmission veneer again.By top process, transparent serial ports 0/1/2 is finished the transparent transmitting-receiving to the remote data of the equipment that has serial ports of the outside that links to each other with the X14/X15/X16 socket.
The configuration serial ports that data is sent to the time interval insertion transmission from the network management configuration order of the PC serial port by PC enters the UART Universal Asynchronous Receiver Transmitter on the time interval insertion transmission veneer, when UART Universal Asynchronous Receiver Transmitter is received a frame complete signal, can send and interrupt application to central processing unit, central processing unit will change Interrupt Process over to this moment, read UART Universal Asynchronous Receiver Transmitter and receive the data of buffering area and analyze, carry out this order; Simultaneously return command is write UART Universal Asynchronous Receiver Transmitter and send buffering area, UART Universal Asynchronous Receiver Transmitter will be with this return command by disposing the webmaster that serial ports sends to PC, to confirm normally to receive order and the execution from webmaster.If in the process of carrying out, be image plate (described image encoding plate and picture decoding plate are referred to as image plate) with the same unit of time interval insertion module from the operand of the network management configuration order of PC, the TXD pin of this order by processor will be sent to image plate so, image plate receive orders and carry out after confirmation is returned to the time interval insertion module, finish reception by the RXD pin of the central processing unit of time interval insertion module.Wherein all signals of time interval insertion module all are that socket X11 by 40PIN links to each other with image plate by the band line and finishes the transmission of signal.And if be the time interval insertion module of opposite end or the image plate of opposite end from the operand of the network management configuration order of PC, central processing unit writes this order the transmission buffering area of High level data link control processor circuit so, the STI2/STI3 that the High level data link control processor circuit will send to this order packing framing Time Slot Switching Circuit delivers to two-way E1 interface respectively by STO0/STO1 after the exchange and sends to the E1 circuit for the other side's reception.To confirm to order the E1 interface that turns back to local time interval insertion module by same mode after the other side receives and carries out, send the data to the STI0/STI1 of Time Slot Switching Circuit after the E1 interface receives.Sent to the reception buffering area of High level data link control processor circuit after exchanging by STO2/STO3, the High level data link control processor circuit unpacks the back with data and sends the interruption application to central processing unit.After the central processing unit reading of data these data are sent to the webmaster of PC by UART Universal Asynchronous Receiver Transmitter and configuration serial ports.
All signals of time interval insertion module all are that the socket X11 by 40PIN links to each other with image plate by the band line and finishes the transmission of signal, video data that has encoded on the image encoding plate and voice data are directly delivered to the STI4/STI5 of the Time Slot Switching Circuit of time interval insertion module by X11, send to the E1 circuit and receive for the other side by delivering to two-way E1 interface by the STO0/STO1 of Time Slot Switching Circuit after the exchange.The other side receives afterwards data to be exchanged by Time Slot Switching Circuit and isolates video, audio frequency, transparent mouth data, HDLC data, then transparent mouthful of data, HDLC data are delivered to each element circuit of this time interval insertion module, video, voice data are delivered to the decoding that the picture decoding plate is finished video and audio frequency by X11.
The time interval insertion transport module provides the E1 interface of 2 road sign standards, can determine the number of time slot that the high low speed image of its system takies respectively by configuration; The perhaps speed by each the end office (EO) image of background net management on same E1 circuit of definition on the interface, and all good E1 bandwidth of the shared predefined of end office's image, each image can be monopolized this bandwidth and realize high speed image with shared this bandwidth of low speed or by certain end office's image.These all operations all are that the online dynamic adjustment of system realizes, the transparent channel of maximum 3 transfer of data is provided simultaneously, asynchronous RS232, RS422 data can be passed through synchronization channel transmissions.Asynchronously realize by hardware fully, can adapt to the asynchronous interface of different rates like this, need not dispose communications parameter, realize that hardware is transparent completely to synchronous conversion.The mode reliability that this implementation realizes than software improves a lot.The information of each transparent serial ports takies any one time slot of 1-31, can select convenient, flexible networking by software programming.Theory diagram is seen accompanying drawing 3.The DS21354 that the E1 interface circuit adopts DALLAS company on this plate is as the E1 interface chip, and its significant feature is the mutual conversion of the interior binary system NRZ coded signal (HW line signal) of E1 signal and plate on the circuit.Finish line clock simultaneously and extract, the state of detection line detects LOS signal and OOF, sends and detect ais signal, functions such as CRC-4 verification.Emerging middle scale switching network chip ZX256 during Time Slot Switching Circuit adopts; Communication and control circuit are made up of 8031 single-chip microcomputers and two hdlc controllers 21525 or 21354 HDLC functions own.Finish initialization and control, to the initialization and the time gas exchange setting of switching network chip, by the communication between the hdlc controller realization codec unit to the E1 interface chip.Sequential and control logic are finished by EPLD, and clock adopts the MT8941 chip of MITEL company.
The E1 signal is converted to HW signal in the plate by the E1 interface circuit, the data that will transmit by the time gas exchange chip are inserted in the idle time slot, no time slot is also gone out by the exchange transparent transmission, has promptly comprised the data of inserting like this in the output signal, does not destroy original data again.The data of the direction of only having drawn among the figure are inserted situation, and the data extract of another direction similarly.
Time interval insertion transport module operation principle is as follows:
1. central processing unit (CPU) part
CPU adopts the AT89C55 of atmel corp, and external crystal oscillator is 12MHz, utilizes 20k bytesFlash Memory and 128 bytes RAM on the sheet to make program storage and data storage, and an external serial EEPROM AT24C02 deposits some configuration informations.Reset circuit adopts the MAX813 of MAXIM company, monitors the operation of supply voltage and software.
2. clock part
The main chip of this part circuit is MT8941, has master slave mode available: during for holotype, be operated in the free oscillation mode, this moment, the clock input was provided by crystal, and clock accuracy is determined by crystal; For from pattern the time, MT8941 preferentially extracts clock from circuit, if circuit does not provide clock, obtains clock from crystal automatically.8kHz, the 2MHz of MT8941 output and 4MHz clock are that interface circuit and image volume (separating) sign indicating number module provide clock signal after EPLD handles.
3.E1 interface section
The E1 interface is made of BT8510, the physical circuit interface of finishing E1 form framing and G.703 advising.Two groups of E1 interfaces are arranged on this module, therefore two BT8510 are arranged.Interface in the BT8510 plate is the linear formula of HW, inserts bits such as TS0, multiframe alignment, CRC check, fault alarm indication in pcm stream by the register that BT8510 inside is set.BT8510 can extract the 8kHz clock signal for the synchronous usefulness of this module in the line.
4. serial ports part
This module has 5 serial ports, comprises COMC, COMV, C0MT0～2.COMV is that CPU carries serial ports, is used for compiling communicating by letter between (separating) sign indicating number module with image, and also be the inside serial ports of this module; COMC is the serial ports through a slice 16C550 expansion, as configuration control serial ports; COMT0 and COMT1 are the optional transparent serial ports of RS232/RS422, another (COMT2) is RS232 (3 line)/RS422 (4 line) mutual exclusion alternative mode with configuration control mouth, even selecting configuration control mouth is the RS232 mode, and then transparent mouthful of 2 (COMT2) are the RS422 mode, and vice versa.Transparent serial ports it " transparent " is meant the transmission course of Serial Port Information from this module to remote end module without any processing.Conversion from the rs 232 serial interface signal line to HW and inverse transformation thereof are finished in the EPLD the inside.For avoiding signal to disturb, serial ports outer end and inside modules realize photoelectricity isolation, isolated from power between each serial ports by optocoupler.
5. first logical circuit
First logical circuit is mainly finished to each programming device on the module chip selection signal is provided; 8kHz, 2MHz, 4MHz signal that MT8941 is produced carry out producing the needed clock of each chip synchronously; Produce the used local bus of MT8985 read-write; Other control logics etc.In the design process, principles such as 74154,74138 decodings, 74374 are latched, d type flip flop establishment sequence circuit have mainly been utilized.
The address decoding part has mainly utilized 74154 decoders to finish the decoding of address, produces the required chip selection signal of each programmable chip.
Processing to MT8941 output clock: MT8941 output 8kHz, 2MHz and 4MHz clock signal, different chips has different requirements to the phase relation of clock signal, cooperate with unit such as door or doors with d type flip flop and to finish adjustment each clock, because of the Bus Speed of MT8985 well below cpu bus, and the CPU of this module does not provide the empty function of waiting for, the address bus of MT8985 and data/address bus must just can be finished the read-write operation of CPU through certain processing.The read-write of MT8985 mainly is subjected to 3 signal line/CS, I) S, RW control ,/CS is a chip selection signal, and DS is a communication signal, and the direction of data circulation on the RW decision MT8985 data/address bus is to read in 1 o'clock, is to write in 0 o'clock.Above-mentioned three signals meet the sequential requirement of chip fully when ensureing read-write operation, and in the design, these 3 signals are by software control.
6. second logical circuit
This modular design three transparent serial ports, three transparent serial ports are by two slot transmission in the 2M link.Serial ports is realized by programming device to the transparent translation of HW line.This design provides the conversion of three transparent serial ports, and each takies half time slot (4bit) transmission in the HW line.When networking two modules can be set at two ends, the serial ports at two ends can be realized transparent transmission by the time slot of 64kbits/s.The asynchronous communication mouth is finished by the sampling storage to the conversion of synchrodata, the signal of asynchronous communication mouth is sampled and stores with the clock of 32kHz, at corresponding time slot the data of storage is exported; At opposite side the data of half time slot are elongated with the clock recovery of 32kHz, promptly realized being converted to the process of asynchronous communication mouth signal by synchrodata.
According to sampling thheorem, when each serial ports during with half slot transmission, the speed of design serial ports reaches as high as 16kbit/s, actually supports that the serial ports flank speed is 14.4kbit/s.
Microprocessor Interface partly comprises an eight bit register, is used for the selection of output mode and ring control certainly.Register is realized data latchings by 74374, and by triple gate control output, so register is read-write register, is convenient to software control.
The clock processing section mainly is made up of the frequency divider sum counter, is used to produce various clock signals.The clock that frequency divider produces mainly contains and is used for the 512kHz clock that time slot is selected, the 32kHz clock that is used to sample.This part produces the frame synchronizing signal and the timing signal of HW line interface by phse conversion.
Conversion portion is the design's core, mainly is made up of deserializer spare STOP4 and parallel-to-serial converter spare PTOS4, and comprises latch.
The process of output HWCOMO that the input COMRXn of com port is converted to the HW line is as follows: the clock of 32kHz is sampled to COMRXn, sampling is to realize by STOP4 string and conversion, the clock of string and conversion is 32kHz, promptly (125us) samples 4 times in the time of a frame, first sampled point in one frame in the 8kHz frame synchronizing signal more after a while, and the sampled data in the former frame is latched with frame synchronizing signal, come these data to be got among the parallel-to-serial converter spare PTOS4 in next frame synchronizing signal temporarily, the clock of PTOS4 is 2MHz, by the output of time slot gating signal SLDn control clock, can be in the time slot dateout of appointment.Just produced the conversion time delay of a frame (125 μ s) like this between input and output, this is to not influence of data communication.
Oppositely as the same, only clock is swapped round.
Output control part is mainly realized by triple gate and MUX.Ternary control of output and the various self-looped testing function of main intact HWCOMO and COMTXn.
7. the main chip that adopts of time interval insertion transport module
The main chip of table 2 time interval insertion transport module
| Numbering | Title | Specifications and | Company | |
| 1 | E1 line interface chip | BT8510 | Brooktree | |
| 2 | The HDLC protocol controller | PSB21525 | SIEMENS | |
| 3 | Digitally enhanced interchanger | MT8985 | MITEL | |
| 4 | Digital phase-locked | MT8941 | MITEL | |
| 5 | Serial EEPROM | AT24C02 | ATMEL | |
| 6 | Central processing unit | AT89C55 | ATMEL |
The time interval insertion module can cooperate arbitrarily with image coding module and picture decoding module, to carry out data according to actual needs; Data, voice; Data, image, voice monitoring.C+A places controlled telepoint base station.C+B places Surveillance center.The bandwidth of image encoding can be decided according to the quantity of controlled base station and the transmission bandwidth that may provide, and can regulate arbitrarily between 1-26B.Voice take 1 time slot, a data occupancy 1-2 time slot.(C represents the time interval insertion transport module; A representative image coding module; B representative image decoder module).
Fig. 5 is the point-to-point networking mode 1 that the present invention adopts the E1 special line, and Surveillance center and supervised exchange adopt the connected mode of E1 special line, and the highest digit rate of image can reach 30fps.
Fig. 6 is the point-to-point networking mode 2 that the present invention adopts the E1 special line, several controlled end office (EO)s by an E1 private line access together in this kind mode, different time-gap in the image of each end office (EO), voice, the data occupancy E1 special line, the decoder module of Surveillance center is corresponding one by one with the coding module of end office (EO).Adopt this kind networking mode to set vision bandwidth according to the end office's quantity that inserts, the general end office's quantity that inserts is many more, and the frame frequency of center decoded picture is low more.
Fig. 7 is the networking mode that the present invention adopts 1 point-to-multipoint of E1 special line, several controlled end office (EO)s by an E1 private line access together in this kind mode, different time-gap in the image of each end office (EO), voice, the data occupancy E1 special line, Surveillance center is corresponding with a plurality of coding modules of end office (EO) with a decoder module, image, voice and the data of the method inquiry end office (EO) that utilization is switched.Adopt this kind networking mode to set vision bandwidth according to the end office's quantity that inserts, the general end office's quantity that inserts is many more, and the frame frequency of center decoded picture is low more.
Fig. 8 is the point-to-point networking mode that the present invention adopts time interval insertion, the transmission line of BST at first is connected to coding module in this kind mode, coding module is inserted into image, voice and image data in the idle time slot, output to Surveillance center in exchanges data to an E1 circuit of BSC with a plurality of end office (EO)s, the decoding unit of the respective numbers of Surveillance center extracts the time slot of corresponding end office (EO) and handles.Adopt this kind networking mode to set vision bandwidth according to the end office's quantity that inserts, the general end office's quantity that inserts is many more, and the frame frequency of center decoded picture is low more.
Fig. 9 is the networking mode that the present invention adopts 1 point-to-multipoint of time interval insertion, the transmission line of BST at first is connected to coding module in this kind mode, coding module is inserted into image, voice and image data in the idle time slot, output to Surveillance center in exchanges data to an E1 circuit of BSC with a plurality of end office (EO)s, Surveillance center is corresponding with a plurality of coding modules of end office (EO) with a decoder module, image, voice and the data of the method inquiry end office (EO) that utilization is switched.Adopt this kind networking mode to set vision bandwidth according to the end office's quantity that inserts, the general end office's quantity that inserts is many more, and the frame frequency of center decoded picture is low more.
Figure 10 is the multi-multipoint mixed fast networking mode that the present invention adopts the E1 special line, several controlled end office (EO)s by an E1 private line access together in this kind mode, the configuration of the image of each end office (EO), voice, data based system network management can take the identical/different time-gap in the E1 special line, Surveillance center is corresponding with a plurality of coding modules of end office (EO) with same a plurality of decoder modules, the data that can directly inquire about all end office (EO)s; Share the E1 bandwidth of setting for the end office (EO) that image can be all, the picture frame frequency that this moment, each decoder module showed is lower; Perhaps can be online the image of certain end office (EO) be exclusively enjoyed with the high speed of 30 frames and be used for the image transfer bandwidth, some specific (special) requirements of can be used to very easily to link alarm or user.Adopt the dynamic change of this kind networking mode image any influence can not arranged, and can reach 31 end office's number maximum that can articulate on the E1 circuit to the data of transparent transmission.
Claims (6)
1. one kind is adopted time slot add-drop method to mix fast image, the device of voice and data monitoring, it is characterized in that: be connected with each other when it is included in operating state, realize data, video, audio frequency mixes two time interval insertion transport modules of speed transmission, and one end link to each other with a described time interval insertion transport module, with image, Speech Signal Compression coding back reaches Surveillance center by the time interval insertion transport module, the compressed digital voice that also Surveillance center passed are down decoded simultaneously, the image coding module that contains audio coder ﹠ decoder (codec) of output simulated audio signal, and one end link to each other with described another piece time interval insertion transport module, image coding module is reached the digital picture of Surveillance center, tone decoding is converted to analog signal output, the analog voice signal of Surveillance center is encoded, the picture decoding module that contains audio coder ﹠ decoder (codec) of the image coding module of the data behind the coding by reaching end office (EO) under the time interval insertion transport module, described two time interval insertion transport modules comprise two-way E1 interface circuit connected to one another, the Time Slot Switching Circuit that is connected with described two-way E1 interface circuit, the High level data link control processor that is connected with Time Slot Switching Circuit and second logical circuit, the central processing unit that is connected with second logical circuit, UART Universal Asynchronous Receiver Transmitter that is connected with central processing unit and serial electric erasable programmable memory device, the digital PLL circuit that is connected with one road E1 interface circuit, first logical circuit that one end is connected with digital PLL circuit, described first logical circuit is exported various clocks and is given Time Slot Switching Circuit, the E1 interface circuit, the High level data link control processor circuit, the UART Universal Asynchronous Receiver Transmitter circuit, the image encoding plate that image coding module is included, the included picture decoding plate of picture decoding module provides work clock, described UART Universal Asynchronous Receiver Transmitter is connected with the configuration order that a configuration serial ports is used to receive the PC webmaster, or to PC webmaster transmission return command, described central processing unit is connected with an image encoding plate or picture decoding board communications and is used for system operational parameters is transmitted so that On-line Control whole system image operating rate and finish resetting to image encoding plate or picture decoding plate to image encoding plate or picture decoding plate with serial ports, the transmission of switching controls order, described second logical circuit are connected with three transparent serial ports and are used for carrying out the transparent transmitting-receiving of remote data to the equipment that has serial ports that links to each other with the time interval insertion transport module.
2. employing time slot add-drop method according to claim 1 mixes fast image, the device of voice and data monitoring, it is characterized in that: described image coding module comprises the image encoder of receiver, video input signal, one end is connected the logic control circuit that the other end is connected with time interval insertion transport module first logical circuit by the special-purpose gang socket of the image module of time interval insertion transport module with the X21 interface with image encoder, one end is connected the other end and is connected with time interval insertion transport module central processing unit by the special-purpose gang socket of the image module of time interval insertion transport module with logic control circuit, when work, utilize communication serial port to realize the data processor of message mutually, the audio coder ﹠ decoder (codec) that the special-purpose gang socket of image module by the time interval insertion transport module is connected with second logical circuit of time interval insertion transport module, the described socket that is connected with first logical circuit will send to image coding module from the clock signal of time interval insertion transport module first logical circuit and receive simultaneously from image coding module processed video encoding stream, the described socket that is connected with second logical circuit will send to audio coder ﹠ decoder (codec) by high speed data lines from the speech message of Surveillance center, receive from the voice of this audio coder ﹠ decoder (codec) simultaneously and utilize the logic control circuit of time interval insertion transport module to handle it to send to Surveillance center by the E1 interface after the back exchanges to predetermined time slot by switching network.
3. employing time slot add-drop method according to claim 1 mixes fast image, the device of voice and data monitoring, it is characterized in that: described picture decoding module comprises the image decoder of receiver, video output signal, one end is connected the logic control circuit that the other end is connected with time interval insertion transport module first logical circuit by the special-purpose gang socket of the image module of time interval insertion transport module by the X21 interface with image decoder, one end is connected the other end and is connected with time interval insertion transport module central processing unit by the special-purpose gang socket of the image module of time interval insertion transport module with logic control circuit, when work, utilize communication serial port to realize the data processor of message mutually, the audio coder ﹠ decoder (codec) that the special-purpose gang socket of image module by the time interval insertion transport module is connected with second logical circuit of time interval insertion transport module, the described socket that is connected with first logical circuit will send to the picture decoding module from the clock signal of time interval insertion module first logical circuit simultaneously will delivering to the picture decoding module from far-end image coding module processed video stream and carry out picture decoding by E1 circuit transmission, the described gang socket that is connected with second logical circuit will send to audio coder ﹠ decoder (codec) by high speed data lines from the speech message of distant station, receive from the voice of this audio coder ﹠ decoder (codec) simultaneously and utilize the logic control circuit of time interval insertion transport module to handle it to send to distant station by the E1 interface after the back exchanges to predetermined time slot by switching network.
4. employing time slot add-drop method according to claim 1 mixes the device of fast image, voice and data monitoring, it is characterized in that: described first logical circuit is the erasable programmable device.
5. employing time slot add-drop method according to claim 1 and 2 mixes the device of fast image, voice and data monitoring, it is characterized in that: described second logical circuit is the erasable programmable device.
6. employing time slot add-drop method according to claim 3 mixes the device of fast image, voice and data monitoring, it is characterized in that: the described transparent serial ports that is connected with second logical circuit is parallel serial ports.
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| CNB031133681A CN100512061C (en) | 2003-04-28 | 2003-04-28 | Device using time slot add-drop method to monitor mixed speed image, voice and data |
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| CNB031133681A CN100512061C (en) | 2003-04-28 | 2003-04-28 | Device using time slot add-drop method to monitor mixed speed image, voice and data |
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| CN100512061C true CN100512061C (en) | 2009-07-08 |
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