CN100517505C - Synchronous dynamic memory read-write method and read-write equipment - Google Patents
Synchronous dynamic memory read-write method and read-write equipment Download PDFInfo
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- CN100517505C CN100517505C CNB2007101420503A CN200710142050A CN100517505C CN 100517505 C CN100517505 C CN 100517505C CN B2007101420503 A CNB2007101420503 A CN B2007101420503A CN 200710142050 A CN200710142050 A CN 200710142050A CN 100517505 C CN100517505 C CN 100517505C
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Abstract
The invention discloses a read-write method and the corresponding device for synchronous dynamic random access memory, which comprises steps as follows: step S102, to cache the current read-write and access requests and the read-write and access addresses; step S104, to identify the status of the previous access request and make it processed according to the current read-write access and the judgment, thus to improve the work efficiency of the SDRAM controller.
Description
Technical field
The present invention relates to SDRAM (synchronous dynamic random access memory, Synchronous DynamicRAM) control method, specifically, relate to the method that improves SDRAM efficient.
Background technology
SDRAM is a kind of high-speed cmos dynamic RAM, SDRAM carries out read-write operation, at first need to activate Bank and the Row of SDRAM, satisfy just can send after the regular hour and read or write order carries out the reading and writing operation to SDRAM, after the reading and writing EO, can close the Bank of activation at once, also can select to allow this Bank keep activating, but, just must close the Bank that has activated if other Row of this Bank is carried out the reading and writing operation.
Based on these characteristics of SDRAM, outside request of access to SDRAM all needs just can deliver to the SDRAM device through certain processing.The device of finishing these processing is commonly called sdram controller.
The control strategy of sdram controller directly influences the work efficiency of device, simple controllers only need activate before each read-write, after read-write, carry out precharge, and guarantee that interval between the order satisfies the requirement of SDRAM device and get final product, but such control strategy efficient is very low, directly influences the data throughout of device.In order to improve the work efficiency of SDRAM, setting long Burst Length is the simplest method, but is subjected to using the restriction of scene, can not generally be suitable for.Also have to utilize to switch between the different B ank and can reduce the method for tRP stand-by period, interleave to reach BANK but be confined to data source end adjustment data structure usually, thereby reduce the overhead time, but have limitation equally.Patent CN200510023687 " memory access controller and access method of storage " has proposed a kind of caching mechanism selectivity that adopts and has sent the visit inequality of Bank address, can raise the efficiency like this, but cost is artificial " unfairness " that caused visit, individualized access may need to wait for that the long period just can meet with a response, and causes the temporary transient obstruction of this direction; CN200410091955 " a kind of SDRAM of raising handles the method for bandwidth " reaches the purpose of raising the efficiency by the improvement to the data content of storage; CN200510061654 " a kind of method for designing of synchronous dynamic storage controller " proposes the method that a kind of address resolution is optimized, avoid the same Bank of connected reference, but such method is only effective to the continuous situation in address, if the address is a random variation, the method for this optimization does not have effect.
Therefore, need a kind of reading/writing method and read-write equipment of synchronous dynamic random access memory, be used to improve the work efficiency of sdram controller.
Summary of the invention
Consider the problems referred to above and make the present invention, for this reason, fundamental purpose of the present invention is, a kind of reading/writing method of synchronous dynamic random access memory is provided, it comprises: step S102, buffer memory send to the address of the request and the read and write access of the current read and write access in the synchronous dynamic random access memory; And step S104, judge the state of a last read and write access request, read and write processing accordingly according to current read and write access and judged result.
The address can comprise Bank address and Row address.
Step S104 can also comprise: when the state of judging a last request of access at read states or before writing the state end and current read and write access with on the type of read and write access when identical, the address of a more current read and write access and a last read and write access, if comparative result is identical, then read and write access before a last read and write access request finishes the laggard trade, if comparative result is inequality, the read write command that has auto-precharge is adopted in then current read and write access.
Step S104 can also comprise: when the state of judging a last request of access is waiting status, the Bank address of a more current read and write access and a last read and write access, if comparative result difference, then enter state of activation, if comparative result is identical, after the auto-precharge of a last visit, enter state of activation after waiting for the very first time.
According to a further aspect in the invention, provide a kind of read-write equipment of synchronous dynamic random access memory, having comprised:
Buffer is used for buffer memory and sends to the request of current read and write access of synchronous dynamic random access memory and the address of read and write access;
The state judging unit is used to judge the state of a last read and write access request;
Address and comparing unit are used for comparison from the address of the current read and write access of buffer and the address and the type of a type and a last read and write access; And
Control module is used for according to controlling current read and write access from the judged result of state judging unit with from the comparative result of address and type comparing unit.
The address can comprise Bank address and Row address.
Control module when the state of judging a last request of access at read states or before writing the state end and current read and write access with on the type of read and write access when identical, the address of a more current read and write access and a last read and write access, if comparative result is identical, then read and write access before a last read and write access request finishes the laggard trade, if comparative result is inequality, the read write command that has auto-precharge is adopted in then current read and write access.
When control module is waiting status when the state of judging a last request of access, the Bank address of a more current read and write access and a last read and write access, if comparative result difference, then enter state of activation, if comparative result is identical, after the auto-precharge of a last visit, enter state of activation after waiting for the very first time.
By technique scheme, the present invention can improve the work efficiency of sdram controller
Other features and advantages of the present invention will be set forth in the following description, and, partly from instructions, become apparent, perhaps understand by implementing the present invention.Purpose of the present invention and other advantages can realize and obtain by specifically noted structure in the instructions of being write, claims and accompanying drawing.
Description of drawings
Accompanying drawing is used to provide further understanding of the present invention, and constitutes the part of instructions, is used from explanation the present invention with embodiments of the invention one, is not construed as limiting the invention.In the accompanying drawings:
Fig. 1 shows the process flow diagram according to the reading/writing method of synchronous dynamic random access memory of the present invention;
Fig. 2 shows the block scheme according to the read-write equipment of synchronous dynamic random access memory of the present invention;
Fig. 3 shows the process flow diagram according to the reading/writing method of the synchronous dynamic random access memory of the embodiment of the invention;
Fig. 4 is existing DDR control command state machine; And
Fig. 5 is according to control command state machine of the present invention.
Embodiment
Below in conjunction with accompanying drawing the preferred embodiments of the present invention are described, should be appreciated that preferred embodiment described herein only is used for description and interpretation the present invention, and be not used in qualification the present invention.
Technical matters to be solved by this invention is in the prior art, for address visit at random, the problem that the sdram controller work efficiency is lower.
Core concept of the present invention is: read-write requests that the buffer memory outside is sent into and address; Visit the state that carries out according to the last time, the Bank address and the Row address of newer request and last request, and according to comparative result and the last state that is carried out of visiting, judge that new request is directly to carry out read-write operation, still do not wait for that the tRP time directly begins the activation of Bank, otherwise wait for that the enough time visits the activation of Bank more next time.Thereby reach the purpose of raising the efficiency.
With reference to Fig. 1, a kind of reading/writing method of synchronous dynamic random access memory is provided, it comprises: step S102, buffer memory send to the address of the request and the read and write access of the current read and write access in the synchronous dynamic random access memory; And step S104, judge the state of a last read and write access request, read and write processing accordingly according to current read and write access and judged result.
The address can comprise Bank address and Row address.
Step S104 can also comprise: when the state of judging a last request of access at read states or before writing the state end and current read and write access with on the type of read and write access when identical, the address of a more current read and write access and a last read and write access, if comparative result is identical, then read and write access before a last read and write access request finishes the laggard trade, if comparative result is inequality, the read write command that has auto-precharge is adopted in then current read and write access.
Step S104 can also comprise: when the state of judging a last request of access is waiting status, the Bank address of a more current read and write access and a last read and write access, if comparative result difference, then enter state of activation, if comparative result is identical, after the auto-precharge of a last visit, enter state of activation after waiting for the very first time.
With reference to Fig. 2, a kind of read-write equipment of synchronous dynamic random access memory is provided, comprising:
Buffer is used for buffer memory and sends to the request of current read and write access of synchronous dynamic random access memory and the address of read and write access;
The state judging unit is used to judge the state of a last read and write access request;
Address and type comparing unit are used for comparison from the address of the current read and write access of buffer and the address and the type of a type and a last read and write access; And
Control module is used for according to controlling current read and write access from the judged result of state judging unit with from the comparative result of address and type comparing unit.
The address can comprise Bank address and Row address.
Control module when the state of judging a last request of access at read states or before writing the state end and current read and write access with on the type of read and write access when identical, the address of a more current read and write access and a last read and write access, if comparative result is identical, then read and write access before a last read and write access request finishes the laggard trade, if comparative result is inequality, the read write command that has auto-precharge is adopted in then current read and write access.
When control module is waiting status when the state of judging a last request of access, the Bank address of a more current read and write access and a last read and write access, if comparative result difference, then enter state of activation, if comparative result is identical, after the auto-precharge of a last visit, enter state of activation after waiting for the very first time.
The present invention is by receiving read-write requests in advance, the address of visit compares with the last time, and according to the process that the last time visits, judges whether to enter the Active state or do not wait for the tRP time, even the address random variation of the outside read-write requests of sending into also can improve the DDR work efficiency.And can not cause the obstruction or temporary transient stagnation of any one request of access.
Fig. 3 shows the process flow diagram according to the reading/writing method of the synchronous dynamic random access memory of the embodiment of the invention.
With reference to Fig. 3, if new request of access is arranged, judge a last state that visit is carried out: if a last visit has entered the S_IDLE state, the Bank address of a newer request and a last request of access, if it is identical, then count, wait for that the new visit of rRP time just can enter the S_ACT state from last AutoPrecharge state; If the Bank address is inequality, then directly enter the S_ACT state.If a last visit is also at S_ACT state or S_RCD_WAIT state, and identical with new request type (be all read request or be all write request), the Bank address of a newer request and a last visit and Row address, if the both is identical, a last visit does not enter S_IDLE, and new visit directly enters S_RD or S_WR state.Otherwise last visit read command or the write order that has AutoPrecharge.
With reference to Fig. 4, S_IDLE among the figure, S_ACT, S_RCD_WAIT, S_RD, S_WR, S_WR_WAIT, S_RD_WAIT, S_PRE represent that respectively state represents waiting status respectively, and state of activation activates waiting status, read states is write state, reads waiting status, writes waiting status, pre-charge state.All needed once to activate before each read-write operation, all carry out precharge after the read-write operation, efficiency ratio is lower.
With reference to Fig. 5, Fig. 4 has reduced S_WR_WAIT, S_RD_WAIT, the several states of S_PRE relatively.Read states and write state and can keep according to the situation of Bank address and Row address relatively is without precharge and activation.The last read-write operation of jumping out read states or writing state adopts the order that has AutoPrecharge.According to the address comparative result, judge whether to enter the S_PR_WAIT state.The Bank address situation all identical with the Row address of path 10 and 12 respectively corresponding adjacent twice visit, directly begin next time read operation or write operation after finishing last read operation or write operation this moment.The Bank address situation inequality of path 5 corresponding adjacent twice visit does not need to wait for this moment, directly enters state of activation.
By the described method of this patent,, also can effectively improve the work efficiency of DDR SDRAM even visit random address.And good versatility is arranged.
The above is the preferred embodiments of the present invention only, is not limited to the present invention, and for a person skilled in the art, the present invention can have various changes and variation.Within the spirit and principles in the present invention all, any modification of being done, be equal to replacement, improvement etc., all should be included within protection scope of the present invention.
Claims (2)
1. the reading/writing method of a synchronous dynamic random access memory is characterized in that, comprising:
Step S102, buffer memory send to the address of the request and the read and write access of the current read and write access in the described synchronous dynamic random access memory, and wherein, described address comprises Bank address and Row address; And
Step S104 judges the state of a last read and write access request, reads and writes processing accordingly according to described current read and write access and judged result, wherein,
When the state of judging described a last request of access at read states or before writing the state end and described current read and write access with on the type of read and write access when identical, the described address of a more described current read and write access and a described last read and write access, if comparative result is identical, then a read and write access request is carried out described current read and write access after finishing on described, if described comparative result is inequality, the read write command that has auto-precharge is adopted in then described current read and write access;
When the state of judging a described last request of access is waiting status, the described Bank address of a more described current read and write access and a last read and write access, if comparative result difference, then enter state of activation, if described comparative result is identical, after the auto-precharge of a last visit, enter state of activation after waiting for the very first time.
2. the read-write equipment of a synchronous dynamic random access memory is characterized in that, comprising:
Buffer is used for buffer memory and sends to the request of current read and write access of described synchronous dynamic random access memory and the address of read and write access, and wherein, described address comprises Bank address and Row address;
The state judging unit is used to judge the state of a last read and write access request;
Address and type comparing unit are used for comparison from the address of the current read and write access of described buffer and the address and the type of a type and a described last read and write access; And
Control module is used for according to controlling current read and write access from the judged result of described state judging unit with from the described comparative result of described address and type comparing unit, wherein,
Described control module when the state of judging described a last request of access at read states or before writing the state end and described current read and write access with on the type of read and write access when identical, the described address of a more described current read and write access and a described last read and write access, if comparative result is identical, then a read and write access request is carried out described current read and write access after finishing on described, if described comparative result is inequality, the read write command that has auto-precharge is adopted in then described current read and write access;
When described control module is waiting status when the state of judging a described last request of access, the described Bank address of a more described current read and write access and a last read and write access, if comparative result difference, then enter state of activation, if described comparative result is identical, after the auto-precharge of a last visit, enter state of activation after waiting for the very first time.
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| CNB2007101420503A CN100517505C (en) | 2007-08-20 | 2007-08-20 | Synchronous dynamic memory read-write method and read-write equipment |
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| CNB2007101420503A CN100517505C (en) | 2007-08-20 | 2007-08-20 | Synchronous dynamic memory read-write method and read-write equipment |
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| CN100517505C true CN100517505C (en) | 2009-07-22 |
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| CN101625892B (en) * | 2009-08-07 | 2011-12-21 | 杭州华三通信技术有限公司 | Controller of dynamic random-access memory and user instruction treatment method |
| US9268720B2 (en) | 2010-08-31 | 2016-02-23 | Qualcomm Incorporated | Load balancing scheme in multiple channel DRAM systems |
| CN102103548B (en) * | 2011-02-22 | 2015-06-10 | 中兴通讯股份有限公司 | Method and device for increasing read-write rate of double data rate synchronous dynamic random access memory |
| CN113900818A (en) * | 2021-10-19 | 2022-01-07 | 瓴盛科技有限公司 | DDR memory data read-write scheduling method and device |
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Application publication date: 20080312 Assignee: SHENZHEN ZTE MICROELECTRONICS TECHNOLOGY CO., LTD. Assignor: ZTE Corporation Contract record no.: 2015440020319 Denomination of invention: Synchronous dynamic memory read-write method and read-write equipment Granted publication date: 20090722 License type: Common License Record date: 20151123 |
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