CN100501694C - Processor availability measuring device and method - Google Patents
Processor availability measuring device and method Download PDFInfo
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- CN100501694C CN100501694C CN 200710106196 CN200710106196A CN100501694C CN 100501694 C CN100501694 C CN 100501694C CN 200710106196 CN200710106196 CN 200710106196 CN 200710106196 A CN200710106196 A CN 200710106196A CN 100501694 C CN100501694 C CN 100501694C
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- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/30—Monitoring
- G06F11/34—Recording or statistical evaluation of computer activity, e.g. of down time, of input/output operation ; Recording or statistical evaluation of user activity, e.g. usability assessment
- G06F11/3409—Recording or statistical evaluation of computer activity, e.g. of down time, of input/output operation ; Recording or statistical evaluation of user activity, e.g. usability assessment for performance assessment
- G06F11/3419—Recording or statistical evaluation of computer activity, e.g. of down time, of input/output operation ; Recording or statistical evaluation of user activity, e.g. usability assessment for performance assessment by assessing time
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- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/30—Monitoring
- G06F11/34—Recording or statistical evaluation of computer activity, e.g. of down time, of input/output operation ; Recording or statistical evaluation of user activity, e.g. usability assessment
- G06F11/3466—Performance evaluation by tracing or monitoring
- G06F11/349—Performance evaluation by tracing or monitoring for interfaces, buses
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- G06—COMPUTING; CALCULATING OR COUNTING
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- G06F2201/88—Monitoring involving counting
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Abstract
This invention discloses a measurement device for usability of an inserted system processor including: a system bus connected with a bus monitor, a counter and a processor, a bus monitor used in monitoring the system bus and generating a trigger signal on the counter when identifying the preset bus character, a timer setting time length of statistic time period of usability by setting its timed period, an interrupt controller used in generating interrupt trigger signals when the time period of the timer arrives. This invention also discloses a measurement method.
Description
Technical field
The present invention relates to the measuring technique of processor utilization, particularly, relate to the device and method that processor utilization or load are measured in real time, it is particularly useful for embedded system and handles utilization factor of device and measure.
Background technology
Because embedded system has very harsh requirement to hardware cost, power consumption, therefore the value of the type selecting of processor and relevant clock frequency thereof, supply voltage becomes main concern factor, and system when normally moving the utilization factor of processor determine the main reference foundation of these factors just.And some embedded systems can be regulated processor clock frequency or operating voltage in real time according to measurement result, just can reduce system power dissipation.
Processor utilization for one section timing statistics, that is, and the ratio of operating at full capacity that the actual effective work finished of this section timing statistics inner treater and processor can be finished.Therefore, what index to weigh the working load of processor with, and the measuring method of this index, the key that processor utilization is measured just become.
At present the known method to the measurement of processor utilization mainly contains following several:
A kind of method is to utilize the one-period timer as the triggering source that processor load is sampled, and determines that by operating system processor is to carry out valid code or free codes when each timer expires, and counts accordingly.Like this, in one section timing statistics, timer expires number of times as the full load index of processor, and this value deducts the execution free codes number of times that samples as the Payload index of processor in this period, and their ratio is exactly the utilization factor of processor at this section timing statistics.As seen, this method at first needs the operating system support, and the accuracy of measuring depends on the cycle of timer, and the cycle is more little, and precision is high more, but also just big more to the system performance influence.
Another kind method is idle process of definition, and this process adds up to a global variable.Allow operating system only move this idle process in certain period, the accumulated value of the global variable that obtains as processor index at full capacity, in the back in certain statistical time range with duration, the difference of global variable is as processor Payload index, and their ratio is as the processor utilization of this period.In this method, because when measurement processor full load index, the operating system factor is not considered and can't be accurately measured yet, and therefore has error unavoidably, thereby can draw the processor utilization less than normal than actual conditions.
In order to overcome above-mentioned unfavorable factor, having proposed some does not rely on operating system but mainly relies on hardware circuit to carry out the method that processor utilization is measured, these methods require processor must follow predefined performance state, such as ACPI standard (Advanced Configuration and Power Interface, abbreviate ACPI as), when processor is in idle condition, the clock signal that is sent to processor just is cut off, correspondingly, processor core counter (also claiming " ticktock " counter) also stops counting.Like this, the time of statistical time range as processor index at full capacity, the processor core counter be multiply by the counting clock cycle in the difference of statistical time range, and the time that obtains, both ratio was exactly the utilization factor of processor at this section timing statistics as processor Payload index.The prerequisite of said method is that processor must be observed certain specification, and this is very rare for flush bonding processor.
Therefore, by above description as can be seen, there is the dependency problem to operating system in currently used technology, and exist measuring error big, influence defective such as system performance, based on such background, if a kind of operating system, general processor utilization measurement mechanism of being independent of can be provided, be undoubtedly for the independence of measuring for processor utilization and the maintenance of accuracy and system desirable.
Summary of the invention
Consider the problems referred to above that exist in the correlation technique and propose the present invention.For this reason, the present invention aims to provide the measuring technique that a kind of embedded system is handled the device utilization factor, at first, a kind of general processor utilization factor measurement mechanism that is independent of operating system is provided, afterwards, proposed a kind of processor utilization measuring method on this basis, it can be used for the measurement of single statistical time range or many statistical time ranges.
Technical scheme of the present invention is as follows.
A kind of embedded system is handled the measurement mechanism of device utilization factor, and comprising: system bus links to each other with bus monitor, counter and processor; Wherein, processor is used for the operating measurement program, produces the expection bus characteristic on system bus, and wherein, process of measurement is the executable code that sets in advance; Bus monitor is used for the surveillance bus, when identifying the expection bus characteristic, produces counter trigger signal; Timer is by being provided with the duration that its timing cycle is provided with the utilization factor statistical time range; Interruptable controller is used for producing interrupt trigger signal when the timing cycle of timer arrives, and reads the count value of described counter by interrupt service routine; The calculation procedure module is used for calculating described processor utilization according to the described count value that described interruptable controller reads.
Wherein, counter is used as the workload indicator of processor to the count value of expection bus characteristic.Workload indicator comprises the index of operating at full capacity, current index and the Payload index of operating at full capacity, wherein, the index of operating at full capacity is the count value of counter in the system bootstrap stage, the current index of operating at full capacity obtains by operate at full capacity index and corresponding statistical time range, and the Payload index obtains in the count value of the statistical time range of correspondence by the current index of operating at full capacity is deducted counter.The calculation procedure module is used for that Payload index and the current index of operating at full capacity are carried out scale operation and comes the computation processor utilization factor.
A kind of measuring method of processor utilization comprises: step 1 sets in advance the processor process of measurement of index at full capacity; Step 2, in the system bootstrap stage, the operating measurement program is measured the full load index of processor in the given time, and reads the raw data of the value of counter as the full load index; Step 3 in system's operational process, is being measured the statistical time range of utilization factor, obtains current full load index corresponding to statistical time range according to raw data, and obtains the Payload index of processor according to the value of current full load index sum counter; Step 4 is according to the utilization factor of Payload index and current full load index counting statistics period inner treater.
Process of measurement is one section processor executable code, when carrying out process of measurement, produces the expection bus characteristic, and system's flip-flop number when monitoring the expection bus characteristic begins counting.
Wherein, in step 3, under the situation that a statistical time range is measured, timer is set to the single timing mode, and timing cycle is the duration of statistical time range.In step 3, under the situation that a plurality of statistical time ranges are measured, timer is set to the cycle timing mode, and timer is resetting automatically to after date.Like this, in step 3, for each statistical time range, the Payload index that it is corresponding leaves in the data buffer.In addition, in step 3, the Payload index equals value poor of current full load index and counter.In step 4, come the utilization factor of computation processor by calculation procedure.
By processor utilization calculation element of the present invention and method, than correlation technique, can improve measuring accuracy, reduce the negative effect that system performance is caused owing to measure in real time, in addition, the present invention has the characteristic of the operating system of not relying on, and processor is not made the characteristics of specific (special) requirements, and this makes the present invention can be applied to embedded system at large.
Description of drawings
Accompanying drawing described herein is used to provide further understanding of the present invention, constitutes the application's a part, and illustrative examples of the present invention and explanation thereof are used to explain the present invention, do not constitute improper qualification of the present invention.In the accompanying drawings:
Fig. 1 is the illustrative view of functional configuration according to the measurement mechanism of the processor utilization of the embodiment of the invention;
Fig. 2 is the illustrative view of functional configuration of the example 1 of measurement mechanism shown in Figure 1;
Fig. 3 is the illustrative view of functional configuration of the example 2 of measurement mechanism shown in Figure 1;
Fig. 4 is the operation system assumption diagram according to the measuring method of the processor utilization of the inventive method embodiment;
Fig. 5 is the process flow diagram according to the measuring method of the processor utilization of the inventive method embodiment;
Fig. 6 shows according to system bootstrap phase measuring program implementation situation in the method for the inventive method embodiment;
Fig. 7 shows the implementation status of normally moving the back process of measurement according to system in the method for the inventive method embodiment;
Fig. 8 is the synoptic diagram of annular data buffer and the storage of day part efficiency index in the method according to the inventive method embodiment; And
Fig. 9 a-Fig. 9 d shows the main treatment scheme of technical solution of the present invention; Wherein, Fig. 9 a shows the system bootstrap phase process device treatment scheme of index measurement at full capacity, and Fig. 9 b shows the system bootstrap phase process device Interrupt Process flow process of index measurement at full capacity; Fig. 9 c shows system and normally moves the preprocessor treatment scheme of index measurement at full capacity; Fig. 9 d shows system and normally moves the preprocessor Interrupt Process flow process of index measurement at full capacity.
Embodiment
Describe the embodiment of the invention in detail hereinafter with reference to accompanying drawing, wherein, provide following examples with provide to of the present invention comprehensively and thorough, rather than the present invention carried out any restriction.Wherein, do not described in detail,, under the situation that does not have these details to describe, can well be put into practice the present invention yet because for those of ordinary skills for some well-known structures, device, circuit and interface etc.
Device embodiment
A kind of measurement mechanism of processor utilization is provided in the present embodiment.
At first define one section executable code of processor as processor load index measurement program (hereinafter to be referred as process of measurement), can go up at system bus (perhaps being called processor bus) when processor is carried out this process of measurement and produce the expection bus characteristic, bus monitor flip-flop number when monitoring the expection bus characteristic begins counting, wherein, system bus can be the combinations of states that is not limited to control bus or data bus or address bus, will be to the count value of this bus characteristic as the processor workload indicator.
As shown in Figure 1, the measurement mechanism of this processor utilization comprises: processor 101, bus monitor 102, counter 103, timer 104, interruptable controller 105 and processor system bus 106.
Particularly, system bus 106 links to each other with bus monitor 102, counter 103 and processor 101.Bus monitor 102 is surveillance bus 106 always, when identifying the expection bus characteristic, produces counter trigger signal 107, causes that counter 103 begins counting.The duration of utilization factor statistical time range is set by the timing cycle that timer 104 is set.Interruptable controller 105 produces interrupt trigger signal 108 when the timing cycle of timer 104 arrives, by timer interrupt service routine (Interrupt Service Routine, abbreviate ISR as) value of counter is handled and preserved, use by processor utilization calculation procedure (hereinafter to be referred as calculation procedure) when needed, and then calculate the processor utilization of this statistical time range.
Wherein, processor 101 produces the expection bus characteristic on system bus 106 when carrying out the scheduled measurement program.And the count value of 103 pairs of expections of counter bus characteristic is as the workload indicator of processor 101.
Example 1
Fig. 2 shows processor and the peripheral equipment thereof as the core of embedded system part.Because at present flush bonding processor all is SOC (system on a chip) (System On Chip abbreviates SOC as) basically, it is integrated central processing unit (CPU) and many functional parts, these parts just comprise timer, interruptable controller, counter or the like.As shown in Figure 2, processor 201 has comprised timer and interruptable controller, therefore only need a slice programmable logic device (PLD) (Programmable Logic Device, abbreviate PLD as) 202 realize the bus monitor sum counter, comprise processor system bus 106 in addition and be used for ROM (read-only memory) (ROM) 203, the random access memory (RAM) 204 of the program of depositing or executive routine.Control signal 205 is produced by timer, is used for terminating in the vectoring phase processor is carried out the measurement of index at full capacity, is actually PLD and according to this signal survey mark is made amendment, and process of measurement is carried out for false stopping by judging survey mark.
Example 2
The another one example of apparatus of the present invention embodiment as shown in Figure 3.Processor 301 is integrated counter, timer and interruptable controller only need have the trigger pip 302 of the root system system bus of expection feature as counter.Similar to preceding example 1, also comprise processor bus 106 and be used for ROM (read-only memory) (ROM) 203, the random access memory (RAM) 204 of the program of depositing or executive routine.
The difference of this example and example 2 is: be not need programmable logic device (PLD) (PLD) on the hardware on the one hand, and different on the software on the other hand, particularly how to terminate in the system bootstrap stage to the processor measurement carried out of index at full capacity.This example has adopted following method: interrupt with timer expiry and generation, and send this measurement indication of termination in timer ISR.Specifically, carry out processor index measurement at full capacity, the cycle of timer is set earlier before the measurement,, start timer then and begin and measure such as 1 second on the appropriate opportunity in system bootstrap stage.Timer expires and produces interruption after 1 second, and it be false revising survey mark in interrupt service routine, and process of measurement judges that survey mark be that execution is ended in false back, and the test data preservation of obtaining is standby.The others details and the example 1 of this example are basic identical.
Method embodiment
In the present embodiment, provide a kind of measuring method of processor utilization, preferably, used above-mentioned measurement mechanism, certainly, also can use other suitable device to implement the present invention.
Fig. 4 is the operation system assumption diagram according to the measuring method of the inventive method embodiment.The a plurality of application programs 401 of process of measurement 402, calculation procedure 403 and system are mutual with operating system 404, and operate by 406 pairs of hardware of hardware device driver, timer interrupt service routine 405 is mutual and finish processing to data buffer zone 408 and global variable 407 with counter.Finally utilize treated data 407 to calculate processor utilization by calculation procedure 403.
As shown in Figure 5, the measuring method according to the processor utilization of the inventive method embodiment comprises following processing:
Step S502 (step 1) sets in advance the processor process of measurement of index at full capacity, for example, can define one section processor executable code as process of measurement;
Step S504 (step 2), in the system bootstrap stage, the operating measurement program is measured the full load index of processor in the given time, and reads the raw data of the value of counter as the full load index;
Step S506 (step 3), after the normal operation of system, at the statistical time range of measuring utilization factor, obtain current full load index according to raw data, and obtain the Payload index (equaling value poor of current full load index and counter) of processor according to the value of current full load index sum counter corresponding to statistical time range;
Step S508 (step 4) is by calculation procedure, according to the utilization factor of Payload index and current full load index counting statistics period inner treater.
In step S506, under the situation that a statistical time range is measured, timer is set to the single timing mode, and timing cycle is the duration of statistical time range; Under the situation that a plurality of statistical time ranges are measured, timer is set to the cycle timing mode, and timer is resetting automatically to after date, like this, in step S506, for each statistical time range, Payload index that need it is corresponding leaves in the data buffer.
Above general description each treatment step of the present invention, describe each details in the above-mentioned processing in detail below with reference to concrete accompanying drawing.
At first, define a function, carry out the at full capacity run time version of index measurement of processor as the system bootstrap stage, also it is normally moved the idle process that preprocessor is carried out by operating system scheduling when idle as system.The core of this function is a process of measurement, and according to the survey mark execution that circulates, carries out process of measurement and can produce the expection bus characteristic, for bus monitor identification and flip-flop number counting (step S502).
Set the processor utilization minimum statistics period T of a standard, this minimum period is also referred to as measurement period, and such as 100 milliseconds, the processor load index is for this period.When carrying out processor full load index measurement in the system bootstrap stage, in order to obtain more accurate measurement result, the duration of measurement period should be multiple times than T, such as the value that obtains counter after the measurement of carrying out for 1 second, so processor at full capacity index Cm (that is, above-mentioned current full load index) obtain (step S504) by the value of this counter divided by 10.
After the normal operation of system, when measuring certain measurement period processor utilization, processor Payload index obtains (Cm-Ci) (step S506) by the value Ci that Cm deducts this statistical time range counter.
The processor utilization calculation procedure calculates the utilization factor U:(step S508 of processor according to following formula (formula one))
U=(Cm-Ci)/Cm * 100% (step S508)
---formula (1)
Top formula only is aimed at a statistical time range T, when needs carry out multi-period n*T statistics, adopts following computing formula (formula 2) to calculate the utilization factor U of processor:
Un＝(Cm×n-(Ci1+Ci2+...+Cin))/(Cm×n)×100％
---formula (2)
Particularly, Fig. 6 show the system bootstrap stage to processor at full capacity during index measurement, the situation that process of measurement 602 is carried out by processor.As shown in Figure 6, on certain appropriate opportunity that guidance code 601 is performed, process of measurement is performed, and measures processor index at full capacity.When Fig. 7 shows and normally moves in system, the situation that application program 701 and process of measurement are carried out by processor.As shown in Figure 7, measure processor Payload index at different statistical time ranges.
When system normally moved, when need be to current time when in the future the processor utilization of certain period be measured, the cycle that should dispose timer equals the duration of this period, with counter O reset and start timer.When timer expired the generation interruption, timer ISR read the value of counter, and is calculated by above-mentioned formula (1) by calculation procedure, obtains the processor utilization of this period.
Under many circumstances, usually need to obtain certain of current time past or the processor utilization of a plurality of periods, this measures processor Payload index with regard to needs always, and the measurement data of each statistic period T is kept in the data buffer zone, use for calculation procedure or timer ISR, and along with the carrying out of measuring constantly refreshed with first-in first-out.As shown in Figure 8, this method adopts a buffer circle 801, the size of buffer zone to determine the duration of long statistical time range, is 100 milliseconds for statistic period T, if expect over 10 minutes processor utilization, then 6000 data need be deposited in the data buffer.In this long duration, can obtain the processor utilization of a plurality of littler periods, such as processor utilization U1s, U10s, U1m, U5m and the U10m of a plurality of periods such as can obtaining over 1 second, 10 seconds, 1 minute, 5 minutes, 10 minutes.
In order to keep that processor Payload index is measured always, should dispose timer after the normal operation of system is the cycle timing mode, promptly, timer can reset automatically to after date, timing cycle just is made as statistic period T, promptly 100 milliseconds, then with the data buffer initialization and start timer.Each timer expires to produce and interrupts, read the value of counter by timer ISR, and by period computation processor Payload index, it is evident that, only need to carry out difference calculating to day part is up-to-date with the oldest two indexs, then the value of counter is stored in the current location of data buffer, current location is pressed data in graph form and is filled the direction stepping afterwards, with counter O reset, withdraw from ISR at last.As seen, except that the data buffer zone, also need several global variables or data structure 802 to deposit the processor Payload index of day part, calculation procedure directly just can calculate the day part processor utilization fast with the value of these several variablees so when needed.
Next, with reference to Fig. 9 a-9d and in conjunction with above device embodiment and method embodiment, further the solution of the present invention is described, wherein, Fig. 9 a-9d shows the main treatment scheme of technical solution of the present invention.
Fig. 9 a shows the system bootstrap phase process device treatment scheme (corresponding to example 1) of index measurement at full capacity; Fig. 9 a combines with Fig. 9 b and shows the system bootstrap phase process device treatment scheme (corresponding to example 2) of index measurement at full capacity.The treatment scheme (corresponding to example 1) of processor Payload index measurement when Fig. 9 c shows system and normally moves is used to add up the current time processor utilization of certain period in the future.The treatment scheme of processor Payload index measurement when Fig. 9 c combines the system of showing with Fig. 9 d and normally moves is used to add up the processor utilizations of a plurality of periods in current time past.
Shown in Fig. 9 a, when beginning to measure, at first timer is configured to the single timing mode, the cycle is 1 second.Process of measurement is carried out in circulation according to survey mark then, produces bus expection feature, and counter is counted this feature.When timer expires, transmit control signal to PLD, make survey mark be modified, end this measurement.Obtain the value of counter subsequently, derive processor index at full capacity, and preserve standby.
Fig. 9 b shows example 2 is revised survey mark by ISR in the system bootstrap stage treatment scheme.
Fig. 9 c shows the treatment scheme that processor utilization is measured always, disposing timer before measuring is the cycle timing mode, and timing cycle is made as T, promptly 100 milliseconds, start timer then, and be equivalent to be circulation execution process of measurement under the genuine condition forever at survey mark.
Fig. 9 d shows, has no progeny in each timer expires and produces, and timer ISR obtains Counter Value, calculates day part processor Payload index then respectively, and preserves Counter Value, withdraws from ISR after to counter O reset, waits for next time and handling.
Device involved in the present invention all is very common in embedded system, does not need extra hardware investment.And, multi-period measuring method provided by the invention, can show processor utilization by graphical man-machine interface, greatly convenient embedded system especially processor performance is assessed, and determined etc. the important reference of process as system design, processor type selecting, clock frequency.
The above is the preferred embodiments of the present invention only, is not limited to the present invention, and for a person skilled in the art, the present invention can have various changes and variation.Within the spirit and principles in the present invention all, any modification of being done, be equal to replacement, improvement etc., all should be included within protection scope of the present invention.
Claims (11)
1. the measurement mechanism of a processor utilization is characterized in that, comprising:
System bus links to each other with bus monitor, counter and processor;
Described processor is used for the operating measurement program, produces the expection bus characteristic on described system bus, and wherein, described process of measurement is the executable code that sets in advance;
Described bus monitor is used to monitor described system bus, when identifying described expection bus characteristic, produces counter trigger signal;
Described counter under the triggering of the described counter trigger signal that described bus monitor produces, begins counting;
Timer is by being provided with the duration that its timing cycle is provided with the utilization factor statistical time range; And
Interruptable controller is used for producing interrupt trigger signal when the described timing cycle of described timer arrives, and reads the count value of described counter by interrupt service routine;
The calculation procedure module is used for calculating described processor utilization according to the described count value that described interruptable controller reads.
2. the measurement mechanism of processor utilization according to claim 1 is characterized in that, described counter is used as the workload indicator of described processor to the count value of described expection bus characteristic.
3. the measurement mechanism of processor utilization according to claim 2, it is characterized in that, described workload indicator comprises the index of operating at full capacity, current index and the Payload index of operating at full capacity, wherein, the described index of operating at full capacity is the count value of described counter in the system bootstrap stage, the described current index of operating at full capacity obtains by described statistical time range of operating at full capacity index and correspondence, and described Payload index obtains in the count value of the statistical time range of described correspondence by the described current index of operating at full capacity is deducted described counter.
4. the measurement mechanism of processor utilization according to claim 3 is characterized in that, described calculation procedure module is used for that described Payload index and the described current index of operating at full capacity are carried out scale operation and calculates described processor utilization.
5. the measuring method of a processor utilization is characterized in that, comprising:
Step 1 sets in advance the processor process of measurement of index at full capacity;
Step 2 in the system bootstrap stage, is moved described process of measurement, in the given time the full load index of processor is measured, and is read the raw data of the value of counter as described full load index;
Step 3, in system's operational process, measuring the statistical time range of utilization factor, obtaining current full load index, and obtaining the Payload index of described processor according to the value of described current full load index and described counter corresponding to described statistical time range according to described raw data; And
Step 4 is calculated the utilization factor of described processor in the described statistical time range according to described Payload index and described current full load index.
6. the measuring method of processor utilization according to claim 5, it is characterized in that, in described step 3, under the situation that a statistical time range is measured, timer is set to the single timing mode, and timing cycle is the duration of described statistical time range.
7. the measuring method of processor utilization according to claim 5, it is characterized in that, in described step 3, under the situation that a plurality of statistical time ranges are measured, timer is set to the cycle timing mode, and described timer is resetting automatically to after date.
8. the measuring method of processor utilization according to claim 7 is characterized in that, in described step 3, for each statistical time range, the Payload index that it is corresponding leaves in the data buffer.
9. according to the measuring method of each described processor utilization in the claim 5 to 8, it is characterized in that, in described step 4, calculate the utilization factor of described processor by calculation procedure.
10. according to the measuring method of each described processor utilization in the claim 5 to 8, it is characterized in that in described step 3, described Payload index equals value poor of described current full load index and described counter.
11. measuring method according to each described processor utilization in the claim 5 to 8, it is characterized in that, described process of measurement is one section processor executable code, when carrying out described process of measurement, produce the expection bus characteristic, system triggers described counter and begins counting when monitoring described expection bus characteristic.
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| CN 200710106196 CN100501694C (en) | 2007-06-25 | 2007-06-25 | Processor availability measuring device and method |
| PCT/CN2007/003784 WO2009000122A1 (en) | 2007-06-25 | 2007-12-25 | Device and method for measuring the utilization ratio of a processor |
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| CN 200710106196 CN100501694C (en) | 2007-06-25 | 2007-06-25 | Processor availability measuring device and method |
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| EP2018863B9 (en) | 2006-05-16 | 2015-02-18 | Takeda Pharmaceutical Company Limited | Fused heterocyclic compound and use thereof |
| CN100501694C (en) * | 2007-06-25 | 2009-06-17 | 中兴通讯股份有限公司 | Processor availability measuring device and method |
| TW201119285A (en) | 2009-07-29 | 2011-06-01 | Ibm | Identification of underutilized network devices |
| CN102662822B (en) * | 2012-04-26 | 2015-02-04 | 华为技术有限公司 | Load monitoring device and load monitoring method |
| US10216526B2 (en) * | 2015-01-14 | 2019-02-26 | Mediatek Inc. | Controlling method for optimizing a processor and controlling system |
| CN105573885A (en) * | 2015-10-30 | 2016-05-11 | 北京中电华大电子设计有限责任公司 | Method and device for monitoring and counting bottom hardware behaviours |
| CN108809299B (en) * | 2018-08-30 | 2022-07-08 | 歌尔光学科技有限公司 | Signal frequency measurement system |
| CN112540886B (en) * | 2020-11-26 | 2024-07-05 | 北京和利时系统工程有限公司 | CPU load value detection method and device |
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| KR20050101497A (en) * | 2004-04-19 | 2005-10-24 | 삼성전자주식회사 | Apparatus and method for measuring the using rate of cpu |
| US7594128B2 (en) * | 2004-08-04 | 2009-09-22 | Hewlett-Packard Development Company, L.P. | Systems and methods to determine processor utilization |
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