CN100508169C - Method for manufacturing single level polysilicon electric removal and programmable read only memory cell - Google Patents
Method for manufacturing single level polysilicon electric removal and programmable read only memory cell Download PDFInfo
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- CN100508169C CN100508169C CNB2006101084160A CN200610108416A CN100508169C CN 100508169 C CN100508169 C CN 100508169C CN B2006101084160 A CNB2006101084160 A CN B2006101084160A CN 200610108416 A CN200610108416 A CN 200610108416A CN 100508169 C CN100508169 C CN 100508169C
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Abstract
The present invention relates to a method for producing storage cell characterized in depletion type, single layer, polysilicion, electrical erase and programme read only. The method includes the steps as follows: providing a substrate which consists of a floating area and a control area, forming a separated pit area and a pit area respectively in the substrate of the floating area and the control area; next, establishing a well region and a separated well region respectively in the separated pit area and the substrate between the separated pit area and the well region; forming a depletion dope area and a storage cell injecting area respectively in the well area and the pit area; constructing a floating grid which crosses the floating area and the control area on the substrate. Wherein, the floating grid exposes part of the depletion dope area as well as part of the storage cell injecting area; finally, carrying out a technique of doping for the aim of forming a source electrode or drain electrode area and a heavy dope area respectively in the exposed part of the depletion dope area and the storage cell injecting area.
Description
Technical field
The present invention relates to a kind of Nonvolatile storage unit, its formation method and method of operation, and particularly relate to a kind of single level polysilicon electric removal and programmable read only memory cell (single-poly EEPROM cell), its manufacture method with and method of operation.
Background technology
Along with the booming influence of consumption electronic products, under the state of power-off, the non-volatility memorizer (non-volatile memory) that still can keep stored data and data, be widely used in the various electronic installations, comprise multimedia or portable multimedia application apparatus, for example digital camera, walkman or portable telephone etc.And,, become one of trend of present manufacturing development for example with CMOS (Complementary Metal Oxide Semiconductor), logic element, high voltage device and low voltage component integrated process with non-volatility memorizer and other element integrated process.
But existingly can remove program read-only memory (Electrically Erasable ProgrammableRead-Only Memory by electricity; EEPROM), be a kind of non-volatility memorizer.General EEPROM born of the same parents have the grid of two mutual storehouses, comprise with polysilicon (poly-silicon) made being used for the floating grid of store charge, and are used for the polysilicon control grid of control data access.Wherein floating grid is in the state of " floating " usually, is not connected with any circuit, and the then common and word line of control gate joins.And control gate is stacked on the floating grid, and between control gate and floating grid with a dielectric layer electrical isolation each other.
But can remove the polysilicon gate that program read-only memory has two mutual storehouses by electricity owing to existing, its ladder height (step height) is greater than in the ladder height of other single level polysilicon element, but therefore increased the difficulty of can electricity removing on program read-only memory and other element integrated process.In addition, but for the integrated process two-layer polysilicon can remove program read-only memory and single level polysilicon element by electricity, the photomask of required use is more, and processing step is also comparatively complicated.
Summary of the invention
Purpose of the present invention is exactly in the manufacture method that a kind of depletion type (or claiming vague and general type) single level polysilicon electric removal and programmable read only memory cell is provided, and can make single level polysilicon electric removal and programmable read only memory cell and high voltage device integrated process.
Another purpose of the present invention provides a kind of depletion type single level polysilicon electric removal and programmable read only memory cell, has wider operating voltage range, therefore is easy to be bumped in other element.
A further object of the present invention provides a kind of method for programming of depletion type single level polysilicon electric removal and programmable read only memory cell, can obtain preferred sequencing stability.
Another object of the present invention provides a kind of erasing method of depletion type single level polysilicon electric removal and programmable read only memory cell, so that preferably erasing result to be provided.
The present invention proposes a kind of formation method of depletion type single level polysilicon electric removal and programmable read only memory cell.The method comprises: the substrate with a floating region and a controlled area is provided, isolates a deep-well region and a deep-well region respectively at forming one in this substrate of this floating region and this controlled area, wherein this isolation deep-well region and this deep-well region have the identical conduction type.Afterwards, isolate in the deep-well region, and be somebody's turn to do in this substrate of isolating between deep-well region and this deep-well region, form a well region and an isolation well region respectively in this.Form one respectively at the surface of this substrate of the surface of this substrate of this well region and this deep-well region and exhaust a doped region and a memory cell injection region.In this substrate, form a floating grid structure across this floating region and this controlled area, wherein this floating grid structure respectively exposed part this exhaust doped region with the part this memory cell injection region, and this floating grid structure comprises that dielectric layer and is worn dielectric layer then between a floating grid, grid, and dielectric layer is between this memory cell injection region and this floating grid between these grid, and this wears then that dielectric layer exhausts between doped region and this floating grid at this.At last, carry out a doping process with respectively at forming a source and a heavily doped region in exposed part depletion doped region and the exposed partial memory cell injection region.
According to the formation method of the described depletion type single level polysilicon of embodiments of the invention electric removal and programmable read only memory cell, wherein form this method that exhausts doped region and this memory cell injection region and comprise and carry out electric current injection technology in (medium current implantation process).And implant energy of electric current injection technology is about 90～140keV in this.
Formation method according to the described depletion type single level polysilicon of embodiments of the invention electric removal and programmable read only memory cell, the method that wherein forms this floating grid structure comprises: before this exhausts doped region and this memory cell injection region in formation, form one first dielectric layer in this substrate.And after this exhausts doped region and this memory cell injection region in formation, remove this first dielectric layer of part to expose this substrate of this floating region.Afterwards, form one second dielectric layer in this substrate of this floating region, wherein one first thickness of this first dielectric layer is greater than one second thickness of this second dielectric layer.Form a conductive layer in this substrate top.At last, this conductive layer of patterning, this first dielectric layer and this second conductive layer are to form between this floating grid, these grid dielectric layer respectively and this wears dielectric layer then.Above-mentioned first thickness is about 100～1000 dusts, and second thickness is about 80～120 dusts.Again, this substrate also comprises a high voltage device district and a low voltage component district, and remove this first dielectric layer partly and also comprise this substrate that exposes this low voltage component district when exposing this substrate of this floating region, and remaining this first dielectric layer is arranged in this substrate in this controlled area and this high voltage device district.In addition in said method, after forming this second dielectric layer, also comprise and remove this second dielectric layer of part to expose this substrate in this low voltage component district, afterwards before forming this conductive layer, in this substrate in this low voltage component district, form one the 3rd dielectric layer, wherein one the 3rd thickness of the 3rd dielectric layer is less than this second thickness.In addition, in the time of this conductive layer of patterning, also comprise: form a high pressure grid and a low pressure grid respectively at this substrate top in this high voltage device district and this substrate top in this low voltage component district.Again, this floating region and this controlled area are arranged in this high voltage device district.
The present invention proposes a kind of depletion type single level polysilicon electric removal and programmable read only memory cell again, and it is positioned in the substrate, and this substrate has an adjacent floating region and a controlled area.This depletion type single level polysilicon electric removal and programmable read only memory cell comprises: an isolation deep-well region, a deep-well region, a well region, a floating grid, source, a heavily doped region, exhaust a doped region and a memory cell injection region.Isolate this substrate that deep-well region is arranged in this floating region, deep-well region then is arranged in this substrate of this controlled area, and well region is arranged in this isolation deep-well region, and this isolation deep-well region and this deep-well region have the identical conduction type.Floating grid is positioned in this substrate, and across this floating region and this controlled area, and this well region of exposed part and this deep-well region.Source/drain regions is arranged in this substrate of the well region that should expose of these floating grid both sides.Heavily doped region is arranged in this substrate of the deep-well region that should expose of this floating grid one side, and exhaust doped region below this wears dielectric layer then and in this substrate between this source/drain regions, wherein this conduction type that exhausts doped region is identical with the conduction type of this source/drain regions.The memory cell injection region is arranged in this substrate of the below of dielectric layer between these grid and adjacent this heavily doped region one side.
According to the described depletion type single level polysilicon of embodiments of the invention electric removal and programmable read only memory cell, wherein the conduction type of this isolation deep-well region is identical with the conduction type that this exhausts doped region.
According to the described depletion type single level polysilicon of embodiments of the invention electric removal and programmable read only memory cell, wherein the conduction type of this heavily doped region is identical with the conduction type of this memory cell injection region.
According to the described depletion type single level polysilicon of embodiments of the invention electric removal and programmable read only memory cell, wherein the conduction type of this heavily doped region is identical with the conduction type of this deep-well region.
According to the described depletion type single level polysilicon of embodiments of the invention electric removal and programmable read only memory cell, wherein have between this floating grid and this well region and wear dielectric layer then.The thickness of this tunneling dielectric layer is about 80～120 dusts.
According to the described depletion type single level polysilicon of embodiments of the invention electric removal and programmable read only memory cell, wherein has dielectric layer between grid between this floating grid and this deep-well region.The thickness of dielectric layer is about 100～1000 dusts between these grid.
According to the described depletion type single level polysilicon of embodiments of the invention electric removal and programmable read only memory cell, wherein this floating region and this controlled area are arranged in a high voltage device district of this substrate.
The present invention reintroduces a kind of method for programming of depletion type single level polysilicon electric removal and programmable read only memory cell.This method comprises: a depletion type single level polysilicon electric removal and programmable read only memory cell is provided, carry out one Fu Le-Nuo Dehan afterwards and wear this depletion type single level polysilicon electric removal and programmable read only memory cell of (Fowler-Nordheim tunneling, F-N tunneling) mode sequencing then.And depletion type single level polysilicon electric removal and programmable read only memory cell is positioned in the substrate, this substrate comprises a floating region and a controlled area, and this depletion type single level polysilicon electric removal and programmable read only memory cell also comprises: a floating grid, source, a control deep-well region and a heavily doped region.Floating grid is positioned in this substrate of this floating region and this controlled area, and source/drain regions is arranged in this substrate of these floating grid both sides of this floating region, and wherein this floating grid and this source/drain regions are formed a depletion type memory cell.The control deep-well region is arranged in this controlled area, and wherein this floating grid covers partly and should control deep-well region.Heavily doped region is arranged in this substrate of this floating grid one side of this control deep-well region of this controlled area.
Method for programming according to the described depletion type single level polysilicon of embodiments of the invention electric removal and programmable read only memory cell, wherein this Fu Le-Nuo Dehan wear then this depletion type single level polysilicon electric removal and programmable read only memory cell of mode sequencing can be by applying a voltage on this substrate in this floating region and this heavily doped region, and this control deep-well region and this source/drain regions ground connection are reached.And this voltage is about 10～20 volts.
According to the method for programming of the described depletion type single level polysilicon of embodiments of the invention electric removal and programmable read only memory cell, wherein this floating region and this controlled area are in the high voltage device district in this substrate.
The present invention also proposes a kind of erasing method of depletion type single level polysilicon electric removal and programmable read only memory cell.The method comprises: a depletion type single level polysilicon electric removal and programmable read only memory cell is provided, carries out one Fu Le-Nuo Dehan afterwards and wear this depletion type single level polysilicon electric removal and programmable read only memory cell of erasing of mode then.And depletion type single level polysilicon electric removal and programmable read only memory cell is positioned in the substrate, this substrate comprises a floating region and a controlled area, and this depletion type single level polysilicon electric removal and programmable read only memory cell also comprises: a floating grid, source, a control deep-well region and a heavily doped region.Floating grid is positioned in this substrate of this floating region and this controlled area, and source/drain regions is arranged in this substrate of these floating grid both sides of this floating region, and wherein this floating grid and this source/drain regions are formed a depletion type memory cell.The control deep-well region is arranged in this controlled area, and wherein this floating grid covers partly and should control deep-well region.Heavily doped region is arranged in this substrate of this floating grid one side of this control deep-well region of this controlled area.
Erasing method according to the described depletion type single level polysilicon of embodiments of the invention electric removal and programmable read only memory cell, wherein this Fu Le-Nuo Dehan wear then this depletion type single level polysilicon electric removal and programmable read only memory cell of erasing of mode can be by on this source/drain regions, applying a voltage, and this substrate and this heavily doped region ground connection in this floating region are reached.And this voltage is about 9～12 volts.In addition, carry out this Fu Le-Nuo Dehan and wear then the step of this depletion type single level polysilicon electric removal and programmable read only memory cell of erasing of mode and also be included on this control deep-well region and apply this voltage, and this voltage is about 9～20 volts.
According to the erasing method of the described depletion type single level polysilicon of embodiments of the invention electric removal and programmable read only memory cell, wherein this floating region and this controlled area are in the high voltage device district in this substrate.
In the present invention, owing to the control gate of deep-well region/control deep-well region as electric removal and programmable read only memory cell, therefore electric removal and programmable read only memory cell shape of the present invention only has the single level polysilicon layer.Therefore can reduce the integration difficulty of electric removal and programmable read only memory cell and other single level polysilicon element.The method according to this invention, depletion type single level polysilicon electric removal and programmable read only memory cell can with the high voltage device integrated process.In addition, the transistor of the floating grid of depletion type single level polysilicon electric removal and programmable read only memory cell of the present invention is the depletion type memory cell, therefore can effectively reduce the starting voltage of electric removal and programmable read only memory cell and the voltage of erasing, and can make electric removal and programmable read only memory cell have wider voltage-operated scope, be beneficial to electric removal and programmable read only memory cell and be inlaid in logic, hybrid circuit or the high voltage device technology.
For above and other objects of the present invention, feature and advantage can be become apparent, preferred embodiment cited below particularly, and conjunction with figs. are described in detail below.
Description of drawings
Figure 1A to Fig. 1 D illustrate a kind of depletion type single level polysilicon electric removal and programmable read only memory cell according to one preferred embodiment of the present invention the formation method on look sketch.
Fig. 2 A to Fig. 2 D is respectively the diagrammatic sectional view of Figure 1A to Fig. 1 D along line I-I and line II-II.
Fig. 3 illustrates the method for programming of a kind of depletion type single level polysilicon electric removal and programmable read only memory cell according to one preferred embodiment of the present invention.
Fig. 4 illustrates the erasing method of a kind of depletion type single level polysilicon electric removal and programmable read only memory cell according to one preferred embodiment of the present invention.
The simple symbol explanation
100: substrate
100a: floating region
100b: controlled area
100c: high voltage device district
100d: low voltage component district
102: isolation structure
104a: isolate deep-well region
104b, 104c, 104d: deep-well region
106a: well region
106b: isolation well region
108,108a: first dielectric layer
108b: dielectric layer between grid
108c: high pressure gate dielectric
110a: exhaust doped region
110b: memory cell injection region
112: the second dielectric layers
112a: wear dielectric layer then
114: the three dielectric layers
114a: low pressure gate dielectric
116a: floating grid
116b: high pressure grid
116c: low pressure grid
118a: source/drain regions
118b: heavily doped region
118c: high voltage device source/drain regions
118d: low voltage component source/drain regions
120: the depletion type memory cell
S301～S303: programming operations flow process
S401～S403: erasing operating process
Embodiment
Figure 1A to Fig. 1 D illustrate a kind of depletion type single level polysilicon electric removal and programmable read only memory cell according to one preferred embodiment of the present invention the formation method on look sketch.Fig. 2 A to Fig. 2 D is respectively the diagrammatic sectional view of Figure 1A to Fig. 1 D along line I-I and line II-II.
Please refer to Figure 1A and Fig. 2 A, a substrate 100 is provided, wherein this substrate 100 has a floating region 100a and a controlled area 100b.It should be noted that floating region 100a and controlled area 100b all are arranged in a high voltage device district 100c of substrate 100.In addition, substrate 100 also comprises a low voltage component district 100d except high voltage device district 100c.All isolate mutually between each element region in the substrate 100 with an isolation structure 102 again.This isolation structure 102 for example is a fleet plough groove isolation structure.
Afterwards, isolate a deep-well region 104a and a deep-well region 104b respectively at forming one in the substrate 100 of floating region 100a and controlled area 100b.Because depletion type single level polysilicon electric removal and programmable read only memory cell of the present invention is to be formed among the high voltage device district 100c of substrate 100, therefore must be in the substrate 100 of floating region 100a, form to isolate deep-well region 104a with the high voltage device (not illustrating) that reduces high voltage device district 100c when the operation with high pressure, in influence at the depletion type single level polysilicon electric removal and programmable read only memory cell of floating region mesolow operation.In addition, it is different to isolate the conduction type of the conduction type of deep-well region 104a and deep-well region 104b and substrate 100.Again, form when isolating deep-well region 104a and deep-well region 104b in the substrate 100 in floating region 100a and controlled area 100b, also be included among low voltage component district 100d and floating region 100a and the controlled area 100b high voltage device district 100c in addition and form deep-well region 104d and 104c.Same, the conduction type of deep- well region 104c and 104d is different with the conduction type of substrate 100.
Follow in isolation deep-well region 104a, and in the substrate 100 between isolation deep-well region 104a and the deep-well region 104b, form a well region 106a and an isolation well region 106b respectively.Wherein, but the conduction type of well region 106a and isolation well region 106b is identical different with the conduction types of isolating deep-well region 104a and deep-well region 104b with substrate 100.Afterwards, in substrate 100, form one first dielectric layer 108.The material of this first dielectric layer 108 comprises silica, and the method that forms first dielectric layer 108 comprises chemical vapour deposition technique.The thickness of other first dielectric layer 108 is about 100～1000 dusts.
Please refer to Figure 1B and Fig. 2 B, carry out a doping process, form one with surface and exhaust a doped region 110a and a memory cell injection region 110b respectively at the substrate 100 of the surface of the substrate 100 of well region 106a and deep-well region 104b.The method of carrying out above-mentioned doping process for example is to form a patterning photoresist layer (not illustrating) prior to substrate 100 tops, to expose the predetermined part of first dielectric layer 108 that forms part substrate 100 tops that exhaust doped region 110a and memory cell injection region 110b, carry out an ion doping technology afterwards, exhaust doped region 110a and memory cell injection region 110b to form in the substrate 100 in well region 106a and deep-well region 104b.Above-mentioned ion doping technology for example is electric current injection technology in, and implant energy of electric current injection technology is about 90～140keV in this.
In the foregoing description, doping process exhausts doped region 110a with formation and memory cell injection region 110b carries out after first dielectric layer 108 forms.Yet in practical application, the present invention is not limited to above-mentioned sequence of process steps, and just above-mentioned doping process can carry out exhausting doped region 110a and memory cell injection region 110b to form before first dielectric layer 108 forms in substrate 100.
Afterwards, please refer to Fig. 1 C and Fig. 2 C, carry out an etch process to remove first dielectric layer 108 partly and to expose substrate 100 surfaces among the floating region 100a and substrate 100 surfaces among the low voltage component district 100d.Just, the first dielectric layer 108a that is not removed is positioned at controlled area 100b and they are on substrate 100 surfaces of high voltage device district 100c.Afterwards, in the substrate 100 of well region 106a, form one second dielectric layer 112.The material of this second dielectric layer 112 for example is a silica, and the method that forms second dielectric layer 112 comprises chemical vapour deposition technique, and its thickness is about 80～120 dusts.It should be noted that the thickness of the thickness of the first dielectric layer 108a wherein greater than second dielectric layer 112.Afterwards, remove this second dielectric layer 112 of part to expose substrate 100 surfaces of low voltage component district 100d.Continue it, in the substrate 100 in low voltage component district 100d, form one the 3rd dielectric layer 114, wherein the 3rd dielectric layer 114 thickness are less than second dielectric layer 112.The material of this 3rd dielectric layer 114 for example is a silica, and the method that forms the 3rd dielectric layer 114 comprises chemical vapour deposition technique.
In addition, when substrate 100 also comprises a logic element district (not illustrating), in the substrate 100 of low voltage component district 100d, form after the 3rd dielectric layer 114, also comprise removing and be arranged in logic element district substrate 100 lip-deep the 3rd dielectric layers 114, then form one the 4th dielectric layer (not illustrating) in the substrate 100 in logic element district, the thickness of this 4th dielectric layer is about 60～70 dusts.
It should be noted that, form second dielectric layer 112 and the 3rd dielectric layer 114, even the method for the 4th dielectric layer for example is directly to form second dielectric layer 112 in the first dielectric layer 108a and substrate 100, remove partly second dielectric layer 112 afterwards to expose substrate 100 surfaces of low voltage component district 100d, then on second dielectric layer 112 in floating region 100a, formation the 3rd dielectric layer 114 in the substrate 100 of the first dielectric layer 108a of controlled area 100b and high voltage device district 100c and low voltage component district 100d.At last, remove the storehouse dielectric layer that is arranged in logic element district substrate 100 surfaces, be to form on the substrate surface 100 in the logic element district the 4th dielectric layer.Just, according to the practical application needs of each element region, each element region in substrate 100 forms thickness dielectric layer from thick to thin in regular turn.
Afterwards, please refer to Fig. 1 D and Fig. 2 D, form a conductive layer (not illustrating) in substrate 100 tops, the material of this conductive layer for example is a polysilicon.Patterned conductive layer, the first dielectric layer 108a, second conductive layer 112 and the 3rd dielectric layer 114 are to go up formation one floating grid structure in floating region 100a and controlled area 100b, form the high pressure grid structure in high voltage device district 100c, form the low pressure grid structure in low voltage component district 100d afterwards.Just, make conductive layer pattern turn to a floating grid 116a across floating region 100a and controlled area 100b, be positioned at the high pressure grid 116b and a low pressure grid 116c who is positioned at low voltage component district 100d of high voltage device district 100c, the first dielectric layer 108a then is patterned as a dielectric layer 108b and a high pressure gate dielectric 108c who is positioned at all the other high voltage device district 100c between grid that are positioned at controlled area 100b.112 of second dielectric layers are patterned as one and wear dielectric layer 112a then, and 114 of the 3rd dielectric layers are patterned as low pressure gate dielectric 114a.Wherein floating grid 116a is positioned at floating region 100a and controlled area 100b.In floating region 100a, floating grid 116a cover part substrate 100, and exhaust doped region 110a in the both sides of floating grid 116a exposed part.Again, in the 100b of controlled area, floating grid 116a cover part substrate 100, and in the side exposed part memory cell injection region 110b of floating grid 116a.Dielectric layer 108b is between memory cell injection region 110b and floating grid 116a between grid, and dielectric layer 112a is exhausting between doped region 110a and the floating grid 116a and wear then.
Continue it, carry out a doping process with respectively at forming a source 118a and a heavily doped region 118b among exposed part depletion doped region 110a and the exposed partial memory cell injection region 110b.Just source/drain regions 118a is arranged in the well region 106a of substrate 100 of the floating region 100a of floating grid 116a both sides, and heavily doped region 118b is arranged in the deep-well region 104b of substrate 100 of the controlled area 100b of floating grid 116a one side.In addition, when forming source/drain regions 118a and heavily doped region 118b, in all the other of high voltage device district 100c partly and among the low voltage component district 100d, formation high voltage device source/drain regions 118c and low voltage component source/drain regions 118d in the substrate 100 of being exposed respectively at high pressure grid 116b and low pressure grid 116c.Conduction type that it should be noted that source/drain regions 118a is identical with the conduction type that exhausts doped region 110a.Be a depletion type memory cell just in the memory cell 120 (shown in Fig. 2 D) that forms in the substrate among the floating region 100a 100.In addition, the conduction type of heavily doped region 118b is identical with the conduction type of memory cell injection region 110b.Again, the ion doping concentration of source/drain regions 118a is greater than the ion doping concentration that exhausts doped region 110a.Same, the ion doping concentration of heavily doped region 118b is greater than the ion doping concentration of memory cell injection region 110b.
Below will describe structure in detail with Fig. 1 D and Fig. 2 D according to a depletion type single level polysilicon electric removal and programmable read only memory cell of the present invention.Please refer to Fig. 1 D and Fig. 2 D, depletion type single level polysilicon electric removal and programmable read only memory cell of the present invention is positioned in the substrate 100 with first conduction type, and this substrate 100 has adjacent floating region 100a and controlled area 100b.In addition, this substrate 100 also comprises high voltage device district 100c and low voltage component district 100d, and wherein above-mentioned floating region 100a and controlled area 100b all are arranged in high voltage device district 100c.Depletion type single level polysilicon electric removal and programmable read only memory cell also comprises isolation deep-well region 104a and the deep-well region 104b that has second conduction type respectively.Isolate the substrate 100 that deep-well region 104a is arranged in floating region 100a, and deep-well region 104b is arranged in the substrate 100 of controlled area 100b.Have identical conduction type owing to isolate deep-well region 104a with deep-well region 104b, so isolate deep-well region 104a and deep-well region 104b can form in same doping process.Again, because depletion type single level polysilicon electric removal and programmable read only memory cell of the present invention is to be made among the high voltage device district 100c, therefore when forming isolation deep-well region 104a and deep-well region 104b, it is required also simultaneously partly to form high voltage device in other of high voltage device district 100c, and with isolate the identical deep-well region 104c of deep-well region 104a conduction type.Identical, the substrate 100 in low voltage component district 100d, it is required also can to form low voltage component simultaneously, and with isolate the identical deep-well region 104d of deep-well region conduction type.
In addition, depletion type single level polysilicon electric removal and programmable read only memory cell comprises well region 106a and the isolation well region 106b that has first conduction type respectively.Well region 106a is arranged in and isolates deep-well region 104a, and isolation well region 106b then is positioned at and isolates deep-well region 104a, deep- well region 104b, 104c and 104d each other, as the purposes of isolating.Because well region 106a is identical with the conduction type of isolation well region 106b, so well region 106a and isolation well region 106b can be formed in the substrate 100 in same doping process.
Again, depletion type single level polysilicon electric removal and programmable read only memory cell comprises floating grid 116a.This floating grid 116a is positioned in the substrate 100, and across floating region 100a and controlled area 100b, wherein have between the well region 106a of floating grid 116a and floating region 100a and wear dielectric layer 112a then, and have dielectric layer 108b between grid between the deep-well region 104b of floating grid 116a and controlled area 100b.And the thickness of tunneling dielectric layer 112a is about 80～120 dusts, and the thickness of dielectric layer 108b is about 100～1000 dusts between grid.Therefore the method that forms dielectric layer 108b between floating grid 106a, tunneling dielectric layer 112a and grid does not give unnecessary details at this described in embodiment before.
Moreover depletion type single level polysilicon electric removal and programmable read only memory cell comprises source/drain regions 118a and the heavily doped region 118b that has second conduction type respectively.Wherein, source/drain regions 118a is arranged in the substrate 100 of the well region 106a of floating region 100a floating grid 116a both sides.Heavily doped region 118b then is arranged in the substrate 100 of the deep-well region 104b of controlled area 100b floating grid 116a one side.In addition, in the substrate 100 of wearing between dielectric layer 112a below then and the source/drain regions 118a, also comprise have second conduction type exhaust doped region 110a.In addition, between grid, in the substrate 100 of dielectric layer 108b below and adjacent heavily doped region 118b, comprise memory cell injection region 110b with second conduction type.
It should be noted that the conduction type of the source/drain regions 118a in the well region 106a of floating region 100a is identical with the conduction type that exhausts doped region 110a between the source/drain regions 118a.Therefore, by floating grid 116a, tunneling dielectric layer 112a, source/drain regions 118a and exhaust doped region 110a and jointly forms depletion type memory and distinguish 120.In addition, because depletion type single level polysilicon electric removal and programmable read only memory cell of the present invention is arranged in high voltage device district 100c, therefore in floating region 100a, be provided with and have and substrate 100 different conduction-types, but isolation deep-well region 104a with source/drain regions identical conduction type, the high voltage device that can prevent high voltage device district 100c is finished drilling when doing in high pressure (about 30 volts), interferes with in low voltage operated depletion type single level polysilicon electric removal and programmable read only memory cell.Just isolate the depletion type single level polysilicon electric removal and programmable read only memory cell high voltage device peripheral with it to isolate deep-well region 104a.Again, in the substrate 100 of controlled area 100b, dispose the heavily doped region 118b that has with deep-well region 104b and memory cell injection region 110b identical conduction type, can reduce well region impedance (well resistance) as the deep-well region 104b of control gate, raising is as the capacitance of the deep-well region 104b of control gate, reduce parasitic capacitance, improve the usefulness of sequencing-erasing.
Fig. 3 illustrates the method for programming of a kind of depletion type single level polysilicon electric removal and programmable read only memory cell according to one preferred embodiment of the present invention.Please refer to Fig. 3 and Fig. 2 D, this method for programming comprises, in step S301, provides a depletion type single level polysilicon electric removal and programmable read only memory cell.Wherein, depletion type single level polysilicon electric removal and programmable read only memory cell is positioned in the substrate 100, and this substrate 100 more comprises floating region 100a and controlled area 100b.In addition, depletion type single level polysilicon electric removal and programmable read only memory cell also comprises in the substrate that is arranged in floating region 100a and controlled area 100b 100 floating grid 116a, is arranged in the source/drain regions 118a of floating region 100a floating grid 116a substrate on two sides 100, is arranged in the deep-well region 104b of this controlled area 100b, and the heavily doped region 118b of substrate 100 that is arranged in deep-well region 104b floating grid 116a one side of controlled area 100b.Wherein one of deep-well region 104b that is depletion type single level polysilicon electric removal and programmable read only memory cell control deep-well region, and floating grid 116a covers partly controls deep-well region 104b.Again, floating grid 116a and source/drain regions 118a form a depletion type memory cell 120.
In addition, because depletion type single level polysilicon electric removal and programmable read only memory cell of the present invention is arranged among the high voltage device district 100c, therefore above-mentioned depletion type memory cell 120 is to be arranged among the well region 106a, and well region 106a isolates deep-well region 104a with one to isolate mutually with high voltage device on every side.Just isolate deep-well region 104a and surround well region 106a, and the source/drain regions 118a of depletion type memory cell 120 is arranged among the well region 106a, and substrate 100 is first conduction type with the conduction type of well region 106a, and the conduction type of isolation deep-well region 104a and source/drain regions 118a is second conduction type.In addition, the conduction type of control deep-well region 104b and heavily doped region 118b is second conduction type.
Continue it, please refer to Fig. 3 and Fig. 2 D, in step S303, carry out one Fu Le-Nuo Dehan and wear (Fowler-Nordheim tunneling, F-N tunneling) above-mentioned depletion type single level polysilicon of mode sequencing electric removal and programmable read only memory cell then.When first conduction type is the P type, and during the second electrical conductive behavior N type, can be through owing to apply a voltage on the substrate 100 of the well region 106a of floating region 100a and the heavily doped region 118b, and make the control deep-well region 104b of controlled area 100b and source/drain regions 118a ground connection carry out above-mentioned F-N to wear tunnel mode programming operations.What deserves to be mentioned is, in the time of will controlling deep-well region 104b ground connection and wear tunnel mode programming operations, also can isolate deep-well region 104a ground connection simultaneously to carry out F-N.Under above-mentioned shape condition, wherein applied voltage is about 10～20 volts.
Fig. 4 illustrates the erasing method of a kind of depletion type single level polysilicon electric removal and programmable read only memory cell according to one preferred embodiment of the present invention.Please refer to Fig. 4 and Fig. 2 D, similar to programming operations, in step S401, one depletion type single level polysilicon electric removal and programmable read only memory cell is provided earlier, therefore the structure of this depletion type single level polysilicon electric removal and programmable read only memory cell and arrangements of components do not give unnecessary details at this as embodiment is described before.In step S403, carry out a F-N and wear the above-mentioned depletion type single level polysilicon of erasing of tunnel mode electric removal and programmable read only memory cell afterwards.When first conduction type is the P type, and during the second electrical conductive behavior N type, can be via on source/drain regions 118a, applying a voltage, and make the substrate 100 and heavily doped region 118b ground connection of the well region 106a of floating region 100a, carry out above-mentioned F-N and wear the operation of erasing of tunnel mode.Wherein above-mentioned applied voltage is about 9～12 volts.On the other hand, F-N wear the operation of erasing of tunnel mode can also by apply simultaneously an applied voltage in control deep-well region 104b, isolate on deep-well region 104a and the source/drain regions 118a, and substrate 100 and the heavily doped region 118b of ground connection well region 106a reach.Wherein, above-mentioned applied voltage is about 9～20 volts.
In the present invention,, therefore form the electric removal and programmable read only memory cell that only has single level polysilicon (floating grid just) by the control gate of the deep-well region 104b among the 100b of controlled area as electric removal and programmable read only memory cell.Therefore can reduce electric removal and programmable read only memory cell and other single level polysilicon element, for example the integration difficulty of high voltage device, low voltage component and logic element.The method according to this invention, depletion type single level polysilicon electric removal and programmable read only memory cell can with the high voltage device integrated process, and by isolating deep-well region depletion type single level polysilicon electric removal and programmable read only memory cell and high voltage device are on every side isolated, can prevent that therefore high voltage device and depletion type single level polysilicon electric removal and programmable read only memory cell from influencing each other when operation.
In addition, the transistor of the floating grid of depletion type single level polysilicon electric removal and programmable read only memory cell of the present invention is the depletion type memory cell, therefore can effectively reduce the starting voltage of electric removal and programmable read only memory cell and the voltage of erasing, and can make electric removal and programmable read only memory cell have wider voltage-operated scope, be beneficial to electric removal and programmable read only memory cell and be inlaid in logic, hybrid circuit or the high voltage device technology.In addition, method of the present invention can be easy to electric removal and programmable read only memory cell of the present invention and time complementary metal oxide semiconductor element integrated process of micron.
The present invention is not limited to above preferred embodiment.The various modifications and variations that those skilled in the art is done on this basis all should belong to protection scope of the present invention.
Claims (29)
1. the formation method of a depletion type single level polysilicon electric removal and programmable read only memory cell comprises:
Substrate is provided, and wherein this substrate has floating region and controlled area;
Isolate deep-well region and deep-well region respectively at forming in this substrate of this floating region and this controlled area, wherein this isolation deep-well region and this deep-well region have the identical conduction type;
Isolate in the deep-well region in this, and be somebody's turn to do in this substrate of isolating between deep-well region and this deep-well region, form well region and isolation well region respectively;
Form respectively at the surface of this substrate of the surface of this substrate of this well region and this deep-well region and to exhaust doped region and memory cell injection region;
In this substrate, form floating grid structure across this floating region and this controlled area, wherein this floating grid structure respectively exposed part this exhaust doped region with the part this memory cell injection region, and this floating grid structure comprises that dielectric layer and is worn dielectric layer then between a floating grid, grid, and dielectric layer is between this memory cell injection region and this floating grid between these grid, and this wears then that dielectric layer exhausts between doped region and this floating grid at this; And
Carry out doping process with respectively at forming source/drain regions and heavily doped region in exposed part depletion doped region and the exposed partial memory cell injection region.
2. the formation method of depletion type single level polysilicon electric removal and programmable read only memory cell as claimed in claim 1, wherein form this method that exhausts doped region and this memory cell injection region comprise carry out in the electric current injection technology.
3. the formation method of depletion type single level polysilicon electric removal and programmable read only memory cell as claimed in claim 2, the implant energy of electric current injection technology is 90～140keV in wherein being somebody's turn to do.
4. the formation method of depletion type single level polysilicon electric removal and programmable read only memory cell as claimed in claim 1, the method that wherein forms this floating grid structure comprises:
Before this exhausts doped region and this memory cell injection region in formation, in this substrate, form first dielectric layer;
After this exhausts doped region and this memory cell injection region in formation, remove this first dielectric layer of part to expose this substrate of this floating region;
Form second dielectric layer in this substrate of this floating region, wherein first thickness of this first dielectric layer is greater than second thickness of this second dielectric layer;
Form a conductive layer in this substrate top; And
This conductive layer of patterning, this first dielectric layer and this second conductive layer are to form between this floating grid, these grid dielectric layer respectively and this wears dielectric layer then.
5. the formation method of depletion type single level polysilicon electric removal and programmable read only memory cell as claimed in claim 4, wherein this first thickness is 100～1000 dusts.
6. the formation method of depletion type single level polysilicon electric removal and programmable read only memory cell as claimed in claim 4, wherein this second thickness is 80～120 dusts.
7. the formation method of depletion type single level polysilicon electric removal and programmable read only memory cell as claimed in claim 4, wherein this substrate also comprises high voltage device district and low voltage component district, and remove this first dielectric layer partly and also comprise this substrate that exposes this low voltage component district when exposing this substrate of this floating region, and remaining this first dielectric layer is arranged in this substrate in this controlled area and this high voltage device district.
8. the formation method of depletion type single level polysilicon electric removal and programmable read only memory cell as claimed in claim 7 also comprises:
After forming this second dielectric layer, remove this second dielectric layer of part to expose this substrate in this low voltage component district; And
Before forming this conductive layer, in this substrate in this low voltage component district, form the 3rd dielectric layer, wherein the 3rd thickness of the 3rd dielectric layer is less than this second thickness.
9. the formation method of depletion type single level polysilicon electric removal and programmable read only memory cell as claimed in claim 7, wherein this conductive layer of patterning the time, also comprise: form high pressure grid and low pressure grid respectively at this substrate top in this high voltage device district and this substrate top in this low voltage component district.
10. the formation method of depletion type single level polysilicon electric removal and programmable read only memory cell as claimed in claim 7, wherein this floating region and this controlled area are arranged in this high voltage device district.
11. a depletion type single level polysilicon electric removal and programmable read only memory cell is positioned in the substrate, this substrate has adjacent floating region and controlled area, and this depletion type single level polysilicon electric removal and programmable read only memory cell comprises:
Isolate deep-well region, be arranged in this substrate of this floating region;
Deep-well region is arranged in this substrate of this controlled area, and wherein this isolation deep-well region and this deep-well region have the identical conduction type;
Well region is arranged in this isolation deep-well region;
Floating grid is positioned in this substrate, and across this floating region and this controlled area, and this well region of exposed part and this deep-well region;
Source/drain regions is arranged in this substrate of the well region that should expose of these floating grid both sides;
Heavily doped region is arranged in this substrate of the deep-well region that should expose of this floating grid one side;
Exhaust doped region, below this wears dielectric layer then and in this substrate between this source/drain regions, wherein this conduction type that exhausts doped region is identical with the conduction type of this source/drain regions; And
The memory cell injection region is arranged in this substrate of the below of dielectric layer between these grid and adjacent this heavily doped region one side.
12. depletion type single level polysilicon electric removal and programmable read only memory cell as claimed in claim 11, wherein the conduction type of this isolation deep-well region is identical with the conduction type that this exhausts doped region.
13. depletion type single level polysilicon electric removal and programmable read only memory cell as claimed in claim 11, wherein the conduction type of this heavily doped region is identical with the conduction type of this memory cell injection region.
14. depletion type single level polysilicon electric removal and programmable read only memory cell as claimed in claim 11, wherein the conduction type of this heavily doped region is identical with the conduction type of this deep-well region.
15. depletion type single level polysilicon electric removal and programmable read only memory cell as claimed in claim 11 wherein has between this floating grid and this well region and wears dielectric layer then.
16. depletion type single level polysilicon electric removal and programmable read only memory cell as claimed in claim 15, wherein the thickness of this tunneling dielectric layer is 80～120 dusts.
17. depletion type single level polysilicon electric removal and programmable read only memory cell as claimed in claim 11 wherein has dielectric layer between grid between this floating grid and this deep-well region.
18. depletion type single level polysilicon electric removal and programmable read only memory cell as claimed in claim 17, wherein the thickness of dielectric layer is 100～1000 dusts between these grid.
19. depletion type single level polysilicon electric removal and programmable read only memory cell as claimed in claim 11, wherein this floating region and this controlled area are arranged in the high voltage device district of this substrate.
20. the method for programming of a depletion type single level polysilicon electric removal and programmable read only memory cell, this method comprises:
Depletion type single level polysilicon electric removal and programmable read only memory cell is provided, wherein this depletion type single level polysilicon electric removal and programmable read only memory cell is positioned in the substrate, this substrate comprises floating region and controlled area, and this depletion type single level polysilicon electric removal and programmable read only memory cell also comprises:
Floating grid is positioned in this substrate of this floating region and this controlled area;
Source/drain regions is arranged in this substrate of these floating grid both sides of this floating region, and wherein this floating grid and this source/drain regions are formed a depletion type memory cell;
The control deep-well region is arranged in this controlled area, and wherein this floating grid covers partly and should control deep-well region;
Heavily doped region is arranged in this substrate of this floating grid one side of this control deep-well region of this controlled area; And
Carry out Fu Le-Nuo Dehan and wear this depletion type single level polysilicon electric removal and programmable read only memory cell of mode sequencing then.
21. the method for programming of depletion type single level polysilicon electric removal and programmable read only memory cell as claimed in claim 20, wherein this Fu Le-Nuo Dehan wear then this depletion type single level polysilicon electric removal and programmable read only memory cell of mode sequencing can be by applying voltage on this substrate in this floating region and this heavily doped region, and this control deep-well region and this source/drain regions ground connection are reached.
22. the method for programming of depletion type single level polysilicon electric removal and programmable read only memory cell as claimed in claim 21, wherein this voltage is 10～20 volts.
23. the method for programming of depletion type single level polysilicon electric removal and programmable read only memory cell as claimed in claim 20, wherein this floating region and this controlled area are in the high voltage device district in this substrate.
24. the erasing method of a depletion type single level polysilicon electric removal and programmable read only memory cell, this method comprises:
Depletion type single level polysilicon electric removal and programmable read only memory cell is provided, wherein this depletion type single level polysilicon electric removal and programmable read only memory cell is positioned in the substrate, this substrate comprises floating region and controlled area, and this depletion type single level polysilicon electric removal and programmable read only memory cell also comprises:
Floating grid is positioned in this substrate of this floating region and this controlled area;
Source/drain regions is arranged in this substrate of these floating grid both sides of this floating region, and wherein this floating grid and this source/drain regions are formed the depletion type memory cell;
The control deep-well region is arranged in this controlled area, and wherein this floating grid covers partly and should control deep-well region;
Heavily doped region is arranged in this substrate of this floating grid one side of this control deep-well region of this controlled area; And
Carry out Fu Le-Nuo Dehan and wear this depletion type single level polysilicon electric removal and programmable read only memory cell of erasing of mode then.
25. the erasing method of depletion type single level polysilicon electric removal and programmable read only memory cell as claimed in claim 24, wherein this Fu Le-Nuo Dehan wear then this depletion type single level polysilicon electric removal and programmable read only memory cell of erasing of mode can be by on this source/drain regions, applying voltage, and this substrate and this heavily doped region ground connection in this floating region are reached.
26. the erasing method of depletion type single level polysilicon electric removal and programmable read only memory cell as claimed in claim 25, wherein this voltage is 9～12 volts.
27. the erasing method of depletion type single level polysilicon electric removal and programmable read only memory cell as claimed in claim 25 is wherein carried out this Fu Le-Nuo Dehan and is worn then the step of this depletion type single level polysilicon electric removal and programmable read only memory cell of erasing of mode and also be included on this control deep-well region and apply this voltage.
28. the erasing method of depletion type single level polysilicon electric removal and programmable read only memory cell as claimed in claim 27, wherein this voltage is 9～20 volts.
29. the erasing method of depletion type single level polysilicon electric removal and programmable read only memory cell as claimed in claim 24, wherein this floating region and this controlled area are in the high voltage device district in this substrate.
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| US9847133B2 (en) * | 2016-01-19 | 2017-12-19 | Ememory Technology Inc. | Memory array capable of performing byte erase operation |
| CN110838513B (en) * | 2018-08-17 | 2023-03-24 | 立锜科技股份有限公司 | High voltage device and method for manufacturing the same |
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