CN100504710C

CN100504710C - Band-gap reference source with high power supply restraint

Info

Publication number: CN100504710C
Application number: CNB2007100532944A
Authority: CN
Inventors: 邹雪城; 陈晓飞; 刘占领; 雷鑑铭; 刘政林; 郑朝霞
Original assignee: Huazhong University of Science and Technology
Current assignee: Huazhong University of Science and Technology
Priority date: 2007-09-20
Filing date: 2007-09-20
Publication date: 2009-06-24
Anticipated expiration: 2027-09-20
Also published as: CN101131592A

Abstract

There is a sort of reference source which has the crack by checking the high electrical source, and it consists of the self-polarization circuit, the regulating circuit, the kernel circuit which has the crack, and the startup circuit. The IPTAT generating circuit of the kernel circuit which has the crack makes the collector current of the Q1 and Q2 of the NPN pipe to equal by that the degenerative feedback which is magnified adjusts its quiescent point, the IPTAT current and the VBE of the Q8 of the NPN transistor which has the negative temperature coefficient in the constant-current circuit are progressed the first compensation of the temperature, at the same time they debase the temperature coefficient. The constant-current circuit produces the polarization by itself, and provides the polarization current to the IPTAT generating current. The operational amplifier circuit advances the plus for the two-stage operational amplifier, the compensation current progresses the frequency compensation for the two-stage operational amplifier. The generating circuit removes the dependency of the reference export VREF to supply voltage by negative feedback effect in order advance the PSRR. The startup circuit removes the degeneration polarization point and it drives the self-polarization circuit to work. The self-polarization circuit provides the polarization voltage for the regulating circuit. The circuit configuration of this invention is simple and new, it does not need the external polarization, the area of this circuit is small, and it has the good temperature coefficient.

Description

Band-gap reference source with high power supply rejection

Technical Field

The invention belongs to the field of digital-analog hybrid integrated circuits, in particular to a Bi-CMOS band-gap reference source with low power consumption and high power supply rejection ratio, which is a band-gap reference voltage source with simple structure, low power consumption and high power supply rejection ratio, and is particularly suitable for being applied to analog-to-digital converters (ADC) and digital-to-analog converters (DAC) of hybrid integrated circuits.

Background

In the design of ADC and DAC mixed integrated circuits, a high-performance Reference source (Reference) integrated on a chip is indispensable. With the complexity of circuit systems and the refinement of digital-analog mixed signals, the requirements for hybrid integrated circuits such as ADCs and DACs have been increasing, and the requirements for reference sources, particularly the power supply rejection thereof, have been increasing.

The reference voltage source is manufactured by utilizing the reverse breakdown characteristic of the diode conventionally. The diode is matched with the current-limiting resistor, and the current flowing through the diode is adjusted to counteract the influence of the change of the power supply voltage on the diode. However, this requires a high supply voltage to cause the diode to breakdown in the reverse direction, and more importantly, it has a large dependence on the supply voltage, and the supply rejection ratio (PSRR) is not ideal. Also using positive V_BETo generate the reference voltage, but this would make the temperature coefficient large. The bandgap reference source is favored because of its advantages such as low temperature coefficient, high power supply rejection ratio and stable output.

In order to reduce the temperature coefficient of the band gap, one generally achieves the goal by a first-order compensation of temperature. The circuit structure of the conventional bandgap reference source is shown in fig. 1, and its power supply rejection performance is not very good, the accuracy is not very high, and it is very sensitive to the offset of the operational amplifier.

Disclosure of Invention

The invention aims to provide a bandgap reference source with high power supply rejection, which has the advantages of low power consumption and high power supply rejection.

The band-gap reference source with high power supply rejection provided by the invention comprises a self-biasing circuit, an adjusting circuit, a band-gap core circuit and a starting circuit; the band gap core circuit comprises NPN transistors Q1, Q2, Q6, Q7, Q8, PNP transistors Q3, Q4, Q5, resistors R1, R2, R3, R4 and a capacitor C1; NPN transistors Q1 andthe base electrodes of the Q2 are respectively connected with two ends of the resistor R3, the emitter electrodes are connected together and are connected with the resistor R4 together, and the other end of the resistor R4 is grounded; the collectors of the NPN transistor Q1 and the PNP transistor Q3 are connected together, and the collectors of the NPN transistor Q2 and the PNP transistor Q4 are connected together; the base potentials of the PNP transistor Q3 and the PNP transistor Q4 are the same, and the emitter potentials are connected with the reference output voltage V_REFThe above step (1); the emitter of the PNP transistor Q5 is connected to the reference output voltage V_REFThe upper and base electrodes are connected with the collectors of the NPN transistor Q2 and the PNP transistor Q4, the emitter electrode of the NPN transistor Q6 is grounded, the base electrode is connected with the base electrode of the NPN transistor Q8, the collectors of the PNP transistor Q5 and the NPN transistor Q6 are connected together and are commonly connected with the base electrode of the NPN transistor Q7; the emitter and collector of NPN transistor Q7 are grounded and reference output voltage V, respectively_REF(ii) a The collector and the base of the NPN transistor Q8 are connected together and connected to the resistor R3; one end of the resistor R2 is connected to the resistor R3, and the other end is connected to the reference output voltage V_REFThe above step (1); one end of the resistor R1 is connected with the base of the NPN transistor Q7, and the other end is connected with the capacitor C1; the other end of the capacitor C1 is connected with the base of the PNP transistor Q5; reference output voltage V_REFThe output end is connected with a peripheral circuit;

starting circuit at supply voltage V_INWhen the power is on, the power works, current is generated and is transmitted to the self-bias circuit to drive the self-bias circuit to be conducted; the self-bias circuit starts to be conducted after receiving the current provided by the starting circuit, and generates a voltage V corresponding to the power supply voltage through the self-bias action_INIrrelevant bias voltage is transmitted to the adjusting circuit, and the starting circuit is closed at the same time; after receiving the bias voltage output by the self-bias circuit, the adjusting circuit generates constant current through self adjustment and outputs the constant current to the band gap core circuit; the band-gap core circuit generates a band-gap reference voltage V through the operation of the band-gap core circuit after receiving the constant current provided by the adjusting circuit_REFAnd takes it as the output of the whole band-gap reference source.

Compared with the prior art, the core circuit of the band-gap reference source has extremely large Power Supply Rejection Ratio (PSRR) through the core circuitLocal supply V in the regulation circuit and core circuit outside the circuit_REFTo be realized. In addition, the core circuit in the invention has simple structure, consumes very small current under the same input voltage, and belongs to a low-power-consumption band-gap reference source. Under the Bi-CMOS process, the circuit structure of the traditional band-gap reference source has larger temperature coefficient through first-order compensation of temperature, and in the circuit structure of the band-gap reference source, a novel I is utilized_PTATThe circuit generates a structure, so that the temperature coefficient is greatly reduced. In addition, the invention adds a self-bias circuit, an adjusting circuit and a starting circuit, wherein the accurate duplication of the current of two branches in the self-bias circuit ensures the independence of the power supply voltage, thereby allowing the large-amplitude change of the input voltage; the adjusting circuit is biased by a self-biasing circuit and provides an external power supply for the band-gap core circuit, so that the band-gap core circuit is less influenced by an input voltage (power supply voltage). In order to avoid the existence of a degenerated point in the self-bias circuit, the starting circuit is introduced, and the starting circuit is closed after the self-bias circuit is started, so that the normal operation of the circuit is ensured, and the power consumption of the circuit is greatly reduced.

Exemplary bandgap structure in fig. 1, PSRR is reduced due to mismatch of operational amplifier, and accuracy is reduced due to limited gain. In the band gap structure diagram 3 of the invention, the gain is improved through two stages of operational amplifiers, thereby improving the precision; the offset of the operational amplifier can be reduced by using single-ended input; the frequency compensation of the compensation circuit 8 is used to improve the phase margin of the operational amplifier itself, thereby ensuring its stability. The specific analysis is as follows: the PNP transistor Q5 and the NPN transistor Q6 form a first-stage amplifier, namely a common emitter amplifier, wherein the PNP transistor Q5 is of a PNP type because the PNP type is used for biasing the potential of a Y point so as to ensure V_X＝V_Y. The NPN transistor Q6 is an active load of the PNP transistor Q5, which utilizes the characteristic of high dynamic impedance of the active load to improve the gain, and in addition, the static power consumption of the active load is also small. The NPN transistor Q7 is a common emitter amplifier, and the cascade connection of the two common emitter amplifiers greatly improves the gain and the precision. A great role of operational amplifierThat is, its deep negative feedback makes the output independent of the input, the feedback polarity of the operational amplifier is briefly explained here: when there is an instantaneous positive signal at point Y, the first stage operational amplifier and the second stage operational amplifier are both common emitters, so that after passing through the two stages of operational amplifiers, the signal is still positive, the positive signal is applied to the resistor R3, and the base voltage of the NPN transistor Q1 is changed into delta V_BEThe base voltage of the NPN transistor Q2 changes to Δ V_BE+ΔIR₃Therefore, the change of the base of the NPN transistor Q2 has far greater influence on the Y point than the change of the base of the NPN transistor Q1; moreover, the base and the point Y of the NPN transistor Q1 are the same-direction ends, and the base and the point Y of the NPN transistor Q2 are the reverse ends, so the negative feedback coefficient of the circuit is far larger than the positive feedback coefficient, and deep negative feedback is formed. That is, when there is a slight difference between the collector currents of the NPN transistors Q1 and Q2, the bases of the NPN transistors Q1 and Q2 are both sensed, and then they adjust their respective quiescent operating points by the action of this deep negative feedback to reduce the difference between the collector currents, thereby ensuring that the collector currents are exactly equal, which is also very advantageous for lowering the temperature coefficient.

In a word, the circuit structure of the reference source is simple and novel, the self bias is used for providing power supply without external bias, the occupied area of the circuit is small, and the circuit has a good temperature coefficient.

Drawings

FIG. 1 is a core circuit schematic of a typical bandgap reference source;

FIG. 2 is a schematic block diagram of a bandgap reference source of the present invention;

FIG. 3 is a schematic diagram of the core circuit of the bandgap reference source of the present invention;

FIG. 4 is a circuit diagram corresponding to one embodiment of FIG. 2;

FIG. 5 shows the PSRR simulation results of the present invention;

FIG. 6 shows the simulation result of the variation of output with input voltage (voltage regulation rate) in the circuit of the present invention.

Detailed Description

The invention is a band-gap reference source with starting circuit and self-bias circuit, which has the advantages of high power supply rejection (PSRR), large input range, small voltage regulation rate, small current consumption under the same power supply voltage, etc. As shown in fig. 2, the bandgap reference source includes a bandgap core circuit 3 for generating a reference, and a self-bias circuit 1 for providing an external power supply to the bandgap core circuit 3, an adjusting circuit 2, and a start-up circuit 4. When the power supply voltage V_INWhen the power is on, the starting circuit 4 works to drive the self-bias circuit 1 to be conducted; the self-bias circuit 1 is turned on to turn off the starting circuit 4 and provide the relative power voltage V for the adjusting circuit 2 through self bias_INAn unrelated bias voltage; the adjusting circuit 2 provides an external power supply irrelevant to the power supply voltage for the band gap core circuit 3; the band gap core circuit 3 outputs a reference voltage V_REFAnd use of V_REFAs its own "local supply" to make it compatible with the supply voltage V_INIs irrelevant.

As shown in fig. 3, the bandgap core circuit 3 includes NPN transistors Q1, Q2, Q6, Q7, and Q8, and PNP transistors Q3, Q4, and Q5, and further includes resistors R1, R2, R3, R4, and a capacitor C1. The bases of NPN transistors Q1 and Q2 are connected to both ends of resistor R3, respectively, and their emitters are connected together and commonly connected to resistor R4, and the other end of resistor R4 is grounded. The collectors of NPN transistor Q1 and PNP transistor Q3 are tied together, and the collectors of NPN transistor Q2 and PNP transistor Q4 are tied together. The base potentials of the PNP transistor Q3 and the PNP transistor Q4 are the same, and the emitter potentials are connected to V_REFThe above. The emitter of the PNP transistor Q5 is connected with V_REFThe upper and base electrodes are connected with the collectors of the NPN transistor Q2 and the PNP transistor Q4, the emitter electrode of the NPN transistor Q6 is grounded, the base electrode is connected with the base electrode of the NPN transistor Q8, and the collectors of the PNP transistor Q5 and the NPN transistor Q6 are connected together and commonly connected with the base electrode of the NPN transistor Q7.The emitter and base of NPN transistor Q7 are connected to ground and V respectively_REFThe above. The collector and base of NPN transistor Q8 are connected together and to resistor R3. One end of the resistor R2 is connected to the resistor R3, and the other end is connected to V_REFThe above. V_REFAs output terminal connected to peripheral circuit.

NPN transistors Q1, Q2 and resistor R3 form I_PTATA generation circuit 6 for generating I_PTATCurrent then V of negative temperature coefficient with NPN transistor Q8_BECompensation is performed to reduce the temperature coefficient. The PNP transistors Q3, Q4 ensure that the currents flowing through the two circuits are exactly equal by current mirroring. The NPN transistors Q8, Q1 and the resistor R4 constitute a constant current source circuit 7, form a micro current source, and supply bias currents to the PNP transistors Q3, Q4. The PNP transistor Q5, the NPN transistor Q6, and the NPN transistor Q7 form an operational amplifier circuit 5, which constitutes a two-stage operational amplifier, wherein the PNP transistor Q5 and the NPN transistor Q6 are the first stage, and the NPN transistor Q7 is the second stage. The resistor R1 and the capacitor C1 form a compensation circuit 8, and frequency compensation is carried out on the two-stage operational amplifier to ensure stability of the two-stage operational amplifier. The whole circuit of fig. 3 is composed of a "local supply" V_REFThe power is supplied, and the core band gap circuit and the power supply voltage V are ensured_INIs not relevant.

The specific operation principle of the bandgap core circuit 3 is as follows. In FIG. 3, a positive temperature coefficient I is generated_PTATThe current circuit is realized by NPN transistors Q1, Q2, and R3, specifically:

let I_S，Q1＝NI_S.Q2Then, I_PTAT＝ΔV_BE/R₃＝V_TlnN/R₃The current is positive temperature coefficient and passes through the negative temperature coefficient V of the NPN transistor Q8_BEThe first order compensation is performed with:

<math> <mrow> <mfrac> <mrow> <mo>&PartialD;</mo> <msub> <mi>V</mi> <mi>REF</mi> </msub> </mrow> <mrow> <mo>&PartialD;</mo> <mi>T</mi> </mrow> </mfrac> <mo>=</mo> <mfrac> <mrow> <mo>&PartialD;</mo> <msub> <mi>V</mi> <mrow> <mi>BE</mi> <mo>,</mo> <mi>Q</mi> <mn>8</mn> </mrow> </msub> </mrow> <mrow> <mo>&PartialD;</mo> <mi>T</mi> </mrow> </mfrac> <mo>+</mo> <mfrac> <msub> <mi>R</mi> <mn>2</mn> </msub> <msub> <mi>R</mi> <mn>3</mn> </msub> </mfrac> <mi>ln</mi> <mi>N</mi> <mfrac> <mrow> <mo>&PartialD;</mo> <msub> <mi>V</mi> <mi>T</mi> </msub> </mrow> <mrow> <mo>&PartialD;</mo> <mi>T</mi> </mrow> </mfrac> </mrow></math>

at room temperature (T300K),

while

The zero temperature coefficient at this temperature can be theoretically achieved by adjusting the ratio of R2 to R3. In practice, it is difficult to achieve very low temperature coefficients, and in the present invention, H-spice simulations under a 0.6 μm Bi-CMOS process library have shown that temperature coefficients in the range of-20 to-125 deg.C reach below 40 ppm/deg.C, which is a very low value in Bi-CMOS processes. In a typical bandgap structure such as that shown in fig. 1, the temperature coefficient can only be theoretically small by ensuring that the collector currents of NPN transistors Q1 and Q2 are equal, but the collector currents of the NPN transistors Q1 and Q2 are difficult to match perfectly due to the fact that the input impedance of the operational amplifier is not infinite, and the like, so the temperature coefficient is not ideal. However, in the structure of the present invention, it can be well ensured that the collector currents of both NPN transistors Q1, Q2 are exactly equal. First, from a large signal perspective, V_X＝V_REF-V_BE，Q3And V is_Y＝V_REF-V_BE，Q5This ensures V_X＝V_YThereby ensuring that the collector currents flowing through the NPN transistors Q1 and Q2 are exactly equal; secondly, from the viewpoint of small signals, when collector currents of the NPN transistors Q1 and Q2 slightly change, the static operating points of the NPN transistors Q1 and Q2 are adjusted by a deep negative feedback effect of the two-stage operational amplifier, so that the collector currents of the NPN transistors Q1 and Q2 are ensured to be accurately equal.

In addition, bias currents I of NPN transistors Q1, Q2, and PNP transistors Q3 and Q4₀The constant current source circuit 7 is used for providing the following specific implementation: in the constant current source circuit 7, from V_BE，Q8＝V_BE，Q1+I₀R₄And

V_{BE} = V_{T} \ln (\frac{I_{C}}{I_{S}})

obtaining:

I_{0} = \frac{V_{T} \ln M}{R_{4}},

where M is the ratio of the emitter areas of NPN transistors Q1 and Q8. The bias is provided in such a way, so that the advantage of no need of external separate bias is achieved, the performance is stable, and the layout area is saved.

The following examples are given by way of illustration only and are not intended to limit the invention in any way.

As shown in fig. 4, the self-bias circuit 1 includes resistors R5, R6, R7, and R8, NPN transistors Q9 and Q10, and PMOS transistors M1 and M2. One end of the resistor R5 is connected with the input end, and the other end is connected with the source electrode of the PMOS tube M1; one end of the resistor R6 is connected with the input end, and the other end is connected with the source electrode of the PMOS tube M2; resistor R8 has one end connected to the emitter of NPN transistor Q10 and the other end connected to ground. The grid potentials of the PMOS tubes M1 and M2 are the same, and the PMOS tubes M1 and M2 are connected to the drain electrode of the PMOS tube M2; the drain of the PMOS transistor M1 is connected to the resistor R7. The base and collector of the NPN transistor Q9 are connected together and commonly connected to the base of the NPN transistor Q10 and the other end of the resistor R7, and the emitter of the NPN transistor Q9 is grounded. The collector of the NPN transistor Q10 is connected to the drain of the PMOS transistor M2, and the emitter is connected to the resistor R8.

The configuration of the bandgap core circuit 3 is the same as that shown in fig. 3.

The regulator circuit 2 is composed of a PMOS transistor M3. The source electrode of the PMOS transistor M3 is connected with power voltage, the grid electrode is connected with the grid electrode of the PMOS transistor M2 in the self-bias circuit 1, and the drain electrode is connected with the emitter electrode of the PNP transistor Q3 in the band gap core circuit 3.

The starting circuit 4 comprises resistors R9 and R10, and further comprises NMOS tubes M4 and M5. One end of the resistor R9 is connected with the power supply voltage V_INThe other end is connected with the drain electrode of the NMOS tube M4; one end of the resistor R10 is connected to the drain of the NMOS transistor M4, and the other end is connected to the gate of the NMOS transistor M5. The grid electrode of the NMOS tube M4 is connected with the drain electrode of the PMOS tube M1 in the self-bias circuit 1, and the source electrode is grounded; the drain of the NMOS transistor M5 is connected to the collector of the NPN transistor Q10 in the self-bias circuit 1, and the source is grounded.

The magnitude of the current flowing through the PMOS transistor M2 in the self-bias circuit 1 is determined by a micro-current source composed of NPN transistors Q9, Q10 and a resistor R8, specifically:

I_PTAT＝ΔV_BE/R₈＝V_TlnN/R₈

this current is biased by self-bias circuit 1 and thus is coupled to supply voltage V_INIs irrelevant. The resistors R5 and R6 form source followers of the PMOS tubes M1 and M2, and independence of the self-bias circuit and power supply voltage is further guaranteed. However, a very important problem in a bias circuit 1 that is independent of the power supply is the existence of a "degenerate" bias point. For example, in the embodiment of fig. 4, if all transistors are delivering zero current when the power supply is powered up, they can be kept off indefinitely because the self-biasing circuit 1 allows zero current to be delivered from both sides. Based on the above, the circuit of the present invention therefore introduces a start-up circuit 4 to account for the presence of a "degenerate" bias point. The introduction of the starting circuit 4, which is expected in the circuit of the present invention, tends to increase the power consumption, so that the power consumption can be reduced by the resistor R7. The principle is as follows: when the start-up circuit starts operating, since the current flowing through the resistor R7 in the self-bias circuit 1 is zero, the voltage V of the start-up circuit is zero_BEWill be added to the NPN transistor Q9 to turn on the NPN transistor Q9, and after the NPN transistor Q9 is turned on, a current independent of the power will be generated in the self-bias circuit 1, and then a voltage drop will be generated in the resistor R7, so that the potential at the point P is greater than V_BEAnd thus the start-up circuit is turned off, which greatly reduces power consumption, and in addition, the bandgap core circuit 3, due to its simple structure, causes the current consumed by the circuit to be small at the same input voltage, thereby also reducing power consumption.

The current generated in the self-bias circuit 1 is almost independent of the supply voltage, which results in a large input range of the input voltage. When the current flows through the PMOS transistor M2, the gate voltage of the PMOS transistor M2 is determined according to the saturation leakage current equation of the PMOS transistor M2, and the gate voltage is the bias voltage of the PMOS transistor M3 in the regulator circuit 3. The PMOS transistor M3 can also be called a voltage regulator transistor because when the supply voltage V is applied_INWhen it becomes larger, due to I_PTATThe current is basically unchanged, so that the gate voltage of the PMOS transistor M2 correspondingly becomes larger according to the saturation current equation, that is, the gate potential of the PMOS transistor M3 increases with the increase of the source potential, while the voltage between the gate and the source of the PMOS transistor M3 does not change much, so that the current flowing through the PMOS transistor M3 also changes little and becomes slightly smaller, and thus the output of the bandgap becomes slightly smaller, about- Δ V due to the slight decrease of the leakage current of the PMOS transistor M3_REF. When Vin is increased, the bandgap output voltage is also slightly increased to about + Δ V_REFAnd + Δ V_REF≈-ΔV_REF. It can be seen that the adjusting circuit 2 is actually a negative feedback circuit of the bandgap core circuit 3 to ensure the bandgap output voltage V in the bandgap core circuit 3_REFIndependent of the supply voltage, thereby also improving the power supply rejection ratio of the overall circuit.

In addition, the circuit structure of the invention introduces the idea of local power supply to further improve the power supply rejection ratio. That is, in the band gap core circuit 3, if we can introduce an ANDSupply voltage V_INThe PSRR of the bandgap core circuit 3 is increased by the power supply with small correlation. In fact, the circuit arrangement of the present invention makes use of the idea that the "local supply" referred to above is the bandgap output V_REF. By regulation of the PMOS transistor M3 in the regulating circuit 2, V_REFAnd V_INThe dependence of (c) has decreased much, and in the bandgap core circuit 3, all devices are powered by the "local supply" V_REFThe PSRR is also greatly improved because of the direct power supply. The H-spice simulation result under the Bi-CMOS process library based on 0.6 mu m is shown in figure 5. As can be seen from fig. 5, the power supply rejection ratio PSRR of the bandgap output is very high under the three models TT, SS and FF.

The circuit of the invention has small voltage regulation rate of band gap output under the condition of direct current. The specific analysis is as follows: when the input voltage has a large fluctuation, V is adjusted by the action of a PMOS tube M3 in the adjusting circuit 2_REFThe amplitude of variation is small, and V_REFAnd further influenced by the deep negative feedback of the operational amplifier in the band-gap core circuit 3, resulting in V_REFSubstantially independent of input voltage V_INThe effect of the change. The above analysis was well verified by performing an H-spice simulation on a Bi-CMOS process of 0.6 μm (simulation results are shown in FIG. 5).

Claims

1. A high power supply rejection bandgap reference source, characterized by: the band-gap power supply comprises a self-biasing circuit (1), an adjusting circuit (2), a band-gap core circuit (3) and a starting circuit (4); wherein,

the band gap core circuit (3) comprises NPN transistors Q1, Q2, Q6, Q7 and Q8, PNP transistors Q3, Q4 and Q5, resistors R1, R2, R3, R4 and a capacitor C1; bases of NPN transistors Q1 and Q2 are respectively connected with two ends of a resistor R3, emitters are connected together and are commonly connected with the resistor R4, and the other end of the resistor R4 is grounded; the collectors of the NPN transistor Q1 and the PNP transistor Q3 are connected together, and the NPN crystalThe collectors of the transistor Q2 and the PNP transistor Q4 are connected together; the base potentials of the PNP transistor Q3 and the PNP transistor Q4 are the same, and the emitter potentials are connected with the reference output voltage V_REFThe above step (1); the emitter of the PNP transistor Q5 is connected to the reference output voltage V_REFThe upper and base electrodes are connected with the collectors of the NPN transistor Q2 and the PNP transistor Q4, the emitter electrode of the NPN transistor Q6 is grounded, the base electrode is connected with the base electrode of the NPN transistor Q8, the collectors of the PNP transistor Q5 and the NPN transistor Q6 are connected together and are commonly connected with the base electrode of the NPN transistor Q7; the emitter and collector of NPN transistor Q7 are grounded and reference output voltage V, respectively_REF(ii) a The collector and the base of the NPN transistor Q8 are connected together and connected to the resistor R3; one end of the resistor R2 is connected to the resistor R3, and the other end is connected to the reference output voltage V_REFThe above step (1); one end of the resistor R1 is connected with the base of the NPN transistor Q7, and the other end is connected with the capacitor C1; the other end of the capacitor C1 is connected with the base of the PNP transistor Q5; reference output voltage V_REFThe output end is connected with a peripheral circuit;

the starting circuit (4) is operated at a supply voltage V_INWhen the power is on, the power works, current is generated and is transmitted to the self-bias circuit (1) to drive the self-bias circuit (1) to be conducted; the self-bias circuit (1) starts to be conducted after receiving the current provided by the starting circuit (4), and generates a power supply voltage V through the self-bias action_INAn unrelated bias voltage is transmitted to the adjusting circuit (2), and the starting circuit (4) is closed; after receiving the bias voltage output by the self-bias circuit (1), the adjusting circuit (2) generates constant current through self adjusting action and outputs the constant current to the band gap core circuit (3); the band-gap core circuit (3) generates a band-gap reference voltage V through the operation of the band-gap core circuit after receiving the constant current provided by the adjusting circuit (2)_REFAnd takes it as the output of the whole band-gap reference source.

2. The bandgap reference source as recited in claim 1, wherein: the self-bias circuit (1) comprises resistors R5, R6, R7 and R8, NPN transistors Q9 and Q10, and PMOS transistors M1 and M2; one end of the resistors R5 and R6 is connected with the power supply voltage V_INThe other end of the resistor R5 is connected with the source of the PMOS tube M1The other end of the resistor R6 is connected with the source electrode of the PMOS tube M2; one end of the resistor R8 is connected with the emitter of the NPN transistor Q10, and the other end is grounded; the gates of the PMOS tubes M1 and M2 are connected with the drain of the PMOS tube M2, and the drain of the PMOS tube M1 is connected with the resistor R7; the base and the collector of the NPN transistor Q9 are connected together and commonly connected with the base of the NPN transistor Q10 and the other end of the resistor R7, and the emitter of the NPN transistor Q9 is grounded; the collector of the NPN transistor Q10 is connected to the drain of the PMOS transistor M2, and the emitter is connected to the resistor R8.

3. The bandgap reference source as claimed in claim 1 or 2, wherein: the regulating circuit (2) is composed of a PMOS tube M3, and the source electrode of the PMOS tube M3 is connected with the power supply voltage V_INThe grid is connected with the grid of a PMOS transistor M2 in the self-bias circuit (1), and the drain is connected with the emitter of a PNP transistor Q3 in the band gap core circuit (3).

4. The bandgap reference source as recited in claim 3, wherein: the starting circuit (4) comprises resistors R9 and R10, and NMOS tubes M4 and M5; one end of the resistor R9 is connected with the power supply voltage VIN, and the other end is connected with the drain electrode of the NMOS tube M4; one end of the resistor R10 is connected with the drain electrode of the NMOS tube M4, and the other end is connected with the grid electrode of the NMOS tube M5; the grid electrode of the NMOS tube M4 is connected with the drain electrode of the PMOS tube M1, and the source electrode is grounded; the drain of the NMOS transistor M5 is connected to the collector of the NPN transistor Q10, and the source is grounded.