CN100504710C - Bandgap Reference Source with High Power Supply Rejection - Google Patents

Abstract

There is a sort of reference source which has the crack by checking the high electrical source, and it consists of the self-polarization circuit, the regulating circuit, the kernel circuit which has the crack, and the startup circuit. The IPTAT generating circuit of the kernel circuit which has the crack makes the collector current of the Q1 and Q2 of the NPN pipe to equal by that the degenerative feedback which is magnified adjusts its quiescent point, the IPTAT current and the VBE of the Q8 of the NPN transistor which has the negative temperature coefficient in the constant-current circuit are progressed the first compensation of the temperature, at the same time they debase the temperature coefficient. The constant-current circuit produces the polarization by itself, and provides the polarization current to the IPTAT generating current. The operational amplifier circuit advances the plus for the two-stage operational amplifier, the compensation current progresses the frequency compensation for the two-stage operational amplifier. The generating circuit removes the dependency of the reference export VREF to supply voltage by negative feedback effect in order advance the PSRR. The startup circuit removes the degeneration polarization point and it drives the self-polarization circuit to work. The self-polarization circuit provides the polarization voltage for the regulating circuit. The circuit configuration of this invention is simple and new, it does not need the external polarization, the area of this circuit is small, and it has the good temperature coefficient.

Description

Bandgap Reference Source with High Power Supply Rejection

technical field

The invention belongs to the field of digital-analog hybrid integrated circuits, specifically a Bi-CMOS bandgap reference source with low power consumption and high power supply rejection, and is a bandgap reference voltage source with simple structure, low power consumption and high power supply rejection ratio, and is especially suitable for application In the analog/digital converter (ADC) and digital/analog converter (DAC) of hybrid integrated circuits.

Background technique

In the design of ADC and DAC hybrid integrated circuits, the high-performance reference source (Reference) integrated on-chip is indispensable. With the complexity of the circuit system and the refinement of the digital-analog mixed signal, the requirements for hybrid integrated circuits such as ADC and DAC are getting higher and higher, so the requirements for the reference source, especially its power supply suppression, are also getting higher and higher. .

To make a reference voltage source, the traditional method is to use the reverse breakdown characteristics of the diode. It uses a diode to cooperate with a current-limiting resistor, and adjusts the current flowing through itself to offset the influence of the change of the power supply voltage on it. However, this requires a very high power supply voltage to cause the diode to reverse breakdown, and more importantly, it has a large correlation with the power supply voltage, and the power supply rejection ratio (PSRR) is not ideal. Some also use the positive V _BE to generate the reference voltage, but this will make the temperature coefficient very large. The bandgap reference source is favored because of its low temperature coefficient, high power supply rejection ratio and stable output.

In order to reduce the temperature coefficient of the bandgap, people generally achieve the goal through the method of temperature first-order compensation. The circuit structure of the traditional bandgap reference source is shown in Figure (1). Its power supply rejection performance is not very good, the accuracy is not very high, and it is also very sensitive to the offset of the operational amplifier.

Contents of the invention

The object of the present invention is to provide a bandgap reference source with high power supply rejection, which has the advantages of low power consumption and high power supply rejection.

The bandgap reference source with high power supply suppression provided by the present invention includes a self-bias circuit, an adjustment circuit, a bandgap core circuit and a start-up circuit; wherein, the bandgap core circuit includes NPN transistors Q1, Q2, Q6, Q7 and Q8, PNP Transistors Q3, Q4, and Q5 also include resistors R1, R2, R3, R4, and capacitor C1; the bases of NPN transistors Q1 and Q2 are respectively connected to both ends of resistor R3, and the emitters are connected together to connect to resistor R4 , the other end of resistor R4 is grounded; the collectors of NPN transistor Q1 and PNP transistor Q3 are connected together, and the collectors of NPN transistor Q2 and PNP transistor Q4 are connected together; the base potentials of PNP transistor Q3 and PNP transistor Q4 are the same, and the emitter The electrode potentials are all connected to the reference output voltage V _REF ; the emitter of the PNP transistor Q5 is connected to the reference output voltage V _REF , the base is connected to the collectors of the NPN transistor Q2 and the PNP transistor Q4, and the emitter of the NPN transistor Q6 is grounded , the base and the base of the NPN transistor Q8 are connected together, and the collectors of the PNP transistor Q5 and the NPN transistor Q6 are connected together, and are commonly connected to the base of the NPN transistor Q7; the emitter and the collector of the NPN transistor Q7 are respectively grounded and the reference output voltage V _REF ; the collector and base of the NPN transistor Q8 are connected together and connected to the resistor R3; one end of the resistor R2 is connected to the resistor R3, and the other end is connected to the reference output voltage V _REF ; one end of the resistor R1 Connected to the base of the NPN transistor Q7, the other end is connected to the capacitor C1; and the other end of the capacitor C1 is connected to the base of the PNP transistor Q5; the reference output voltage V _REF is connected to the peripheral circuit as the output terminal;

The start-up circuit works when the power supply voltage V _IN is powered on, generates current and sends it to the self-bias circuit to drive the self-bias circuit to conduct; the self-bias circuit starts to conduct after receiving the current provided by the start-up circuit, and through its own The bias function to generate a bias voltage that has nothing to do with the power supply voltage V _IN , and send it to the adjustment circuit, and at the same time turn off the startup circuit; after the adjustment circuit receives the bias voltage output from the bias circuit, through its own adjustment function To generate a constant current and output it to the bandgap core circuit; after the bandgap core circuit receives the constant current provided by the adjustment circuit, it generates the bandgap reference voltage V _REF through its own operation, and uses it as the entire bandgap reference source Output.

Compared with the prior art, the bandgap reference source core circuit of the present invention has a great power supply rejection ratio (PSRR), which is realized by the adjustment circuit outside the core circuit and "local power supply" V _REF in the core circuit of. Moreover, the core circuit in the present invention has a simple structure, consumes very little current under the same input voltage, and belongs to a bandgap reference source with low power consumption. Under the Bi-CMOS process, the circuit structure of the traditional bandgap reference source has a relatively large temperature coefficient through the first-order compensation of temperature. In the circuit structure of the bandgap reference source, a novel _IPTAT circuit is used to generate the structure, so that The temperature coefficient is greatly reduced. In addition, the present invention adds a self-bias circuit, an adjustment circuit and a start-up circuit, wherein the precise replication of the two branch currents in the self-bias circuit ensures independence from the power supply voltage, thereby allowing a large range of input voltage Change; the adjustment circuit is biased by a self-bias circuit and provides an external power supply for the bandgap core circuit, which makes the bandgap core circuit less affected by the input voltage (power supply voltage). In order to avoid the existence of "degenerate points" in the self-bias circuit, the present invention introduces a start-up circuit. When the self-bias circuit is started, the start-up circuit is closed, which not only ensures the normal operation of the circuit, but also greatly reduces the power consumption of the circuit.

Typical structure of the bandgap In Figure 1, the PSRR will be reduced due to the offset of the op amp, and the limited gain will also reduce the accuracy. And in bandgap structure Fig. 3 of the present invention, increase gain by two-stage op-amp, and then improve precision; Op-amp can reduce its offset with single-ended input; The frequency compensation of compensating circuit 8 is used for improving the phase of op-amp self margin, thereby ensuring its stability. The specific analysis is as follows: PNP transistor Q5 and NPN transistor Q6 form the first-stage amplifier—common emitter amplifier. The reason why PNP transistor Q5 uses PNP type is to bias the potential of point Y to ensure V _X =V _Y . The NPN transistor Q6 is the active load of the PNP transistor Q5, which utilizes the characteristic of high dynamic impedance of the active load to increase the gain. In addition, the static power consumption of the active load is also small. The NPN transistor Q7 is a common-emitter amplifier, and the cascading of two common-emitter amplifiers greatly improves the gain and precision. A great function of the operational amplifier is that its deep negative feedback makes the output irrelevant to the input. Here is also a brief explanation of the feedback polarity of the operational amplifier: when there is an instantaneous positive signal at point Y, due to the first and second stages The operational amplifiers are all common emitters, so after two stages of operational amplifiers, the signal is still positive, and the positive signal is added to the resistor R3, the base voltage of the NPN transistor Q1 changes to ΔV _BE , and the base voltage of the NPN transistor Q2 changes to ΔV _BE +ΔIR ₃ , therefore, the change of the base of NPN transistor Q2 has a greater influence on point Y than the change of the base of NPN transistor Q1; moreover, since the base of NPN transistor Q1 and point Y are the same terminal, NPN The base of the transistor Q2 and the Y point are opposite terminals, therefore, the negative feedback coefficient of this circuit is much larger than the positive feedback coefficient, forming deep negative feedback. That is to say, when there is a slight difference in the collector currents of NPN transistors Q1 and Q2, the bases of NPN transistors Q1 and Q2 can feel it, so they adjust their quiescent operating points through this deep negative feedback, To reduce the difference of the collector current, thus ensuring the exact equalization of the collector current, which is also very beneficial for reducing the temperature coefficient.

In a word, the circuit structure of the reference source of the present invention is simple and novel. It uses its own bias to provide power without external bias. The circuit occupies a small area and has a good temperature coefficient.

Description of drawings

Figure 1 is a schematic diagram of the core circuit of a typical bandgap reference source;

Fig. 2 is the functional block diagram of the bandgap reference source of the present invention;

Fig. 3 is the core circuit schematic diagram of the bandgap reference source of the present invention;

Fig. 4 is a circuit diagram corresponding to an embodiment of Fig. 2;

Fig. 5 is the PSRR simulation result of the present invention;

FIG. 6 is a simulation result of output varying with input voltage (voltage regulation rate) in the circuit of the present invention.

Detailed ways

The invention is a bandgap reference source with a start-up circuit and a self-bias circuit, which has the advantages of high power supply rejection (PSRR), large input range, small voltage adjustment rate, and low current consumption under the same power supply voltage. As shown in FIG. 2 , the bandgap reference source includes a bandgap core circuit 3 for generating a reference, a self-bias circuit 1 , an adjustment circuit 2 and a start-up circuit 4 for providing external power to the bandgap core circuit 3 . When the power supply voltage V _IN is powered on, the start-up circuit 4 works to drive the self-bias circuit 1 to conduct; after the self-bias circuit 1 is turned on, the start-up circuit 4 is turned off, and provides relative power for the adjustment circuit 2 through its own bias Voltage V _IN has nothing to do with the bias voltage; the adjustment circuit 2 provides an external power supply independent of the power supply voltage for the bandgap core circuit 3; the bandgap core circuit 3 outputs the reference voltage V _REF and uses V _REF as its own "local power supply" to make It is independent of the supply voltage V _IN .

As shown in FIG. 3 , the bandgap core circuit 3 includes NPN transistors Q1, Q2, Q6, Q7 and Q8, PNP transistors Q3, Q4 and Q5, resistors R1, R2, R3, R4 and capacitor C1. The bases of the NPN transistors Q1 and Q2 are respectively connected to both ends of the resistor R3, and their emitters are connected together to be connected to the resistor R4, and the other end of the resistor R4 is grounded. The collectors of the NPN transistor Q1 and the PNP transistor Q3 are connected together, and the collectors of the NPN transistor Q2 and the PNP transistor Q4 are connected together. The base potentials of the PNP transistor Q3 and the PNP transistor Q4 are the same, and the emitter potentials are also connected to _VREF . The emitter of the PNP transistor Q5 is connected to _VREF , the base is connected to the collectors of the NPN transistor Q2 and the PNP transistor Q4, the emitter of the NPN transistor Q6 is connected to the ground, and the base is connected to the base of the NPN transistor Q8. The collectors of the PNP transistor Q5 and the NPN transistor Q6 are connected together, and are commonly connected to the base of the NPN transistor Q7. The emitter and base of NPN transistor Q7 are connected to ground and V _REF respectively. The collector and base of NPN transistor Q8 are connected together and connected to resistor R3. One end of the resistor R2 is connected to the resistor R3, and the other end is connected to V _REF . V _REF is connected to the peripheral circuit as an output terminal.

NPN transistors Q1, Q2 and resistor R3 form an I _PTAT generating circuit 6 for generating I _PTAT current, and then compensate with V _BE of the negative temperature coefficient of NPN transistor Q8, so as to reduce the temperature coefficient. PNP transistors Q3 and Q4 ensure that the currents flowing through the two circuits are exactly equal through current mirroring. NPN transistors Q8, Q1 and resistor R4 form a constant current source circuit 7, forming a micro current source, and providing bias current for PNP transistors Q3, Q4. The PNP transistor Q5, NPN transistor Q6 and NPN transistor Q7 constitute an operational amplifier circuit 5, forming a two-stage operational amplifier, wherein the PNP transistor Q5 and the NPN transistor Q6 are the first stage, and the NPN transistor Q7 is the second stage. The resistor R1 and the capacitor C1 form a compensation circuit 8, which performs frequency compensation on the two-stage operational amplifier to ensure its stability. The entire circuit in Figure 3 is powered by the "local power supply" V _REF , which further ensures the independence of the core bandgap circuit from the power supply voltage V _IN .

The specific working principle of the bandgap core circuit 3 is as follows. In Figure 3, the circuit that generates the positive temperature coefficient I _PTAT current is realized by NPN transistors Q1, Q2 and R3, specifically:

${\mathrm{<span\; class="notranslate">\; I</span>}}_{\mathrm{<span\; class="notranslate">\; PTAT</span>}}{\mathrm{<span\; class="notranslate">\; <figure-callout\; id="3"\; label="R"\; filenames="C200710053294E00132.png,C200710053294E00142.png"\; state="\{\{state\}\}">R</figure-callout></span>}}_{\mathrm{<span\; class="notranslate">\; 3</span>}}<span\; class="notranslate">\; =</span>\mathrm{<span\; class="notranslate">\; \&Delta;</span>}{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; BE</span>}}<span\; class="notranslate">\; =</span>{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; BE</span>}<span\; class="notranslate">\; ,</span>\mathrm{<span\; class="notranslate">\; Q</span>}\mathrm{<span\; class="notranslate">\; 2</span>}}<span\; class="notranslate">\; -</span>{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; BE</span>}<span\; class="notranslate">\; ,</span>\mathrm{<span\; class="notranslate">\; <figure-callout\; id="1"\; label="Q"\; filenames="C200710053294E00141.png,C200710053294E00142.png"\; state="\{\{state\}\}">Q</figure-callout></span>}\mathrm{<span\; class="notranslate">\; 1</span>}}<span\; class="notranslate">\; =</span>{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; T</span>}}\mathrm{<span\; class="notranslate">\; ln</span>}<span\; class="notranslate">\; (</span>\frac{{\mathrm{<span\; class="notranslate">\; I</span>}}_{\mathrm{<span\; class="notranslate">\; C</span>}<span\; class="notranslate">\; ,</span>\mathrm{<span\; class="notranslate">\; Q</span>}\mathrm{<span\; class="notranslate">\; 2</span>}}}{{\mathrm{<span\; class="notranslate">\; I</span>}}_{\mathrm{<span\; class="notranslate">\; S</span>}<span\; class="notranslate">\; ,</span>\mathrm{<span\; class="notranslate">\; Q</span>}\mathrm{<span\; class="notranslate">\; 2</span>}}}<span\; class="notranslate">\; )</span><span\; class="notranslate">\; -</span>{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; T</span>}}\mathrm{<span\; class="notranslate">\; ln</span>}<span\; class="notranslate">\; (</span>\frac{{\mathrm{<span\; class="notranslate">\; I</span>}}_{\mathrm{<span\; class="notranslate">\; C</span>}<span\; class="notranslate">\; ,</span>\mathrm{<span\; class="notranslate">\; Q</span>}\mathrm{<span\; class="notranslate">\; 1</span>}}}{{\mathrm{<span\; class="notranslate">\; I</span>}}_{\mathrm{<span\; class="notranslate">\; S</span>}<span\; class="notranslate">\; ,</span>\mathrm{<span\; class="notranslate">\; Q</span>}\mathrm{<span\; class="notranslate">\; 1</span>}}}<span\; class="notranslate">\; )</span>$

Assuming I _{S, Q1} = NI _S.Q2 , then I _PTAT = ΔV _BE /R ₃ = V _T lnN/R ₃ , the current has a positive temperature coefficient, and the first-order compensation is performed with the V _BE of the negative temperature coefficient of the NPN transistor Q8 ,have:

$\frac{<span\; class="notranslate">\; \&PartialD;</span>{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; REF</span>}}}{<span\; class="notranslate">\; \&PartialD;</span>\mathrm{<span\; class="notranslate">\; T</span>}}<span\; class="notranslate">\; =</span>\frac{<span\; class="notranslate">\; \&PartialD;</span>{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; BE</span>}<span\; class="notranslate">\; ,</span>\mathrm{<span\; class="notranslate">\; <figure-callout\; id="8"\; label="Q"\; filenames="C200710053294E00141.png,C200710053294E00152.png"\; state="\{\{state\}\}">Q</figure-callout></span>}\mathrm{<span\; class="notranslate">\; 8</span>}}}{<span\; class="notranslate">\; \&PartialD;</span>\mathrm{<span\; class="notranslate">\; T</span>}}<span\; class="notranslate">\; +</span>\frac{{\mathrm{<span\; class="notranslate">\; R</span>}}_{\mathrm{<span\; class="notranslate">\; 2</span>}}}{{\mathrm{<span\; class="notranslate">\; <figure-callout\; id="3"\; label="R"\; filenames="C200710053294E00132.png,C200710053294E00142.png"\; state="\{\{state\}\}">R</figure-callout></span>}}_{\mathrm{<span\; class="notranslate">\; 3</span>}}}\mathrm{<span\; class="notranslate">\; ln</span>}\mathrm{<span\; class="notranslate">\; N</span>}\frac{<span\; class="notranslate">\; \&PartialD;</span>{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; T</span>}}}{<span\; class="notranslate">\; \&PartialD;</span>\mathrm{<span\; class="notranslate">\; T</span>}}$

而

通过调整R2与R3的比值就可以在理论上实现该温度下的零温度系数。实际中，很难达到很低的温度系数，而在本发明中，在0.6μm的Bi-CMOS工艺库下进行H-spice仿真得出，温度系数在-20--125℃范围内达到40ppm/℃以下，这在Bi-CMOS工艺中是一个非常低的数值。在典型的带隙结构如图1中，只有保证NPN晶体管Q1和Q2的集电极电流相等才能使得温度系数在理论上达到很小，但是由于运放的输入阻抗不是无穷大等原因，二者的集电极电流很难完全匹配，所以温度系数不是很理想。但是，在本发明的结构中就能很好的保证NPN晶体管Q1、Q2两者的集电极电流精确相等。首先，从大信号的角度出发，V_X＝V_REF-V_BE，Q3，而V_Y＝V_REF-V_BE，Q5，这就保证了V_X＝V_Y，从而保证了流过NPN晶体管Q1和Q2的集电极电流精确相等；其次，从小信号角度分析，当NPN晶体管Q1和Q2的集电极电流有微小变化时，通过两级运放的深度负反馈作用，来进行调整NPN晶体管Q1和Q2的静态工作点，从而保证二者的集电极电流精确相等。At room temperature (T=300K),

and

The zero temperature coefficient at this temperature can be theoretically realized by adjusting the ratio of R2 and R3. In practice, it is difficult to achieve a very low temperature coefficient, but in the present invention, the H-spice simulation is carried out under the 0.6 μm Bi-CMOS process library, and the temperature coefficient reaches 40ppm/ Below ℃, which is a very low value in Bi-CMOS process. In the typical bandgap structure shown in Figure 1, only by ensuring that the collector currents of NPN transistors Q1 and Q2 are equal can the temperature coefficient be theoretically small, but because the input impedance of the op amp is not infinite, the set of the two The electrode currents are difficult to match perfectly, so the temperature coefficient is not very ideal. However, in the structure of the present invention, it can well ensure that the collector currents of the NPN transistors Q1 and Q2 are exactly equal. First, from the perspective of large signals, V _X =V _REF -V _{BE, Q3} , and V _Y =V _REF -V _{BE, Q5} , which ensures that V _X =V _Y , thus ensuring the flow through the NPN transistor Q1 It is precisely equal to the collector current of Q2; secondly, from the small signal point of view, when the collector currents of NPN transistors Q1 and Q2 have slight changes, the NPN transistors Q1 and Q2 are adjusted through the deep negative feedback effect of the two-stage op amp The quiescent operating point, so as to ensure that the collector currents of the two are exactly equal.

In addition, the bias current _I0 of the NPN transistors Q1, Q2, PNP transistors Q3 and Q4 is provided by the constant current source circuit 7, and the specific realization is as follows: in the constant current source circuit 7, by V _{BE, Q8} =V _{BE, Q1} +I ₀ R ₄ and $V_{\mathrm{BE}}=V_T\ln \left(\frac{I_C}{I_S}\right)$ have to: $I_0=\frac{V_T\ln m}{{\mathrm{<figure-callout\; id="4"\; label="R"\; filenames="C200710053294E00132.png,C200710053294E00142.png"\; state="\{\{state\}\}">R</figure-callout>}}_4},$ Wherein, M is the ratio of the emitter areas of the NPN transistors Q1 and Q8. The advantage of providing bias in this way is that no external bias is required, the performance is stable, and the layout area is saved.

The following example is used for illustration, and this embodiment is only a further detailed description of the present invention, and does not imply any limitation to the present invention.

As shown in FIG. 4 , the self-bias circuit 1 includes resistors R5 , R6 , R7 and R8 , and also includes NPN transistors Q9 and Q10 and PMOS transistors M1 and M2 . One end of the resistor R5 is connected to the input end, and the other end is connected to the source of the PMOS transistor M1; one end of the resistor R6 is connected to the input end, and the other end is connected to the source of the PMOS transistor M2; one end of the resistor R8 is connected to the emitter of the NPN transistor Q10, The other end is grounded. The gate potentials of the PMOS transistors M1 and M2 are the same, and both are connected to the drain of the PMOS transistor M2; the drain of the PMOS transistor M1 is connected to the resistor R7. The base and collector of the NPN transistor Q9 are connected together to the base of the NPN transistor Q10 and the other end of the resistor R7, and the emitter of the NPN transistor Q9 is grounded. The collector of the NPN transistor Q10 is connected to the drain of the PMOS transistor M2, and the emitter is connected to the resistor R8.

The configuration of the bandgap core circuit 3 is the same as that shown in FIG. 3 .

The adjustment circuit 2 is composed of a PMOS transistor M3. The source of the PMOS transistor M3 is connected to the power supply voltage, the gate is connected to the gate of the PMOS transistor M2 in the self-bias circuit 1 , and the drain is connected to the emitter of the PNP transistor Q3 in the bandgap core circuit 3 .

The start-up circuit 4 includes resistors R9 and R10, and NMOS transistors M4 and M5. One end of the resistor R9 is connected to the power supply voltage V _IN , and the other end is connected to the drain of the NMOS transistor M4; one end of the resistor R10 is connected to the drain of the NMOS transistor M4, and the other end is connected to the gate of the NMOS transistor M5. The gate of the NMOS transistor M4 is connected to the drain of the PMOS transistor M1 in the self-bias circuit 1, and the source is grounded; the drain of the NMOS transistor M5 is connected to the collector of the NPN transistor Q10 in the self-bias circuit 1, and the source is grounded.

The magnitude of the current flowing through the PMOS transistor M2 in the self-bias circuit 1 is determined by the micro-current source composed of NPN transistors Q9, Q10 and resistor R8, specifically:

I _PTAT =ΔV _BE /R ₈ =V _T lnN/R ₈

This current acts through the self-biasing of the self-biasing circuit 1 and thus is independent of the supply voltage V _IN . Resistors R5 and R6 constitute source followers of PMOS transistors M1 and M2, which further ensures the independence of the self-bias circuit from the power supply voltage. However, there is a very important problem in the bias circuit 1 that has nothing to do with the power supply, which is the existence of "degenerate" bias points. For example, in the implementation circuit of Figure 4, if all transistors deliver zero current when the power supply is turned on, they can remain off indefinitely because the self-bias circuit 1 allows zero current to be delivered across them. Therefore, based on the above situation, the circuit of the present invention introduces the start-up circuit 4 to solve the existence of the "degenerate" bias point. The introduction of the starting circuit 4 will inevitably increase the power consumption, which is expected in the circuit of the present invention. Therefore, the power consumption can be reduced with the resistor R7. The principle is as follows: when the starting circuit starts to work, since the current flowing through the resistor R7 in the self-bias circuit 1 is zero, the voltage V _BE of the starting circuit will be added to the NPN transistor Q9, so that the NPN transistor Q9 is turned on, and the NPN transistor After Q9 is turned on, a current irrelevant to the power supply will be generated on the self-bias circuit 1, and a voltage drop will be generated on the resistor R7, so that the potential of point P is greater than V _BE , so that the startup circuit is turned off, which is extremely The power consumption is greatly reduced. In addition, the bandgap core circuit 3 consumes very little current under the same input voltage due to its simple structure, thereby reducing power consumption.

The current generated in the self-bias circuit 1 is almost independent of the power supply voltage, which makes the input voltage have a larger input range. Moreover, when the current flows through the PMOS transistor M2, the gate voltage of the PMOS transistor M2 is determined according to the saturation leakage current equation of the PMOS transistor M2, and the gate voltage is the bias voltage of the PMOS transistor M3 in the adjustment circuit 3 . The PMOS transistor M3 can also be called a voltage regulator transistor, because when the power supply voltage V _IN increases, the I _PTAT current basically remains unchanged, so according to the saturation current equation, it can be known that the gate voltage of the PMOS transistor M2 will also increase correspondingly , that is to say, the gate potential of the PMOS transistor M3 increases with the increase of the source potential, and the voltage between the gate and source of the PMOS transistor M3 does not change much, so the current flowing through the PMOS transistor M3 is also basically The change is not big, but slightly smaller, so a slight drop in the leakage current of the PMOS transistor M3 will make the output of the bandgap slightly smaller, which is about -ΔV _REF . And when Vin becomes larger, the bandgap output voltage will also become slightly larger, about +ΔV _REF , and +ΔV _REF ≈-ΔV _REF . It can be seen that the adjustment circuit 2 is actually the negative feedback circuit of the bandgap core circuit 3, so as to ensure that the bandgap output voltage V _REF in the bandgap core circuit 3 has nothing to do with the power supply voltage, thereby also improving the power supply rejection ratio of the entire circuit .

In addition, the circuit structure of the present invention introduces the idea of "local power supply" to further improve the power supply rejection ratio. That is to say, in the bandgap core circuit 3, if we can introduce a power supply that has little correlation with the power supply voltage V _IN to power the bandgap core circuit 3, then its PSRR will definitely increase. In fact, the circuit structure of the present invention utilizes this idea, wherein the "local power supply" mentioned above is the bandgap output V _REF . By adjusting the PMOS transistor M3 in circuit 2, the correlation between V _REF and V _IN has dropped a lot, and in the bandgap core circuit 3, all devices are directly powered by the "local power supply" V _REF Therefore, its PSRR can also be greatly improved. The H-spice simulation results based on the 0.6μm Bi-CMOS process library are shown in Figure 5. It can be seen from Figure 5 that the power supply rejection ratio PSRR of the bandgap output is very high under the three models of TT, SS and FF.

Under the direct current condition, the circuit of the present invention has a very small adjustment rate of the bandgap output voltage. The specific analysis is as follows: When the input voltage fluctuates in a large range, by adjusting the function of the PMOS transistor M3 in the circuit 2, V _REF changes in a small range, and V _REF is further affected by the operational amplifier in the bandgap core circuit 3 The effect of deep negative feedback, the result makes V _REF basically not affected by the change of input voltage V _IN . Under the 0.6μm Bi-CMOS process, it is simulated by H-spice (the simulation result is shown in Figure 5), which verifies the above analysis very well.

Claims (4)

1. A high power supply rejection bandgap reference source, characterized by: the band-gap power supply comprises a self-biasing circuit (1), an adjusting circuit (2), a band-gap core circuit (3) and a starting circuit (4); wherein,

the band gap core circuit (3) comprises NPN transistors Q1, Q2, Q6, Q7 and Q8, PNP transistors Q3, Q4 and Q5, resistors R1, R2, R3, R4 and a capacitor C1; bases of NPN transistors Q1 and Q2 are respectively connected with two ends of a resistor R3, emitters are connected together and are commonly connected with the resistor R4, and the other end of the resistor R4 is grounded; the collectors of the NPN transistor Q1 and the PNP transistor Q3 are connected together, and the NPN crystalThe collectors of the transistor Q2 and the PNP transistor Q4 are connected together; the base potentials of the PNP transistor Q3 and the PNP transistor Q4 are the same, and the emitter potentials are connected with the reference output voltage V_REFThe above step (1); the emitter of the PNP transistor Q5 is connected to the reference output voltage V_REFThe upper and base electrodes are connected with the collectors of the NPN transistor Q2 and the PNP transistor Q4, the emitter electrode of the NPN transistor Q6 is grounded, the base electrode is connected with the base electrode of the NPN transistor Q8, the collectors of the PNP transistor Q5 and the NPN transistor Q6 are connected together and are commonly connected with the base electrode of the NPN transistor Q7; the emitter and collector of NPN transistor Q7 are grounded and reference output voltage V, respectively_REF(ii) a The collector and the base of the NPN transistor Q8 are connected together and connected to the resistor R3; one end of the resistor R2 is connected to the resistor R3, and the other end is connected to the reference output voltage V_REFThe above step (1); one end of the resistor R1 is connected with the base of the NPN transistor Q7, and the other end is connected with the capacitor C1; the other end of the capacitor C1 is connected with the base of the PNP transistor Q5; reference output voltage V_REFThe output end is connected with a peripheral circuit;

the starting circuit (4) is operated at a supply voltage V_INWhen the power is on, the power works, current is generated and is transmitted to the self-bias circuit (1) to drive the self-bias circuit (1) to be conducted; the self-bias circuit (1) starts to be conducted after receiving the current provided by the starting circuit (4), and generates a power supply voltage V through the self-bias action_INAn unrelated bias voltage is transmitted to the adjusting circuit (2), and the starting circuit (4) is closed; after receiving the bias voltage output by the self-bias circuit (1), the adjusting circuit (2) generates constant current through self adjusting action and outputs the constant current to the band gap core circuit (3); the band-gap core circuit (3) generates a band-gap reference voltage V through the operation of the band-gap core circuit after receiving the constant current provided by the adjusting circuit (2)_REFAnd takes it as the output of the whole band-gap reference source.

2. The bandgap reference source as recited in claim 1, wherein: the self-bias circuit (1) comprises resistors R5, R6, R7 and R8, NPN transistors Q9 and Q10, and PMOS transistors M1 and M2; one end of the resistors R5 and R6 is connected with the power supply voltage V_INThe other end of the resistor R5 is connected with the source of the PMOS tube M1The other end of the resistor R6 is connected with the source electrode of the PMOS tube M2; one end of the resistor R8 is connected with the emitter of the NPN transistor Q10, and the other end is grounded; the gates of the PMOS tubes M1 and M2 are connected with the drain of the PMOS tube M2, and the drain of the PMOS tube M1 is connected with the resistor R7; the base and the collector of the NPN transistor Q9 are connected together and commonly connected with the base of the NPN transistor Q10 and the other end of the resistor R7, and the emitter of the NPN transistor Q9 is grounded; the collector of the NPN transistor Q10 is connected to the drain of the PMOS transistor M2, and the emitter is connected to the resistor R8.

3. The bandgap reference source as claimed in claim 1 or 2, wherein: the regulating circuit (2) is composed of a PMOS tube M3, and the source electrode of the PMOS tube M3 is connected with the power supply voltage V_INThe grid is connected with the grid of a PMOS transistor M2 in the self-bias circuit (1), and the drain is connected with the emitter of a PNP transistor Q3 in the band gap core circuit (3).

4. The bandgap reference source as recited in claim 3, wherein: the starting circuit (4) comprises resistors R9 and R10, and NMOS tubes M4 and M5; one end of the resistor R9 is connected with the power supply voltage VIN, and the other end is connected with the drain electrode of the NMOS tube M4; one end of the resistor R10 is connected with the drain electrode of the NMOS tube M4, and the other end is connected with the grid electrode of the NMOS tube M5; the grid electrode of the NMOS tube M4 is connected with the drain electrode of the PMOS tube M1, and the source electrode is grounded; the drain of the NMOS transistor M5 is connected to the collector of the NPN transistor Q10, and the source is grounded.

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