CN100483298C - Automatic clock speed control - Google Patents

Abstract

Clock speed is controlled based upon the supply voltage to a digital device. When the supply voltage is below a reference voltage the clock speed will be slower than if the supply voltage is above the reference voltage. A phase-lock-loop (PLL) may be used to generate a higher frequency that is an integer multiple of a reference oscillator. The clock speed will be proportional to the frequency multiplication of the PLL when the faster clock speed is selected. A multiplexer is used to switch between different frequency sources, and a timer can be used to insure stable operation of the PLL. A status configuration register has status and control bits for indicating and controlling operation of the clock speed control. A universal serial bus (USB) device can operate at a slower clock with reduced operating voltage, and at a faster clock with increased operating voltage.

Description

Digital display circuit with selectable clock speed

Technical field

The present invention relates to digital display circuit, more particularly, relate to the clock speed control in the digital display circuit that can change based on available mains voltage.

Background technology

Digital display circuit uses clock to drive or progressively carry out the operation and the information transmission on the data bus of digital display circuit of sequential and locking digital circuit.Speed dependent during the digital circuit reliable operation is in the supply voltage that offers these digital circuits.Higher operating voltage allows digital circuit to operate with clock speed faster.Yet, have some digital display circuits, even it may be by battery-operated and also necessary ongoing operation when cell voltage reduces.Clock speed makes the more power of digital circuit consumption equally, faster.

USB (universal serial bus) (USB) device just is being used to the multiple application in the digital display circuit.The USB device can be used in the multiple application for the general compatibility of many dissimilar digital devices.Yet, these different application have been forced the operating parameter ability of the required broad range of USB device, and for example computer operation of carrying out with full voltage and the power that uses the cell voltage supply are operated (power versus remote field operation) with the far field.The former benefits from high data processing amount (fast clock speed), and the latter benefits from low operating voltage and power consumption (slow clock speed).

Therefore, need the digital device that to operate with the supply voltage and the power consumption of broad range with USB interface.

Summary of the invention

The present invention is by providing a kind of other shortcoming and defective that is used for solving based on equipment, system and method that the supply voltage of the digital device with USB (universal serial bus) (USB) interface capability (hereinafter referred to as " USB device ") is controlled clock speed above pointed problem and existing technologies.As used herein clock speed refers to the oscillator frequency that is used to produce clock, and frequency is high more, and clock speed is just fast more.

In order to obtain maximum usb data transmittability, the USB device must move with the clock speed of 48MHz.With this clock speed, need about four (4) volt or bigger power supplys.Yet, for the USB device, there is the multiple application that lower voltage available supply and limited power capacity are only arranged, for example wherein the USB device will use the low-power data record of battery operation in the long period section.For saving power, need low voltage and USB device to operate with clock speed far below 48MHz.Yet, if this USB device is also with the basic computer with enough voltage available and power (base computer) when using, according to voltage available and power and a plurality of clock speeds (for example, fast, in or slow) between the ability that automaticallyes switch have superiority most.Because USB is a dynabus, thus can remove the USB device at any time, and the USB device must be with slower clock speed operation when supply voltage reduces.

According to a particular exemplary embodiment of the present invention, clock speed can be finished by forbidding phase-locked loop (PLL) frequency multiplier from the reduction of 48MHz.Forbid this PLL multiplier if drop to (for example) four (4) volt at voltage when following, the USB device can continue to operate with (for example) 12MHz under this low voltage so.Return when increasing to five volts when the USB device is inserted back into full supply voltage (for example usb hub) and voltage, the PLL multiplier will be reactivated and can be provided with a flag with notice USB function software: the USB device now can use full speed degree (48MHz) clock operation.

Can expect and within the scope of the present invention, other multiplied clock value (for example using PLL and/or a plurality of clock oscillator of selecting) can be by the control of voltage level sensing circuit, so that lower voltage will cause lower clock speed and higher voltage will cause clock speed faster.

A technical advantage of the present invention is that the USB device operates in its clock frequency and voltage limit.

Another technical advantage is the reliable and unbroken USB device operation on the operating voltage of broad range.

In view of the content that this paper has disclosed, the those skilled in the art should easily see other technical advantage.

Description of drawings

Can obtain more complete understanding referring to following description in conjunction with the drawings to this disclosure and its advantage, in the accompanying drawings:

Fig. 1 is the schematic block diagram with digital display circuit of the USB port that is used to be connected to the USB device; With

Fig. 2 is the synoptic diagram according to the USB clock circuit with clock speed of being controlled by supply voltage of particular exemplary embodiment of the present invention.

The present invention can have multiple modification and replacement form.Specific embodiment of the present invention is showed by way of example in the accompanying drawings, and is described in detail in this article.Yet, should be appreciated that the description to specific embodiment that this paper stated is not intended to the present invention is limited to the particular form that is disclosed.But, be intended to contain all modifications, substitute and the equivalent that belong in the spirit and scope of the invention that defines by appended claims.

Embodiment

Now, schematically illustrated the details of one exemplary embodiment of the present invention in the accompanying drawing referring to accompanying drawing.Similar elements in the accompanying drawing will be represented by same numbers, and like will be by the same numeral with different lower case letter suffix.

As used herein clock speed refers to the oscillator frequency that is used to produce clock, and frequency is high more, and clock speed is just fast more.

Referring to Fig. 1, describe to have the schematic block diagram of the digital display circuit of the USB port that is used to be connected to the USB device.Described digital display circuit (generally by numeral 100 expressions) comprises the USB transceiver 106 that a digital device 102, a USB module and clock 104 and are connected to usb bus 108.Described digital device 102 can be (such as but not limited to) digital processing unit, microprocessor, microcontroller, digital signal processor (DSP), special IC (ASIC), programmable logic array (PLA) and analog.Described USB module and clock 104 have a USB clock, and its speed can be controlled based on system voltage.

Referring to Fig. 2, it describes the synoptic diagram according to the USB clock circuit with clock speed of being controlled by supply voltage of particular exemplary embodiment of the present invention.Described USB clock circuit (generally by numeral 200 expressions) can be the part of USB module and clock 104 (Fig. 1).One band gap voltage reference 202 is used in combination with a voltage comparator 202, and described voltage comparator provides a signal 206 to enable a PLL 210 rightly when operating voltage (Vdd) 208 is in sufficiently high voltage.Described signal 206 is suitable for being provided with the PLL armed bit 212 in the PLL control register 214.Digital display circuit 100 then is provided with the startup PLL position 216 in the described PLL control register 214.When described PLL armed bit 212 with when to start PLL position 216 all be effective, start a PLL timer 218 and described PLL 210.Described PLL timer 218 count down to an adequate value makes PLL 210 become stable so that the time to be provided.When PLL timer 218 reached its schedule time (becoming effectively), it exported rising.When PLL timer 218 is effectively (to export high), and PLL armed bit 212 and to start PLL position 216 all be effectively when (output is high), one makes a clock multiplexer 220 export from the PLL 210 that oscillator 222 is outputted to the higher multifrequency that is in oscillator 222 with door 226.When multiplexer 220 when oscillator 222 switches to PLL 210, PLL operation position 224 also is set up.Therefore, when multiplexer 220 when oscillator 222 switches to PLL 210, the output of the high-frequency of PLL 210 becomes system clock.

When operating voltage Vdd 208 begins to drop to the reference voltage of band gap voltage reference 202 when following, comparer 204 output signals 206 reduce.This will forbid PLL armed bit 212 and by two and door 226 and 228, clock multiplexer 220 will switch to lower frequency oscillator 222 as system clock.When comparer 204 output signals 206 reduce, decline marginal detector 230 will send a look-at-me (PLL IRQ) 232, and described signal will be sent out look-at-me to the operating system software of digital display circuit 100.Operating system software can determine new USB system clock speed by the state of the position in the consulting PLL control register 214.PLL armed bit 212 and PLL operation position 224 will all be low.Software can then take appropriate action to reconfigure digital display circuit to be used for low velocity USB operation.

Can be set to extra different voltage threshold by the extra voltage detection comparator and realize further power-saving.Each extra voltage threshold value can be used for enabling and will be suitable for alternative clock source or the frequency divider of available action voltage Vdd.

From particular exemplary embodiment angle the present invention has been described.According to the present invention, the parameter that is used for a system can be usually with specifying and selecting it to change with the design engineer who is used for required application.In addition, expection can be by the those skilled in the art based on teaching that this paper stated and easily other embodiment of design can be within the scope of the present invention, and the scope of the invention is defined by appended claims.Can different but equivalent mode revise and put into practice the present invention, described mode is conspicuous for the those skilled in the art and has benefited from the teaching that this paper states.

Claims (10)

1. digital display circuit with the clock speed that can select based on available mains voltage, described digital display circuit comprises:

One clock oscillator, it is in a first frequency;

One phase-locked loop, it has a phase-locked loop oscillator that is in a second frequency, and wherein said second frequency is the integral multiple of described first frequency;

One voltage comparator, it has an input and an output of being coupled to a supply voltage, and described output is in one first logic level and is in one second logic level when described supply voltage is less than or equal to described reference voltage during greater than a reference voltage at described supply voltage;

One clock multiplexer, it has first input of being coupled to described phase-locked loop oscillator, one is coupled to second input of described clock oscillator and an output of described clock oscillator or described phase-locked loop oscillator, the selection of wherein said clock oscillator or described phase-locked loop oscillator is by described voltage comparator output control, make and to export when being in described first logic level when described voltage comparator, described phase-locked loop oscillator is coupled to the output of described clock multiplexer and when described voltage comparator output was in described second logic level, described clock oscillator was coupled to described clock multiplexer and exports;

One phase-locked loop control register, it has

One phase-locked loop armed bit, it indicates described voltage comparator output when to be in described first logic level;

One phase-locked loop start bit, it controls phase-locked loop-timed device and when the phase-locked loop oscillator starts; With

Operation position, one phase-locked loop, it indicates the described output of described clock multiplexer when to be coupled to described phase-locked loop oscillator; With

One digital device, it is coupled to the phase-locked loop control register, and wherein said digital device reads and writes described phase-locked loop control register.

2. digital display circuit according to claim 1, it further comprises a band gap voltage reference that combines with described voltage comparator.

3. digital display circuit according to claim 1, it further comprises a timer to be used for postponing the output selection of described clock multiplexer till described phase-locked loop oscillator is stable.

4. digital display circuit according to claim 1, it further comprises a logic level change detecting device and when arrives described second logic level from described first logic level to be used to detecting described voltage comparator output.

5. digital display circuit according to claim 4, wherein said first logic level is a high logic level, and described second logic level is a low logic level, and described logic level change detecting device is a decline marginal detector.

6. digital display circuit according to claim 4, wherein said logic level change detecting device produce an interruption that offers described digital device when detecting described logic level change.

7. digital display circuit according to claim 1, wherein said second frequency are four times of described first frequency.

8. digital display circuit according to claim 1, wherein said digital device is selected from the group that is made up of a digital processing unit, microprocessor, microcontroller, digital signal processor, special IC and programmable logic array.

9. digital display circuit according to claim 1, wherein said clock multiplexer output is coupled to a USB (universal serial bus).

10. digital display circuit according to claim 1, wherein said reference voltage is for being beset with.

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