CN100486224C - Method and device for controlling ATM network flow based on FPGA - Google Patents
Method and device for controlling ATM network flow based on FPGA Download PDFInfo
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- 238000000034 method Methods 0.000 title claims abstract description 26
- 230000005540 biological transmission Effects 0.000 claims description 28
- 238000010586 diagram Methods 0.000 description 7
- 238000012545 processing Methods 0.000 description 5
- 238000006243 chemical reaction Methods 0.000 description 4
- 238000005538 encapsulation Methods 0.000 description 4
- 230000007547 defect Effects 0.000 description 3
- GNFTZDOKVXKIBK-UHFFFAOYSA-N 3-(2-methoxyethoxy)benzohydrazide Chemical compound COCCOC1=CC=CC(C(=O)NN)=C1 GNFTZDOKVXKIBK-UHFFFAOYSA-N 0.000 description 2
- FGUUSXIOTUKUDN-IBGZPJMESA-N C1(=CC=CC=C1)N1C2=C(NC([C@H](C1)NC=1OC(=NN=1)C1=CC=CC=C1)=O)C=CC=C2 Chemical compound C1(=CC=CC=C1)N1C2=C(NC([C@H](C1)NC=1OC(=NN=1)C1=CC=CC=C1)=O)C=CC=C2 FGUUSXIOTUKUDN-IBGZPJMESA-N 0.000 description 2
- YTAHJIFKAKIKAV-XNMGPUDCSA-N [(1R)-3-morpholin-4-yl-1-phenylpropyl] N-[(3S)-2-oxo-5-phenyl-1,3-dihydro-1,4-benzodiazepin-3-yl]carbamate Chemical compound O=C1[C@H](N=C(C2=C(N1)C=CC=C2)C1=CC=CC=C1)NC(O[C@H](CCN1CCOCC1)C1=CC=CC=C1)=O YTAHJIFKAKIKAV-XNMGPUDCSA-N 0.000 description 2
- 238000011161 development Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 230000006870 function Effects 0.000 description 2
- 230000003287 optical effect Effects 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 238000000605 extraction Methods 0.000 description 1
- 238000013467 fragmentation Methods 0.000 description 1
- 238000006062 fragmentation reaction Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 230000001360 synchronised effect Effects 0.000 description 1
- 238000012546 transfer Methods 0.000 description 1
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Abstract
This invention discloses the realizing ATM network flow control device and method based on FPGA.
Description
Technical Field
The invention relates to the technical field of flow control in a router, in particular to a device and a method for realizing ATM network flow control on the router based on FPGA.
Background
With the development of computing technology, various data transmission networks appear, and at present, there are two kinds of networks, one is an Internet Protocol (IP) packet network that transmits packets as a unit, and the other is an Asynchronous Transfer Mode (ATM) network that transmits cells as a unit. As a router based on IP packet switching, a line interface card for handling inter-conversion of IP packets into ATM cells is required when connecting an ATM network.
The current ATM line interface card mainly includes (as shown in fig. 1) an optical module 101, a physical layer chip 102, an SAR (Segment And read reasseble, or removable) chip 103, an FPGA (field programmable Gate Array) chip 104, And a network processor 105. The optical module 101 completes photoelectric conversion, the physical layer chip 102 completes functions of SDH (Synchronous Digital Hierarchy) frame extraction, cell encapsulation and the like, the SAR chip 103 completes functions of IP packet fragmentation, ATM cell reassembly, QoS (Quality of Service) Service and the like, and the FPGA chip 104 is used for connecting the SAR chip 103 and the network processor 105 to complete data conversion between the SAR chip 103 and the network processor 105. Because the data interfaces between the network processor and most chips are not consistent at present, data conversion is needed, and an FPGA chip is necessary in the system. With the development of semiconductor technology, the FPGA chip is larger in scale and cheaper, and the SAR chip can be replaced by the cheap FPGA chip. The flow control of the current ATM line interface card is completed by an SAR chip, and the system has the defects of complex design, high cost and the like.
Disclosure of Invention
The technical problem to be solved by the present invention is to provide a device and a method for implementing ATM network flow control based on FPGA, which are used to overcome the problems and defects of complex system and high cost caused by the fact that ATM network flow control in a router is implemented by a special SAR chip in the prior art.
In order to achieve the above object, the present invention provides a device for implementing ATM network flow control based on FPGA, which includes a network processor and a physical layer chip, and is characterized by further including:
an ATM cell memory for receiving ATM cells transmitted from said network processor and storing said ATM cells in blocks according to PVC channels;
a PVC management module, which is used for virtualizing the ATM cell memory into a plurality of FIFO queues according to PVC and managing the FIFO queues;
a PVC state buffer module for storing the next ATM cell sending time variable of each PVC channel;
a PVC bandwidth configuration module, which is used for configuring the bandwidth parameters of each PVC channel;
a flow control module for generating PVC channel number, inquiring the PVC management module, PVC state buffer module and PVC bandwidth configuration module, calculating whether the channel corresponding to the PVC channel number has ATM cell and whether it is allowed to read ATM cell, assembling ATM cell into cell frame and storing;
a cell frame sending module, which is used for reading the cell frame from the flow control module, performing ATM cell interval control and sending the cell frame without the frame header;
and the physical interface module is used for receiving the cell frame sent by the cell frame sending module and sending the cell frame to the physical layer chip.
The device for controlling the flow of the ATM network based on the FPGA comprises the following components: an external storage device and a memory interface module; the external storage device is used for storing ATM cells, and the memory interface module is used as an interface module for data exchange between an external RAM and internal logic of the FPGA.
The device for realizing ATM network flow control based on FPGA comprises: an ATM cell sending module, a cell frame buffer, a bandwidth control module and a reference time generating module; wherein
The ATM cell sending module is used for inquiring each PVC channel, generating the operation of inquiring the PVC management module, the PVC state cache module, the PVC bandwidth configuration module and the bandwidth control module, sending a read RAM address to the ATM cell memory, forming a cell frame by the read ATM cell and the parameter returned by the bandwidth control module according to a certain format, and storing the cell frame into the cell frame buffer;
the cell frame buffer is used for storing a FIFO queue of cell frames;
the bandwidth control module is used for maintaining a previous ATM cell sending time variable and a time interval number variable of the maximum bandwidth configured by the system, inquiring the condition that a next ATM cell sending time variable value returned by the PVC state cache module is respectively compared with a counting variable value of the reference time generation module and a previous ATM cell sending time variable value, determining whether the ATM cell sending module is allowed to read the ATM cell from the ATM cell memory at the next ATM cell sending time according to a comparison result, and maintaining the PVC channel state;
the reference time generation module is a counter and is used for generating the counting variable used as the judgment reference of the bandwidth control module and generating a signal for initializing the PVC state cache module.
The device for realizing ATM network flow control based on FPGA is characterized in that the physical interface module is a standard Utopia interface.
In order to achieve the above object, the present invention further provides a method for implementing ATM network flow control based on FPGA, which is suitable for the apparatus, and is characterized in that the method includes:
step 51, the ATM cell memory receives the ATM cell transmitted from the network processor and stores the ATM cell in blocks according to the PVC channel;
step 52, the flow control module generates a PVC channel number, continuously queries the PVC management module, the PVC state cache module and the PVC bandwidth configuration module, calculates whether the channel corresponding to the PVC channel number has an ATM cell and whether to allow reading the ATM cell, assembles the ATM cell into a cell frame and stores the cell frame;
step 53, the cell frame sending module reads the cell frame from the flow control module, performs ATM cell interval control, and sends the cell frame without the frame header;
step 54, the physical interface module receives the cell frame sent by the cell frame sending module and sends it to the physical layer chip.
The method for realizing ATM network flow control based on FPGA includes a step of initializing the PVC state buffer module through a PVC state initialization command sent by the flow control module between steps 51 and 52, and is used to point the next ATM cell pointers of all PVC channels to zero.
The method for implementing ATM network flow control based on FPGA includes, in step 52, a step of determining whether the channel corresponding to the PVC channel number has an ATM cell by querying a FIFO queue state of the channel corresponding to the PVC channel number returned by the PVC management module.
The method for controlling the flow of the ATM network based on the FPGA, wherein the step 52 further includes a step of determining whether to allow the ATM cell sending module to read the ATM cell from the ATM cell storage through a value returned by the bandwidth control module and the cell frame buffer.
In step 52, if the channel corresponding to the PVC channel number allows reading ATM cells, the ATM cell sending module reads ATM cells from the ATM cell memory, and adds an interval control word to the head of the ATM cells to form a cell frame and store the cell frame in the cell frame buffer, sets a cell frame flag bit, and waits for the cell frame sending module to read; and simultaneously writing the updated PVC state back to the PVC state cache module, and continuously querying the next PVC channel.
The method for implementing ATM network flow control based on FPGA further includes a step of determining whether the cell frame buffer contains a cell frame by the cell frame sending module querying the cell frame flag bit of the flow control module before step 53.
The method for controlling the flow of the ATM network based on the FPGA further includes a step of determining whether to allow the cell frame sending module to read the cell frame from the cell frame buffer before the step 53.
In step 53, the cell frame sending module starts an interval counter to obtain a current value of the counter, reads a cell frame header by querying a cell frame buffer to obtain an ATM cell interval parameter, and compares the current value of the counter with the ATM cell interval parameter to realize ATM cell interval control.
The method for realizing ATM network flow control based on FPGA is characterized in that if the ATM cell interval parameter value is smaller than the current value of the counter and the physical interface module allows to send ATM cells, the cell frame sending module sends the ATM cells to the physical interface module.
The invention provides a method and a device for simply realizing ATM network flow control based on FPGA, which solve the problems and defects of complex system and overhigh cost caused by the fact that the ATM network flow control in a router is realized by a special SAR chip in the prior art; compared with the prior art, the invention has the beneficial effects that:
the method and the device of the invention make the technical progress of realizing flow control by using the FPGA to replace a special SAR chip, achieve the effect of accurately controlling the ATM cell rate, save the system cost, improve the system reliability and the market competitiveness, and the like.
The invention is described in detail below with reference to the drawings and specific examples, but the invention is not limited thereto.
Drawings
FIG. 1 is a block diagram of an ATM line interface board system in the prior art;
FIG. 2 is a block diagram of ATM network flow control in accordance with the present invention;
FIG. 3 is a diagram illustrating PVC bandwidth configuration parameters used in the present invention;
FIG. 4 is a cell frame encapsulation diagram used in the present invention;
FIG. 5 is a flow chart of the PVC channel bandwidth control process of the present invention;
fig. 6 is a flow chart of ATM cell processing according to the present invention.
Detailed Description
The following describes in further detail the implementation of the technical solution for implementing ATM network flow control based on FPGA with reference to the accompanying drawings.
Fig. 2 is a block diagram of an ATM network flow control module according to the present invention; FIG. 3 is a diagram illustrating PVC bandwidth configuration parameters used in the present invention; FIG. 4 is a diagram of cell frame encapsulation used in the present invention. The device for realizing ATM network flow control based on FPGA of the invention comprises: hardware module part, software module part.
The hardware module part includes: the ATM cell memory 201 includes an external storage device 202 and a memory interface module 203. The external storage device 202 is a large-capacity RAM (random access Memory) for storing ATM cells; the memory interface module 203 is an interface module for data exchange between an external RAM and internal logic of the FPGA; the ATM cell memory 201 is controlled by the PVC management block 204 and the flow control block 211 for reading and writing.
The software module part comprises the following modules:
the PVC management module 204 provides a write RAM address for the ATM cell memory 201, virtualizes the ATM cell memory 201 into a plurality of FIFO (First-In First-Out) queues according to PVC (Permanent Virtual links), and manages the status of each FIFO queue to be queried by the flow control module 211.
The PVC state buffer module 205, which is an internal RAM of the FPGA, stores the next ATM cell transmission Time0 of each PVC channel, and is queried by the flow control module 211; and meanwhile, receiving a state initialization command sent by the flow control module 211, and performing zero clearing operation on the state of each PVC.
The PVC bandwidth configuration module 206 is an internal RAM of the FPGA, and is configured to configure bandwidth parameters of each PVC channel, where the bandwidth parameters are obtained by calculating a time interval (Step) between two ATM cell clocks adjacent to the same PVC channel with reference to a reference clock of 19.44MHz (as shown in fig. 3), and configuring the obtained parameters to the PVC bandwidth configuration module 206 through a CPU (host processor) interface.
The flow control module 211 is a core module for implementing ATM cell flow control, and the module 211 determines when to send the ATM cell of which PVC channel, and also determines the interval between two adjacent ATM cells. The flow control module 211 further includes four modules, i.e., an ATM cell transmitting module 207, a cell frame buffer 208, a bandwidth control module 209, and a reference time generating module 210. Wherein,
the ATM cell sending module 207 is a state machine, continuously polls each PVC channel, generates operations of modules such as the PVC management module 204, the PVC state buffer module 205, the PVC bandwidth configuration module 206, and the bandwidth control module 209, sends a read RAM address to the ATM cell memory 201, forms a cell frame with the read ATM cell and the parameter Step0 returned by the bandwidth control module 209 according to the format of fig. 4, and stores the cell frame in the cell frame buffer 208, where the parameter Step0 is an ATM cell interval parameter.
The cell frame buffer 208 is a FIFO queue for storing ATM cell frames.
The bandwidth control module 209 is an arithmetic unit, and maintains two variables, one is the sending Time of the last ATM cell 1, and the other is the Time interval number Step1 of the maximum bandwidth configured by the system. The bandwidth control module 209 compares the Time0 value returned by the PVC state buffer module 205 with the Counter _1 value of the reference Time generation module 210 and the value of the Time1 of the previous ATM cell, determines whether to allow the ATM cell transmission module 207 to read an ATM cell from the ATM cell memory 201 at this Time, and maintains the PVC channel state.
The reference time generation module 210 is a Counter _1, which is a reference clock parameter, and 19.440MHz clock is its clock source, and the reference time generation module cycles once every second, and is used as a reference for the decision of the bandwidth control module 209, and generates a signal for initializing the PVC state buffer module 205.
The cell frame transmitting module 212, which is an executing module for implementing ATM cell flow control, maintains a Counter _2 for calculating the interval between adjacent ATM cells. The cell frame sending module 212 continuously queries the flow control module 211, and if the flow control module 211 allows reading a cell frame, first reads the cell header Step0, and compares the header Step0 with the Counter _ 2; if the value of Step0 is less than the value of Counter _2 and physical interface module 213 allows sending of ATM cells, the ATM cells are sent to physical interface module 213, otherwise wait for physical interface module 213 to allow sending of ATM cells.
The physical interface module 213 is a standard Utopia interface, and sends the ATM cell sent by the cell frame sending module 212 to the physical layer chip 102, so as to implement flow control.
Fig. 5 is a flow chart of the PVC channel bandwidth control processing according to the present invention. With reference to fig. 2, the steps for the data processing of the bandwidth control module 209 of the present invention are as follows:
step a, reading the PVC channel state parameters, after the ATM cell sending module 207 sends out the query command, the bandwidth control module 209 reads back the next ATM cell sending Time0 of the PVC channel from the PVC state buffer module 205, and simultaneously reads back the PVC channel bandwidth configuration parameter Step of the system from the PVC bandwidth configuration module 206.
Step b, comparing the Time0 with the Counter _1 and the Time1, the bandwidth control module 209 compares the next ATM cell transmission Time0 with the reference clock parameter Counter _1 and the last ATM cell transmission Time1, respectively, to determine whether to allow the ATM cell transmission module 207 to transmit the ATM cell.
And c, judging whether the Time0 is less than or equal to the Counter _1, if the next ATM cell sending Time0 is less than or equal to the reference clock parameter Counter _1, turning to the step d for execution, and if not, turning to the step i for execution.
And d, judging whether the Time0 is less than or equal to the Time1, if the next ATM cell transmission Time0 is less than or equal to the last ATM cell transmission Time1 of the system, turning to the step e for execution, and if not, turning to the step g for execution.
And e, judging whether the Time1 is less than or equal to the Counter _1, if the sending Time of the last ATM cell of the system, namely the Time1, is less than or equal to the reference clock parameter Counter _1, turning to the step f for execution, and otherwise, turning to the step h for execution.
Step f, updating each parameter, updating parameters Time0 and Time1, and returning to the ATM cell interval parameter Step0 for the ATM cell sending module 207 to use. At this Time, the value of the next ATM cell transmission Time0 is the sum of Counter _1 and Step, and the value of the previous ATM cell transmission Time1 is the current value of Counter _ 1. The ATM cell spacing parameter Step0 is zero.
And Step g, updating each parameter, updating the parameters Time0 and Time1, and returning the ATM cell interval parameter Step0 for the ATM cell sending module 207 to use. At this Time, the value of the next ATM cell transmission Time0 is the sum of Counter _1 and Step, and the value of the previous ATM cell transmission Time1 is the current value of Counter _ 1. The ATM cell spacing parameter Step0 is zero.
And Step h, updating each parameter, updating the parameters Time0 and Time1, and returning the ATM cell interval parameter Step0 for the ATM cell sending module 207 to use. At this Time, the value of the next ATM cell transmission Time0 is the sum of Time1 and Step, and the value of the previous ATM cell transmission Time1 is unchanged. The ATM cell spacing parameter Step0 is zero.
And step i, judging whether the Time0 is less than or equal to the Time1, if the next ATM cell transmission Time0 is less than or equal to the last ATM cell transmission Time1 of the system, turning to the step n for execution, and if not, turning to the step j for execution.
Step j, judging whether the Time1 is less than or equal to the Counter _1, if the sending Time of the last ATM cell of the system is less than or equal to the reference clock parameter Counter _1, turning to step k to execute, otherwise, turning to step. And (6) executing.
Step k, updating parameter Step0, the value of ATM cell interval parameter Step0 is the difference between the next ATM cell transmission Time0 and the reference clock parameter Counter _ 1.
Step1, judging whether Step0 is less than or equal to Step1, if the ATM cell interval parameter Step0 is less than or equal to the time interval number Step1 of the maximum bandwidth of the system configuration, turning to Step m for execution, otherwise, turning to Step q for execution.
And Step m, updating each parameter, updating the parameters Time0 and Time1, and returning the ATM cell interval parameter Step0 for the ATM cell sending module 207 to use. At this Time, the value of the next ATM cell transmission Time0 is the sum of Time0 and Step, and the value of the previous ATM cell transmission Time1 is the Time0 value before updating. The ATM cell spacing parameter Step0 remains unchanged.
And Step n, updating each parameter, updating the parameters Time0 and Time1, and returning the ATM cell interval parameter Step0 for the ATM cell sending module 207 to use. At this Time, the value of the next ATM cell transmission Time0 is the sum of Time1 and Step, and the value of the previous ATM cell transmission Time1 remains unchanged. The ATM cell spacing parameter Step0 is zero.
And Step o, updating the parameter Step0, wherein the value of the ATM cell interval parameter Step0 is the difference between the next ATM cell transmission Time0 and the previous ATM cell transmission Time 1.
In step p, the transmission permission flag is set, and the bandwidth control module 209 sets a flag bit indicating that the ATM cell transmission module 207 is permitted to read an ATM cell from the ATM cell memory 201.
And step q, returning, finishing the judgment, storing the next ATM cell sending Time Time0 back to the PVC state cache module 205, and returning to step a to wait for the next operation.
FIG. 6 is a flow chart of ATM cell processing according to the present invention. The processing steps for an incoming ATM cell of the present invention are as follows:
step1, initialize the PVC state buffer module 205, and make the next ATM cell pointers of all PVC channels point to zero. This initialization operation is performed once per second, controlled by the reference time generation module 210.
And 2, judging whether to perform initialization operation, inquiring the state of the reference time generation module 210, returning to the step1 to execute the initialization operation if the one-second timing is finished, and otherwise, continuing to execute the next operation.
And step 3, generating a PVC channel number, and generating the PVC channel number to be inquired by the ATM cell sending module 207.
And 4, inquiring the PVC channel, and inquiring the PVC management module 204 according to the PVC channel number generated in the step 3.
And step 5, judging whether the inquired PVC channel has ATM cell transmission, and when inquiring the PVC management module 204, the PVC management module 204 returns the FIFO queue state of the corresponding PVC channel. If there is ATM cell to send, then go to step 6 to execute, otherwise return to step 2.
And 6, inquiring the bandwidth controller, and inquiring the bandwidth control module 209 according to the PVC channel number generated in the step 3.
Step 7, judging whether to allow reading, the ATM cell transmission module 207 decides whether to read an ATM cell from the ATM cell memory 201 according to the values returned by the bandwidth control module 209 and the cell frame buffer 208. If an ATM cell is allowed to be read, the next step is carried out in step 8, otherwise, the step 2 is returned.
Step 8, reading the ATM cell and encapsulating the frame, the ATM cell sending module 207 reads back the start address of the ATM cell from the PVC management module 204, reads an ATM cell from the ATM cell memory 201, and assembles a cell frame according to the value Step0 returned by the polling bandwidth control module 209.
Step 9, storing the cell frame, the ATM cell sending module 207 storing the assembled cell frame into the cell frame buffer 208, and setting the cell frame flag bit, indicating to the cell frame sending module 212 that at least one complete cell frame exists in the cell frame buffer 208.
Step 10, returning to step 2 after the cell frame encapsulation is finished.
Step 11, inquiring the cell frame buffer, the cell frame transmitting module 212 continuously inquires the cell frame flag bit of the flow control module 211.
Step 12, judging whether there is cell frame in the cell frame buffer 208, if yes, going to the next step, otherwise, returning to step 11.
Step 13, reading the cell frame header, firstly, the cell frame sending module 212 reads the cell frame header of only one word from the cell frame buffer 208, and obtains the ATM cell interval parameter Step 0.
Step 14, the Counter _2 is queried, and the cell frame transmitting module 212 reads the current value of the Counter _ 2.
Step 15, determining whether to allow the ATM cell to be transmitted, the cell frame transmitting module 212 compares Step0 with the value of Counter _2, if the value of Step0 is less than or equal to the value of Counter _2, go to the next Step, otherwise, go back to Step 14.
And step 16, clearing the Counter _2 value, and continuing counting after the Counter _2 is cleared.
Step 17, sending the ATM cell, the cell frame sending module 212 continues to read the subsequent part of the cell frame, i.e. the cell frame without the frame header, from the cell frame buffer 208, and sends the ATM cell to the physical interface module 213.
Step 18, returning, after one cell frame is sent, returning to step 11.
The method and the device of the invention make the technical progress of realizing flow control by using the FPGA to replace a special SAR chip, achieve the effect of accurately controlling the ATM cell rate, save the system cost, improve the system reliability and the market competitiveness, and the like.
The present invention may be embodied in other specific forms without departing from the spirit or essential attributes thereof, and it should be understood that various changes and modifications can be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.
Claims (13)
1. The utility model provides a device based on FPGA realizes ATM network flow control, includes network processor, physical layer chip, its characterized in that still includes:
an ATM cell memory for receiving ATM cells transmitted from said network processor and storing said ATM cells in blocks according to PVC channels;
a PVC management module, which is used for virtualizing the ATM cell memory into a plurality of FIFO queues according to PVC and managing the FIFO queues;
a PVC state buffer module for storing next ATM cell sending time variable of each PVC channel;
a PVC bandwidth configuration module for configuring bandwidth parameters of each PVC channel;
a flow control module for generating PVC channel number, inquiring the PVC management module, PVC state buffer module and PVC bandwidth configuration module, calculating whether the channel corresponding to the PVC channel number has ATM cell and whether it is allowed to read ATM cell, assembling ATM cell into cell frame and storing;
a cell frame sending module, which is used for reading the cell frame from the flow control module, performing ATM cell interval control and sending the cell frame without the frame header;
and the physical interface module is used for receiving the cell frame sent by the cell frame sending module and sending the cell frame to the physical layer chip.
2. An apparatus for controlling flow in an ATM network based on an FPGA as recited in claim 1, wherein said ATM cell memory further comprises: an external storage device and a memory interface module; the external storage device is used for storing ATM cells, and the memory interface module is used as an interface module for data exchange between the external storage device and the internal logic of the FPGA.
3. An apparatus for implementing ATM network flow control based on FPGA according to claim 1, wherein said flow control module further comprises: an ATM cell sending module, a cell frame buffer, a bandwidth control module and a reference time generating module; wherein
The ATM cell sending module is used for inquiring each PVC channel, generating the operation of inquiring the PVC management module, the PVC state cache module, the PVC bandwidth configuration module and the bandwidth control module, sending a read RAM address to the ATM cell memory, forming a cell frame by the read ATM cell and the parameter returned by the bandwidth control module according to a certain format, and storing the cell frame into the cell frame buffer;
the cell frame buffer is used for storing a FIFO queue of cell frames;
the bandwidth control module is used for maintaining a previous ATM cell sending time variable and a time interval number variable of the maximum bandwidth configured by the system, inquiring the condition that a next ATM cell sending time variable value returned by the PVC state cache module is respectively compared with a counting variable value of the reference time generation module and a previous ATM cell sending time variable value, determining whether the ATM cell sending module is allowed to read the ATM cell from the ATM cell memory at the next ATM cell sending time according to a comparison result, and maintaining the PVC channel state;
the reference time generation module is a counter and is used for generating the counting variable used as the judgment reference of the bandwidth control module and generating a signal for initializing the PVC state cache module.
4. An apparatus for implementing ATM network flow control based on FPGA according to claim 1, 2 or 3, wherein said physical interface module is a standard Utopia interface.
5. A method for controlling ATM network traffic based on FPGA adapted for use in the apparatus of claim 1, comprising:
step 51, the ATM cell memory receives the ATM cell transmitted from the network processor and stores the ATM cell in blocks according to the PVC channel;
step 52, the flow control module generates a PVC channel number, continuously queries the PVC management module, the PVC state cache module and the PVC bandwidth configuration module, calculates whether the channel corresponding to the PVC channel number has an ATM cell and whether to allow reading the ATM cell, assembles the ATM cell into a cell frame and stores the cell frame;
step 53, the cell frame sending module reads the cell frame from the flow control module, performs ATM cell interval control, and sends the cell frame without the frame header;
step 54, the physical interface module receives the cell frame sent by the cell frame sending module and sends it to the physical layer chip.
6. An FPGA-based method for controlling ATM network flow according to claim 5, further comprising a step of initializing said PVC state buffer module by a PVC state initialization command sent by the flow control module between said steps 51 and 52, for pointing the next ATM cell pointer of all PVC channels to zero.
7. The method of claim 5, wherein the step 52 further comprises a step of determining whether the channel corresponding to the PVC channel number has ATM cells by querying the FIFO queue status of the channel corresponding to the PVC channel number returned by the PVC management module.
8. An FPGA-based method of controlling flow in an ATM network as defined in claim 5, further comprising a step of determining whether to allow the ATM cell transmission module to read ATM cells from the ATM cell memory based on a value returned from the cell frame buffer by the bandwidth control module in step 52.
9. The method of claim 5, 6, 7 or 8 for controlling ATM network flow based on FPGA, wherein in step 52, if the channel corresponding to the PVC channel number allows reading ATM cells, the ATM cell sending module reads ATM cells from the ATM cell memory, and adds a space control word to the header of the ATM cells to form a cell frame and store the cell frame buffer, and sets a cell frame flag bit to wait for reading by the cell frame sending module; and simultaneously writing the updated PVC state back to the PVC state cache module, and continuously querying the next PVC channel.
10. A method for realizing flow control of an ATM network based on FPGA according to claim 5, 6, 7 or 8, characterized by further comprising a step of said cell frame transmitting module determining whether said cell frame buffer contains cell frame by inquiring cell frame flag bit of the flow control module before said step 53 and after step 52.
11. A method of FPGA-based ATM network flow control according to claim 5, 6, 7 or 8, characterized in that it further comprises a step of determining whether to allow said cell frame sending module to read cell frames from said cell frame buffer before said step 53 and after step 52.
12. A method for controlling flow of ATM network based on FPGA according to claim 5, 6, 7 or 8, wherein in step 53, the cell frame transmitting module obtains the current value of the counter by starting an interval counter, reads the header of the cell frame by inquiring the cell frame buffer to obtain an ATM cell interval parameter, and then realizes the ATM cell interval control by comparing the current value of the counter with the ATM cell interval parameter.
13. The method of claim 12 wherein the cell frame transmit module transmits ATM cells to the physical interface module if the ATM cell gap parameter value is less than the current value of the counter and the physical interface module allows ATM cells to be transmitted.
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| CNB2005101306034A CN100486224C (en) | 2005-12-14 | 2005-12-14 | Method and device for controlling ATM network flow based on FPGA |
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| CNB2005101306034A CN100486224C (en) | 2005-12-14 | 2005-12-14 | Method and device for controlling ATM network flow based on FPGA |
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| CN100486224C true CN100486224C (en) | 2009-05-06 |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN105812282A (en) * | 2016-05-12 | 2016-07-27 | 苏州联视泰电子信息技术有限公司 | ATM (Asynchronous Transfer Mode) branching and combining device based on FPGA |
Families Citing this family (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101188609B (en) * | 2007-12-05 | 2012-05-23 | 中兴通讯股份有限公司 | ATM and IP conversion device, system and method |
| CN101197774B (en) * | 2007-12-12 | 2012-01-04 | 上海华为技术有限公司 | Method and apparatus for controlling service flux |
| CN101414978B (en) * | 2008-11-19 | 2012-02-22 | 中兴通讯股份有限公司 | Method for processing cascade connection cell fragment |
| CN101599294B (en) * | 2009-05-11 | 2012-01-25 | 曙光信息产业(北京)有限公司 | Method for storing multiple virtual queues data based on FPGA |
| CN101977155B (en) * | 2010-11-18 | 2012-04-25 | 无锡源清高新技术研究所有限公司 | Virtual bandwidth self-adaptive control system and control method thereof |
| CN102164095B (en) * | 2011-05-31 | 2014-07-02 | 西安空间无线电技术研究所 | Datagram segmentation and reassembly system and realization method for onboard switching module |
| CN103391329B (en) * | 2013-07-12 | 2017-06-20 | 青岛海信宽带多媒体技术有限公司 | A kind of interface module and its method for supporting multiplex roles standard |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN105812282A (en) * | 2016-05-12 | 2016-07-27 | 苏州联视泰电子信息技术有限公司 | ATM (Asynchronous Transfer Mode) branching and combining device based on FPGA |
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