CN100485608C - Data stream prefetching method based on access instruction - Google Patents
Data stream prefetching method based on access instruction Download PDFInfo
- Publication number
- CN100485608C CN100485608C CNB2006101184455A CN200610118445A CN100485608C CN 100485608 C CN100485608 C CN 100485608C CN B2006101184455 A CNB2006101184455 A CN B2006101184455A CN 200610118445 A CN200610118445 A CN 200610118445A CN 100485608 C CN100485608 C CN 100485608C
- Authority
- CN
- China
- Prior art keywords
- instruction
- data stream
- data
- level data
- hit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Landscapes
- Memory System Of A Hierarchy Structure (AREA)
- Advance Control (AREA)
Abstract
The invention discloses a data flow pre-fetched method which is based on memory reference instruction, comprising a first-level data high speed buffering storage unit and a main memory, and a data flow pre-fetched instruction which is based on RISC processor instruction visiting and storing, wherein the data in the first-level data high speed buffering storage unit is a subset of the data in the main memory, the data flow pre-fetched instruction withdraws immediately whether to hit the first-level data high speed buffering storage unit, and does not enter into the data flow loading queue which stores reading-type memory reference instruction, and does not enter into the data flow storing queue which stores writing-type memory reference instruction, and occupies a non-hit address buffering unit when the data flow pre-fetched instruction does not hit the first-level data high speed buffering storage unit or the state of the high speed buffering storage unit does not agree with requirements, and the data flow pre-fetched instruction is used for continuing the memory reference operation. The invention can not only improve the hit rate of the first-level data high speed buffering storage unit of normal memory reference instruction, but also reduces the situation that the data flow pre-fetched instruction and the normal memory reference instruction struggle for the hardware resource, moreover, the design complex degree and the cost of the hardware are not increased evidently.
Description
Technical field
The present invention relates to a kind ofly fetch the method that improves microprocessor one-level data cache hit rate in advance, particularly relate to and a kind ofly instruct the method that data stream is looked ahead that realizes by the memory access class by data stream.
Background technology
The hit rate of one-level data caching is most important for the memory access performance of microprocessor, and data pre-fetching is the effective means that improves one-level data cache hit rate.Data pre-fetching can be realized by software control or hardware controls dual mode.Wherein, the data stream of software control is looked ahead, be by carrying out special access instruction---" data stream prefetched instruction " realized, it do not need the data stream of hardware controls look ahead the hardware control logic and relevant buffering that must increase, saved hardware spending, reduce design complexities, but also existed tangible deficiency.
The data stream prefetched instruction is divided into again reads to look ahead and writes prefetched instruction two classes.Wherein, reading prefetched instruction does not need the target data register, and writing prefetched instruction does not need source data register, and therefore, the data stream prefetched instruction lacks than the general-purpose register resource that other access instruction takies.But it still needs to take the instruction reorder buffer, and data stream all access instruction such as formation or data stream storage queue of packing into all need the hardware resource that uses.When not hitting one-level data caching or this memory lines state and do not meet the demands, holding time can reach tens even a hundreds of clock period, and the concrete time is depended on factors such as system frequency and scale.Because these resources also are that other access instruction is necessary, so event data stream prefetched instruction improper use, even reached the effect of the one-level data cache hit rate that improves normal access instruction, also can be owing to too much taking the required hardware resource of access instruction, make these resources become the bottleneck that new obstruction access instruction is carried out, thereby influence processor memory access performance.
Compiler static scheduling instruction or programmer when writing assembly routine, unpredictable when going out prefetched instruction and carrying out, the operating position of related hardware resource, therefore be difficult to accomplish by increasing the data stream prefetched instruction, both improved the one-level data cache hit rate of normal access instruction, and can not fight for hardware resource again with normal access instruction.
Summary of the invention
The technical problem to be solved in the present invention provides a kind of data stream forecasting method based on access instruction, can improve the one-level data cache hit rate of normal access instruction, can reduce data stream prefetched instruction and normal access instruction again and fight for the situation of hardware resource, and, needn't obviously increase hardware design complexity and hardware cost.
For solving the problems of the technologies described above, data stream forecasting method based on access instruction of the present invention is to adopt following technical scheme to realize: comprise one-level data caching and main memory, and the data stream prefetched instruction of a class risc-based processor access instruction, the data in the one-level data caching are subclass of data in the main memory; During data in the described data stream prefetched instruction visit main memory, at first to inquire about the one-level data caching, when hitting the one-level data caching, finish accessing operation; When not hitting one-level data caching or this memory lines state and not meeting the demands, accessing operation will be proceeded, this operation just with the data load in the designated memory address location in described storer, perhaps in loading data, obtain modification authority, and the visible system image of software is not had any impact data in this storage address unit; Described data stream prefetched instruction, in the entire process process, do not produce the fault of accurate breakpoint or unusual, wherein: described data stream prefetched instruction, no matter whether hit the one-level data caching, all withdraw from immediately, and do not enter and deposit the formation of packing into of the data stream of reading the class access instruction, do not enter yet and deposit the data stream storage queue of writing the class access instruction; Only when not hitting one-level data caching or cache line state and do not meet the demands, take a not hit address buffer cell, be used to proceed accessing operation.
The characteristics that the present invention utilizes the data stream prefetched instruction the visible system image of software not to be had any impact, after having judged whether such instruction hits the one-level data caching, allow it to withdraw from advance, so that release order the resource of reorder buffer as early as possible, and need not wait for that the actual memory access process of such instruction finishes.Described data stream prefetched instruction produces the fault of accurate breakpoint or when unusual, adopt and abandon accessing operation, but do not produce the request mode that reports an error, the fault of any accurate breakpoint that the data streams prefetched instruction produces or unusual in the entire process process.So make that reading prefetched instruction needn't use the data stream formation information of holding instruction of packing into; Write prefetched instruction and needn't use the data stream storage queue information of holding instruction.Avoided data stream prefetched instruction and normal access instruction to fight for two hardware resources the most in short supply in the memory access process.
The mode of accessing operation is abandoned in employing, handle and not hit the data stream prefetched instruction that one-level data caching or this memory lines state do not meet the demands, application is less than the situation of hit address buffer entries not, further improved above-mentioned prefetch process method, avoided because hit address buffer entries deficiency not, and cause the data stream prefetch request self-trapping, hinder the situation that other instruction is carried out.
Accessing operation is abandoned in employing, but does not empty the mode of streamline, and it is any self-trapping that the data streams prefetched instruction produces, and further improved above-mentioned prefetch process method.Make that in any case therefore the request that the data stream prefetch request can not produce instruction fetch again and carry out, needn't use the instruction reorder buffer information of holding instruction.When further advanceing to post-set time of data stream prefetch request instruction and enter the emission formation, and avoided such instruction and other instruction to fight for the situation of instruction reorder buffer.
In a word, the present invention is by suitably abandoning the mode of accessing operation, and in the data streams prefetched instruction implementation, some need take the small probability event of microprocessor internal buffer resource for a long time.So both guaranteed that most data stream prefetched instructions can normally carry out, improved the hit rate of one-level data caching effectively, avoided the data stream prefetched instruction to instruction reorder buffer, data stream the taking of important hardware resources such as formation or data stream storage queue of packing into again; Avoided because hit address buffer entries deficiency not, and caused the data stream prefetch request self-trapping, hindered the situation that other instruction is carried out.Simultaneously, suitably abandon accessing operation and be easy to realize, and only need the little hardware expense.On the microprocessor of one 2 decoding 3 emission, single memory access streamline, use this method, can make the test performance of data stream memory access performance test topic Stream improve 78.6%, and the area of memory access parts does not almost increase.
Description of drawings
The present invention is further detailed explanation below in conjunction with accompanying drawing and embodiment:
Fig. 1 is the treatment scheme of existing access instruction;
Fig. 2 is the treatment scheme of one embodiment of the invention data stream prefetched instruction;
Fig. 3 is the further treatment scheme of another embodiment data stream prefetched instruction of optimization of the present invention.
Embodiment
The present invention is a kind of data stream forecasting method based on access instruction, adopts special access instruction---data stream prefetched instruction, finishes looking ahead of one-level data caching.The data stream prefetched instruction was handled with access instruction is the same normally in emission, address computation and actual situation address substitution stage, if the fault that accurate breakpoint just takes place in this course is with unusual, then the data stream prefetched instruction will unconditionally be abandoned accessing operation, withdraw from immediately, and reporting errors not.Do not break down or unusual data stream prefetched instruction will be inquired about the one-level data caching, if hit and the capable state of one-level data caching meets the demands, end process then, otherwise, be used to initiate the memory access request to clauses and subclauses of hit address buffering application not.If successfully apply for clauses and subclauses, then send the memory access request to l2 cache memory or main memory, once to retransmit self-trappingly otherwise produce, this data stream prefetched instruction that cancels is laid equal stress on and is newly launched and carry out this instruction; If find the hit address buffering free cells is not arranged, then continue accessing operation, otherwise, produce again and once retransmit self-trappingly, and repeat said process, till obtaining idle not hit address buffer cell.But no matter whether the data stream prefetched instruction hits the one-level data caching, and only otherwise produce and retransmit self-trappingly, such instruction all will be withdrawed from immediately, not need to wait for the end of memory access process.In the memory access process,, then finish the memory access process immediately, but do not report an error if the fault of any accurate breakpoint or unusual takes place.If the fault of non-accurate breakpoint takes place, still to report an error.
Because the data stream prefetched instruction does not need to load general-purpose register, do not need the data in the general-purpose register are write the one-level data caching yet, and can not produce the fault of any accurate breakpoint or the request that reports an error unusually, therefore the relevant information that need not hold instruction in data stream is packed formation and data stream storage queue into is to finish aforesaid operations.So the data stream prefetched instruction does not need to enter data stream pack into formation or data stream storage queue as other memory access request after finishing address substitution.
As improvement to said method, can enter emission at the data stream prefetched instruction and withdraw from advance during formation, and instruction only is transmitted into the address computation parts, and not entry instruction reorder buffer.Not for the data stream prefetched instruction distributes age number, the content of its instruction age field and the age of its last instruction are number identical.When the fault of any accurate breakpoint takes place, when unusual or self-trapping, will unconditionally abandon accessing operation in instruction, and reporting errors not, do not carry out the command retransmission operation yet.
The following stated embodiment understands the present invention in detail.
Embodiment one
As shown in Figure 2, when data stream prefetched instruction A entered emission formation 101, entry instruction reorder buffer 108 waited for that instruction withdraws from.After instruction A is launched, after the processing through address computation parts 102 and address substitution parts 103, generate the required physical address of memory access.If the fault of accurate breakpoint and unusual takes place in this process, then the data stream prefetched instruction will unconditionally be abandoned accessing operation, and notification instruction reorder buffer 108 these instructions immediately can be withdrawed from, but reporting errors not.
Utilize this physical address, by the data in the inquiry parts 104 inquiry one-level data cachings 109, if hit the requirement that one-level data caching 109 and this memory lines state meet the data stream prefetch request, then finish prefetch operation, 108 these instructions of notification instruction reorder buffer can be withdrawed from.Otherwise, to clauses and subclauses of the buffering of hit address not 107 applications,, then notify reorder buffer 108 these instructions to withdraw from if apply for successfully, and to secondary data cache memory or main memory transmission memory access request.Otherwise 108 generations of notice reorder buffer are once retransmitted self-trapping, re-execute this instruction.
Embodiment two
As shown in Figure 3, data stream prefetched instruction A enters emission formation the time, withdraw from immediately, not entry instruction reorder buffer 108, for age of this command assignment number identical with last instruction.After instruction A is launched,, generate the required physical address of memory access through address computation parts 102 and address substitution parts 103.If the fault of accurate breakpoint and unusual takes place in this process, then the data stream prefetched instruction will unconditionally be abandoned accessing operation, but reporting errors not.
Utilize this physical address,,, then finish prefetch operation if hit the requirement that one-level data caching 109 and this memory lines state meet the data stream prefetch request by inquiry parts 104 inquiry one-level data cachings 109.Otherwise, to clauses and subclauses of the buffering of hit address not 107 applications, if apply for successfully, then to secondary data cache memory or main memory transmission memory access request.Otherwise, finish prefetch operation.
In the treatment scheme of existing access instruction shown in Figure 1, when data stream prefetched instruction A entered emission formation 101, entry instruction reorder buffer 108 waited for that instruction withdraws from.After instruction A is launched,, generate the required physical address of memory access through address computation parts 102 and address substitution parts 103.Information data-in stream pack into the formation 105 or the data stream storage queue 106 of instruction.
In the present invention, the fault of event data stream prefetched instruction generation accurate breakpoint and unusual, then the data stream prefetched instruction will unconditionally be abandoned accessing operation, and notification instruction reorder buffer 101 these instructions immediately can be withdrawed from, but reporting errors not.
Utilize this physical address, by inquiry parts 104 inquiry one-level data cachings 109, if hit the requirement that one-level data caching 109 and this memory lines state meet the data stream prefetch request, then finish prefetch operation, 108 these instructions of notification instruction reorder buffer can be withdrawed from.Otherwise to clauses and subclauses of the buffering of hit address not 107 applications, if apply for successfully, then 108 these instructions of notification instruction reorder buffer can be withdrawed from, and to secondary data cache memory or main memory transmission memory access request.Otherwise 108 generations of notification instruction reorder buffer are once retransmitted self-trapping, re-execute this instruction.
Compare with the treatment scheme of existing access instruction, the present invention can reduce data stream prefetched instruction taking the microprocessor internal buffering, wherein, embodiment one has avoided the data stream prefetched instruction to data stream the taking of formation 105 and data stream storage queue 106 of packing into, has reduced the holding time to instruction reorder buffer 108.Embodiment two, avoided the data stream prefetched instruction to instruction reorder buffer 108, data stream the taking of formation 105 and data stream storage queue 106 of packing into, avoided since not hit address cushion 107 clauses and subclauses deficiencies, and cause the data stream prefetch request self-trapping, hinder the situation that other instruction is carried out.
During data streams prefetched instruction of the present invention, broken of the restriction of " Feng. Nuo Yiman " structure partially to " instruction sequences withdraws from ", and adopt the small probability event that takes place in the special measure data streams prefetched instruction implementation, thereby reduced such instruction to the taking of microprocessor internal buffer queue, also reduced the data stream mode of looking ahead and aligned frequentation and deposit the influence that instruction is carried out.
Claims (3)
1, a kind of data stream forecasting method based on access instruction, comprise one-level data caching (109) and main memory, and the data stream prefetched instruction of a class risc-based processor access instruction, the data in the one-level data caching (109) are subclass of data in the main memory; During data in the described data stream prefetched instruction visit main memory, at first to inquire about one-level data caching (109), when hitting one-level data caching (109), finish accessing operation; When one-level data caching (109) or this storer (109) state of going that do not hit does not meet the demands, accessing operation will be proceeded, this operation just will specify the data load in the core address unit to arrive in the described one-level data caching (109), perhaps in loading data, obtain modification authority, and the visible system image of software is not had any impact data in this one-level data caching (109) address location; Described data stream prefetched instruction, in the entire process process, do not produce the fault of accurate breakpoint or unusual, it is characterized in that: described data stream prefetched instruction, no matter whether hit one-level data caching (109), all withdraw from immediately, and do not enter and deposit the formation (105) of packing into of the data stream of reading the class access instruction, do not enter yet and deposit the data stream storage queue (106) of writing the class access instruction; Only when one-level data caching (109) or one-level data caching (109) state of going that do not hit does not meet the demands, take not hit address buffering (a 107) unit, be used to proceed accessing operation.
2, the data stream forecasting method based on access instruction as claimed in claim 1, it is characterized in that: in the described data stream prefetched instruction implementation, occur any need be by self-trapping situation about handling the time, described data stream prefetched instruction is end process immediately, abandon accessing operation, described data stream prefetched instruction is during entry instruction emission formation (101), can withdraw from not entry instruction reorder buffer (108) immediately.
3, the data stream forecasting method based on access instruction as claimed in claim 2 is characterized in that: if hit address buffering (107) does not have free cells, described data stream prefetched instruction is end process immediately, abandons accessing operation.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2006101184455A CN100485608C (en) | 2006-11-17 | 2006-11-17 | Data stream prefetching method based on access instruction |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2006101184455A CN100485608C (en) | 2006-11-17 | 2006-11-17 | Data stream prefetching method based on access instruction |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN101187859A CN101187859A (en) | 2008-05-28 |
| CN100485608C true CN100485608C (en) | 2009-05-06 |
Family
ID=39480275
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB2006101184455A Active CN100485608C (en) | 2006-11-17 | 2006-11-17 | Data stream prefetching method based on access instruction |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN100485608C (en) |
Families Citing this family (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8533437B2 (en) * | 2009-06-01 | 2013-09-10 | Via Technologies, Inc. | Guaranteed prefetch instruction |
| CN103729314B (en) * | 2012-10-11 | 2016-09-07 | 珠海扬智电子科技有限公司 | The management method of memory access instruction and management system |
| US20160371089A1 (en) * | 2014-03-27 | 2016-12-22 | Intel Corporation | Instruction and logic for filtering of software prefetching instructions |
| CN104391680B (en) * | 2014-11-25 | 2017-04-19 | 上海高性能集成电路设计中心 | Method for realizing streamline retiring of store instruction in superscalar microprocessor |
| CN114265812B (en) * | 2021-11-29 | 2024-02-02 | 山东云海国创云计算装备产业创新中心有限公司 | Method, device, equipment and medium for reducing access delay of RISC-V vector processor |
-
2006
- 2006-11-17 CN CNB2006101184455A patent/CN100485608C/en active Active
Also Published As
| Publication number | Publication date |
|---|---|
| CN101187859A (en) | 2008-05-28 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US8069336B2 (en) | Transitioning from instruction cache to trace cache on label boundaries | |
| US5983325A (en) | Dataless touch to open a memory page | |
| CN103699362B (en) | Microprocessor and the method for execution thereof | |
| CN100487642C (en) | D-cache miss prediction and scheduling method and device | |
| US20220156149A1 (en) | Pipelined read-modify-write operations in cache memory | |
| US7962730B2 (en) | Replaying memory operation assigned a load/store buffer entry occupied by store operation processed beyond exception reporting stage and retired from scheduler | |
| JP5084280B2 (en) | Self-prefetch L2 cache mechanism for data lines | |
| TWI383320B (en) | Processor with dependence mechanism to predict whether a load is dependent on older store and related method and computer system | |
| EP0097790B1 (en) | Apparatus for controlling storage access in a multilevel storage system | |
| CN100407134C (en) | System and method for handling exceptional instructions in a trace cache based processor | |
| US6088789A (en) | Prefetch instruction specifying destination functional unit and read/write access mode | |
| US20040128448A1 (en) | Apparatus for memory communication during runahead execution | |
| US8458282B2 (en) | Extended write combining using a write continuation hint flag | |
| US6775749B1 (en) | System and method for performing a speculative cache fill | |
| US9092346B2 (en) | Speculative cache modification | |
| KR101541001B1 (en) | Processor with a coprocessor having early access to not-yet issued instructions | |
| JP2009540411A (en) | Fast and inexpensive store-load contention scheduling and transfer mechanism | |
| TW201017531A (en) | Apparatus and methods for speculative interrupt vector prefetching | |
| JP5444889B2 (en) | Arithmetic processing device and control method of arithmetic processing device | |
| CN100485608C (en) | Data stream prefetching method based on access instruction | |
| CN102662634A (en) | Memory access and execution device for non-blocking transmission and execution | |
| KR101093784B1 (en) | Load store unit with replay mechanism | |
| US11321097B2 (en) | Super-thread processor | |
| US9405545B2 (en) | Method and apparatus for cutting senior store latency using store prefetching | |
| US10261909B2 (en) | Speculative cache modification |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant |