CN100468960C - Class-D amplifier - Google Patents

Abstract

A class-D amplifier includes: an operational amplifier and capacitors, which constitute an integrator for integrating a difference between a plus-sided input signal and a minus-sided input signal which constitute analog input signals; delay circuits for delaying a phase of a triangular wave by a desirable very small angle; resistors, which constitute a synthesizing circuit for synthesizing an output of the integrator, the triangular wave, and outputs of the delay circuits with each other; comparators for comparing outputs of the synthesizing circuit with each other; AND circuits which constitute a buffer for inputting outputs of the comparators; and resistors feeding back an output of the buffer to an input side of the integrator.

Description

Class D amplifier

Technical Field

The invention relates to a class D amplifier.

Background

The class D amplifier performs power amplification by a Pulse Width Modulation (PWM) input signal and is used to perform power amplification of an audio signal. A conventional class-D amplifier is arranged with an integrator to integrate an analog input signal, a comparator to compare an output signal of the integrator with a predetermined triangular waveform, and a buffer (pulse amplifier) to amplify the output signal of the comparator to output a pulse signal. In such a conventional class-D amplifier, a pulse signal output from the buffer is fed back to an input terminal of the integrator. The output signal of the buffer is then filtered by a low pass filter consisting of an inductor and a capacitor to obtain an analog signal that drives a load such as a loudspeaker.

A conventional pulse width modulation amplifier is arranged with a comparator to compare an analog input signal with a triangular waveform, an amplifier to amplify an output of the comparator, and a transformer arranged between the amplifier and a load (see, for example, japanese patent laid-open No. 56-27001).

Further, conventional digital amplifying circuits using a digital signal processing circuit are each equipped with a noise shaper, a converter, a logic circuit, a switch, and a filter (for example, refer to japanese patent laid-open No. 2000-500625). The noise shaper frequency shapes the quantization noise of the digital input signal. The converter converts a PCM (pulse code modulation) signal, which is responsive to the output of the noise shaper, into a PWM (pulse width modulation) signal. The logic circuit compensates for the linearity of the output signal of the converter. The switch is controlled by the output of the logic circuit. The input of the filter is connected to the power supply through a switch.

However, in the conventional class-D amplifier described above, the buffer is constituted by two buffers called a positive-side buffer and a negative-side buffer, respectively. The two buffers output signals having opposite polarities with an energy ratio of 50% even when there is no input signal. As a result, in the conventional class D amplifier, current may flow through the low pass filter even in the absence of an input signal, which results in a large amount of waste.

In japanese patent laid-open No. 56-27001, a technical idea of turning off an output amplifying element during a period of no input signal in order to avoid waste of power when no input signal is present is described. However, the conventional pulse width modulation amplifier in the above-described patent publication 1 has such a problem that: it requires a transformer to transform the impedance and cut off the DC voltage, which may require a large-sized device and also increases the cost. Further, there is another problem in the pulse width modulation amplifier described in japanese patent publication No. 56-27001: since the comparator compares the input signal with a simple triangular waveform, distortion of the output signal is severe.

On the other hand, the digital amplifying circuit described in japanese patent laid-open No. 2000-500625 uses three or four values of output states (switching states) and amplifies the digital input signal when the digital circuit is provided as a logic circuit in order to improve linearity. As a result, the digital amplification circuit described in japanese patent laid-open No. 2000-500625 has such a problem: since the digital amplification circuit cannot be arranged to provide an analog circuit, the analog input signal cannot be amplified while maintaining better linearity. In other words, in such a conventional digital amplifying circuit, when a small signal pulse is input, since a compensation pulse is added to the small signal pulse, output switching distortion in a logic circuit is compensated. However, a circuit for compensating for output switching distortion is constructed by merely providing such a digital circuit as a logic circuit, and thus such a conventional amplifying circuit cannot amplify an analog input signal with better linearity.

Disclosure of Invention

The present invention is designed to solve the above-described problems, and therefore, provides a class D amplifier capable of operating with low distortion and small power consumption.

Also, the present invention provides a class D amplifier that can operate with low distortion and low power consumption without a transformer.

Also, the present invention provides a class D amplifier capable of outputting a DC voltage component of the DC voltage to substantially zero volts.

In order to solve the above-described problems, the class D amplifier of the present invention has the following structure.

(1) A class D amplifier comprising:

the integrator is used for integrating the analog input signal;

a first comparator for comparing the output of the integrator with the first triangular waveform;

a second comparator for comparing the output of the integrator with a second triangular waveform which is a waveform obtained by changing the phase of the first triangular waveform positively by 180 degrees or negatively by a very small angle;

a buffer for outputting a positive side output signal and a negative side output signal based on an output of the first comparator and an output of the second comparator; and

the feedback circuit is used to feed back the difference between the positive-side output signal and the negative-side output signal to the input terminal of the integrator.

(2) The class-D amplifier according to (1), wherein the buffer comprises:

a first buffer for calculating a logical product of an output of the first comparator and an output of the second comparator to output a calculated result as an output signal of a negative side; and

the second buffer is used for calculating the logical product of the output of the first comparator and the output of the second comparator to output a calculated result as an output signal of the positive side.

(3) The class-D amplifier according to (1), wherein the feedback circuit includes a differential amplifier for amplifying a difference between the positive side output signal and the negative side output signal.

(4) A class D amplifier comprising:

an integrator for integrating a difference between a positive-side input signal and a negative-side input signal constituting the analog input signal;

a delay circuit for delaying the phase of the triangular waveform by a predetermined very small angle;

a synthesizing circuit for synthesizing an output of the integrator, the triangular waveform, and an output of the delay circuit with each other to output a plurality of output signals;

the comparator is used for comparing a plurality of output signals of the synthesizing circuit with each other;

the buffer is used for inputting the output of the comparator; and

the feedback circuit is used for feeding back the output of the buffer to the input end of the integrator.

(5) The class-D amplifier according to (4), wherein,

the triangular waveform is composed of a first triangular waveform and a second triangular waveform corresponding to a waveform generated by changing the phase of the first triangular waveform by 180 degrees,

the delay circuit includes a first delay circuit for delaying the phase of the first triangular waveform by the predetermined very small angle, and a second delay circuit for delaying the phase of the second triangular waveform by the predetermined very small angle,

the synthesizing circuit synthesizes a negative side output of the integrator with the first triangular waveform to generate a first synthesized waveform, synthesizes a positive side output of the integrator with the second triangular waveform to generate a second synthesized waveform, synthesizes a negative side output of the integrator with an output of the second delay circuit to generate a third synthesized waveform, synthesizes a positive side output of the integrator with an output of the first delay circuit to generate a fourth synthesized waveform,

the comparator includes a first comparator to compare the first synthesized waveform with the second synthesized waveform, and a second comparator to compare the third synthesized waveform with the fourth synthesized waveform,

the buffer includes a first buffer for calculating a logical product of an output of the first comparator and an output of the second comparator, and a second buffer for calculating a logical product of an output of the first comparator and an output of the second comparator, and

the feedback circuit includes a first feedback circuit for feeding back an output of the first buffer to a positive side input of the integrator, and a second feedback circuit for feeding back an output of the first buffer to a negative side input of the integrator.

(6) A class D amplifier comprising:

an integrator for integrating a difference between a positive-side input signal and a negative-side input signal constituting the analog input signal;

a synthesizing circuit for synthesizing an output of the integrator with a triangular waveform, and synthesizing the output of the integrator with a triangular waveform having an inverted phase from the aforementioned triangular waveform so as to output a plurality of signals, wherein the inverted phase triangular waveform corresponds to a waveform changed by 180 degrees in phase in accordance with the aforementioned triangular waveform;

the comparator is used for comparing the output signals of the synthesis circuits with each other;

the buffer is used for inputting the output of the comparator; and

a feedback circuit is used to feed back the output of the buffer to the input of the integrator,

wherein the combining circuit includes a plurality of resistors having at least two resistance values and is arranged to generate a phase difference between a plurality of signals corresponding to an output of the combining circuit based on the resistance values of the plurality of resistors and an input capacitance of the comparator.

(7) The class-D amplifier according to (6), wherein,

the synthesis circuit includes: a first synthesizing section for synthesizing a negative side output of the integrator with the triangular waveform to generate a first synthesized waveform; a second synthesizing section for synthesizing the positive side output of the integrator with the inverted phase triangular waveform to generate a second synthesized waveform; a third synthesis section for synthesizing a negative side output of the integrator with the inverted-phase triangular waveform to generate a third synthesized waveform; and a fourth synthesizing section for synthesizing the positive side output of the integrator with the triangular waveform to produce a fourth synthesized waveform;

the first combining portion includes a first resistor and a second resistor, one terminal of the first resistor being connected to the negative side output of the integrator, the triangular waveform being supplied to one terminal of the second resistor; the other terminal of the first resistor is connected to the other terminal of the second resistor to form an output terminal thereat;

the second combining section includes a third resistor and a fourth resistor, one terminal of the third resistor being connected to the positive side output of the integrator, the triangular waveform being supplied to one terminal of the fourth resistor; the other terminal of the third resistor is connected to the other terminal of the fourth resistor to form an output terminal thereat;

the third synthesis section includes a fifth resistor and a sixth resistor, one terminal of the fifth resistor is connected to the negative side output of the integrator, and the triangular waveform of the inverted phase is supplied to one terminal of the sixth resistor; the other terminal of the fifth resistor is connected to the other terminal of the sixth resistor to form an output terminal thereat;

the fourth combining portion includes a seventh resistor and an eighth resistor, one terminal of the seventh resistor is connected to the positive side output of the integrator, and the triangular waveform is supplied to one terminal of the eighth resistor; the other terminal of the seventh resistor is connected to the other terminal of the eighth resistor to form an output terminal thereat;

the comparator includes a first comparator having one input terminal connected to the output terminal of the first combining section and the other input terminal connected to the output terminal of the second combining section, and a second comparator having one input terminal connected to the output terminal of the third combining section and the other input terminal connected to the output terminal of the fourth combining section;

the buffer includes a first buffer for calculating a logical product of an output of the first comparator and an output of the second comparator, and a second buffer for calculating a logical product of an output of the first comparator and an output of the second comparator;

the feedback circuit includes a first feedback circuit for feeding back an output of the first buffer to a positive side input of the integrator, and a second feedback circuit for feeding back an output of the second buffer to a negative side input of the integrator; and is

The resistance value of any one of the first resistor, the second resistor, the third resistor and the fourth resistor is different from the resistance value of any one of the fifth resistor, the sixth resistor, the seventh resistor and the eighth resistor.

(8) The class-D amplifier according to (7), wherein a resistance value of each of the first resistor, the second resistor, the third resistor, and the fourth resistor is obtained by multiplying a value other than 1 by a resistance value according to each of the fifth resistor, the sixth resistor, the seventh resistor, and the eighth resistor.

(9) A class D amplifier comprising:

the integrator is used for integrating a positive side input signal and a negative side input signal which form an analog input signal;

the triangular waveform generating circuit comprises a current source and a capacitor;

a comparator for comparing the output of the integrator with the output of the triangular waveform generating circuit;

the buffer is used for inputting the output of the comparator; and

a feedback circuit is used to feed back the output of the buffer to the input of the integrator.

(10) The class-D amplifier according to (9), wherein,

one end of the capacitor is connected to one of the input terminals of the comparator, an

The current source switches the direction of the output current so as to repeatedly charge and discharge the capacitor.

(11) The class-D amplifier according to (10), wherein,

one terminal of the current source is connected to one terminal of the capacitor,

the current source flows a current in a direction in which the capacitor is charged when the potential of the capacitor is lower than a first potential and flows a current in a direction in which the capacitor is discharged when the potential of the capacitor is higher than a second potential, and

the second potential is higher than the first potential.

(12) The class-D amplifier according to (9), wherein,

the comparator includes a first comparator for comparing a negative side output of the integrator with an output of the triangular waveform generating circuit, and a second comparator for comparing a positive side output of the integrator with an output of the triangular waveform generating circuit,

the buffer includes a first buffer for calculating a logical product of an inverted value of an output of the first comparator and an output of the second comparator, and a second buffer for calculating a logical product of inverted values of the first comparator and the second comparator, and

the feedback circuit includes a first feedback circuit for feeding back an output of the first buffer to a negative side input of the integrator, and a second feedback circuit for feeding back an output of the second buffer to a positive side input of the integrator.

According to the present invention, the class D amplifier can be provided to operate with low distortion and small power consumption.

At the same time, the invention also provides a class D amplifier operating with low distortion and low power consumption without the need for a transformer, while the DC voltage component in the output can be reduced to substantially zero volts.

Drawings

Fig. 1 is a circuit diagram showing a configuration example of a class D amplifier according to embodiment mode 1 of the present invention.

Fig. 2 shows waveforms for the operation of a class D amplifier as shown in fig. 1, in case zero voltage is supplied to the class D amplifier.

Fig. 3 is a waveform diagram showing the operation of the class D amplifier in the case where a positive voltage is supplied to the class D amplifier shown in fig. 1.

Fig. 4 is a waveform diagram illustrating the operation of the class D amplifier in the case where a negative voltage is applied to the class D amplifier shown in fig. 1.

Fig. 5 is a circuit diagram showing a configuration example of a class D amplifier according to embodiment mode 2 of the present invention.

Fig. 6 shows waveforms for the operation of a class D amplifier as shown in fig. 5 with zero voltage supplied to the class D amplifier.

Fig. 7A to 7C are graphs showing waveforms appearing in a load when a sine wave is input to the class D amplifier according to embodiment 1 or embodiment 2 of the present invention.

Fig. 8 is a circuit diagram showing a configuration example of a class-D amplifier according to embodiment mode 3 of the present invention.

Fig. 9 shows waveforms for the operation of the class D amplifier as shown in fig. 8 with zero voltage supplied to the class D amplifier.

Fig. 10 is a waveform diagram showing the operation of the class D amplifier in the case where a positive voltage is supplied to the class D amplifier shown in fig. 8.

Fig. 11 is a waveform diagram showing the operation of the class D amplifier in the case where a negative voltage is supplied to the class D amplifier shown in fig. 8.

Fig. 12 is a circuit diagram showing a configuration example of a class D amplifier according to embodiment mode 4 of the present invention.

Fig. 13 is a circuit diagram showing an example of the configuration of a current source of a class D amplifier.

The waveform diagram of fig. 14 shows the operation of the current source.

The waveform diagram of fig. 15 shows the operation in the case of a positive value supplied to the class D amplifier.

The waveform diagram of fig. 16 shows the operation with the voltage supplied to the class D amplifier 0.

The waveform diagram of fig. 17 shows operation with negative values supplied to the class D amplifier.

Detailed Description

Various embodiment modes of the present invention will now be described with reference to the accompanying drawings.

Example 1

Fig. 1 is a circuit diagram showing a configuration example of a class D amplifier according to embodiment mode 1 of the present invention.

The class-D amplifier is arranged with resistors R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, AND R12, capacitors C1 AND C2, an operational amplifier 11, comparators 12 AND 13, delay circuits 21 AND 22, an AND (AND) circuit 31 (low activity), AND another AND circuit 32. As shown, predetermined triangular waveform signals "a" and "b" are supplied to one terminal of the resistors R9 and R10, respectively. The triangular waveform signal "a" and the triangular waveform signal "b" are signals having the same waveform, but are out of phase by 180 degrees from each other.

One terminal of each of resistors R1 and R2 constitutes a differential input for the analog input signal. And, one terminal of the resistor R1 constitutes a positive side input terminal (+ IN), and one terminal of the resistor R2 constitutes a negative side input terminal (-IN). The operational amplifier 11 and the capacitors C1 and C2 constitute an integrator. The analog input signal inputted differentially through the resistors R1 and R2 is integrated by the integrator, while the integrated signal is outputted to the resistors R5, R6, R7, and R8.

The resistors R5, R6, R7, R8, R9, R10, R11, and R12 constitute a synthesizing circuit that synthesizes the triangular waveform signal "a" or "b" with the output signal of the integrator. The triangular waveform signals "a" and "b" are generated by delaying the triangular waveform signal "a" and the triangular waveform signal "b" by a very small angle "θ" (i.e., θ < <180 degrees). The synthesizing circuit generates first to fourth four kinds of synthesized waveforms "e", "f", "g", "h".

The first synthesized waveform "e" is generated by synthesizing the negative-side output signal of the operational amplifier 11 constituting the integrator with the triangular waveform signal "a" (first triangular waveform). The second synthesized waveform "f" is generated by synthesizing the positive side output signal of the operational amplifier 11 constituting the integrator with the triangular waveform signal "b" (second triangular waveform). The third synthesized waveform "g" is generated by synthesizing the negative side output signal of the operational amplifier 11 constituting the integrator with the triangular waveform signal "b". The fourth synthesized waveform "h" is generated by synthesizing the positive side output signal of the operational amplifier 11 constituting the integrator with the triangular waveform signal "a'" generated by delaying the triangular waveform signal "a".

The comparator 12 (first comparator) compares the first synthesized waveform "e" with the second synthesized waveform "f" to output a comparison result. When the first synthesized waveform "e" is larger than the second synthesized waveform "f", the first comparator 12 outputs a signal of a predetermined "low" potential (for example, zero potential), and when the first synthesized waveform "e" is smaller than the second synthesized waveform "f", the first comparator 12 outputs a signal of a predetermined "high" potential. The comparator 13 (second comparator) compares the third synthesized waveform "g" with the fourth synthesized waveform "h" to output a comparison result. When the third synthesized waveform "g" is larger than the fourth synthesized waveform "h", the second comparator 13 outputs a signal of a predetermined "low" potential (for example, zero potential), and when the third synthesized waveform "g" is smaller than the fourth synthesized waveform "h", the second comparator 13 outputs a signal of a predetermined "high" potential. Both comparators 12 and 13 may be selectively implemented by using operational amplifiers.

AND circuit 31 is responsive to a buffer circuit having an AND gate function with a negative logic input. The AND circuit 31 performs an AND calculation (low activity) in which the AND circuit 31 outputs a "high" potential signal when both the output of the first comparator 12 AND the output of the second comparator 13 are "low", AND outputs the result of this calculation as the negative side output "-OUT" of the class-D amplifier. Resistor R3 constitutes a first feedback circuit. This first feedback circuit feeds back the output of the AND circuit 31 functioning as a buffer to the positive side input of the operational amplifier 11.

The AND circuit 32 is responsive to a buffer circuit having an AND calculation function, AND performs an AND calculation operation between the output of the comparator 12 AND the output of the comparator 13, AND then outputs the calculation result as the positive side output "+ OUT" of the class-D amplifier. Resistor R4 forms a second feedback circuit. This second feedback circuit feeds back the output of the AND circuit 32 functioning as a buffer to the negative side input of the operational amplifier 11.

A load (e.g., a speaker or the like) is connected between the positive side output "+ OUT" and the negative side output "+ OUT" of the class D amplifier via a low pass filter. Due to the provision of these circuit arrangements, the class-D amplifier can amplify analog input signals "+ IN" and "-IN" with low distortion without providing a transformer, and can drive a load with reduced power consumption.

Next, the operation of the class D amplifier of embodiment 1 arranged according to the above description is described with reference to fig. 2 to 4. Fig. 2 to 4 show operations of respective circuit parts representing the class D amplifier shown in fig. 1. Fig. 2 shows waveforms of the various circuit parts of the class D amplifier when the value of the analog input signal "+ IN" is equal to the value of the analog input signal "-IN", i.e. when the differential input value is a zero voltage value (no input signal). Fig. 3 shows waveforms of respective circuit portions of the class-D amplifier when (analog input signal "+ IN") > (analog input signal "-IN"), that is, when the differential input is positive. Fig. 4 shows waveforms of the respective circuit parts of the class-D amplifier when (analog input signal "+ IN") < (analog input signal "-IN"), i.e., when the differential input is negative.

First, the operation for fig. 2, i.e. the case of no differential input (zero voltage value), will be explained. The phase of the triangular waveform signal "a" is different from the phase of the triangular waveform signal "b" by 180 degrees. The triangular waveform signal "a" constitutes a signal generated by delaying the triangular waveform signal "a" by a very small angle "θ". In this case, a predetermined noise called "jitter" is selectively applied to the triangular waveform signals a, a ', b, and b', respectively. Since the jitter noise is applied to each triangular waveform signal, distortion of the output waveform can be corrected. In addition to these triangular waveform signals a, a ', b, and b', a sawtooth waveform, an integral waveform, and the like may be selectively used.

The phase relationships between a, a' and the positive side output of the integrator (positive side output of the operational amplifier 11) "d" are substantially equal to each other. The phase relationships between b, b' and the negative side output (negative side output "c" of the operational amplifier 11) are also substantially equal to each other.

The inputs of the comparators 12 and 13, i.e., the first to fourth synthesized waveforms e, f, g, and h have waveforms synthesized with the integrator. The phase of the first synthesized waveform "e" is different from the phase of the second synthesized waveform "f" by about 180 degrees. The phase of the third composite waveform "g" differs from the phase of the fourth composite waveform "h" by about 180 degrees. The waveform of the first synthesized waveform "e" is substantially equal to the waveform of the fourth synthesized waveform "h", and the first and fourth synthesized waveforms "e" and "h" are different by a very small angle "θ". The waveform of the second synthesized waveform "f" is equal to the waveform of the third synthesized waveform "g", and the second and third synthesized waveforms "f" and "g" are different by a very small angle "θ".

The output "j" of the comparator 12 becomes "low" when (the first synthesized waveform "e") > (the second synthesized waveform "f"), and becomes "high" when (the first synthesized waveform "e") < (the second synthesized waveform "f"). The output "k" of the comparator 13 becomes "low" when (the third synthesized waveform "g") > (the fourth synthesized waveform "h"), and becomes "high" when (the third synthesized waveform "g") < (the fourth synthesized waveform "h"). The output (-OUT) of AND circuit 31 is "high" when the outputs "j" AND "k" of comparators 12 AND 13 are "low". The output (+ OUT) of the AND circuit 32 is "high" when the outputs "j" AND "k" of the comparators 12 AND 13 are "high".

In other words, "+ OUT" is output on the positive side in the class-D amplifier, and is high potential in a period defined from an intersection point (time constant "t 1") between the first synthesized waveform "e" and the second synthesized waveform "f" to another intersection point (time constant "t 2") between the third synthesized waveform "g" and the fourth synthesized waveform "h". The negative side output "-OUT" in this class-D amplifier is a high potential in a period defined from a cross point (time constant "t 3") between the first synthesized waveform "e" and the second synthesized waveform "f" to another cross point (time constant "t 4") between the third synthesized waveform "g" and the fourth synthesized waveform "h".

In this case, the period of time for which "+ OUT" is output on the positive side or "-OUT" is output on the negative side may depend on the phase difference (very small angle "θ") of the triangular waveform signals a, a 'and the triangular waveform signals b, b'. As a result, since the delay time in the delay circuits 21 and 22 is sufficiently short to a desired value in order to reduce the phase difference (very small angle "θ") of the triangular waveform signals a, a 'and the triangular waveform signals b, b', the period during which the positive side output "+ OUT" and the negative side output "-OUT" become high potential can be sufficiently short to a desired value. At this time, the voltages of the negative side output "c" and the positive side output "d" of the integrator become very low.

In other words, in the case where there is no input signal (i.e., the case where zero voltage is applied as described below), the period during which both the positive side output + OUT and the negative side output-OUT are high can be set to an energy ratio of 0 to several percent. The positive side output "+ OUT" and the negative side output "-OUT" are supplied to a load such as a speaker via, for example, a low-pass filter. As a result, in the case where there is no input signal, the period in which both the positive side output + OUT and the negative side output-OUT are high potential can be set to an energy ratio of 0 to several percent, and thus the current passing through the low-pass filter and the load becomes very small. As a result, in the case where the class D amplifier in the present embodiment is used for a small signal, the above-described low pass (LC filter or the like) arranged between the output terminal and the load can be eliminated.

The class D amplifier according to embodiment 1 provides the above-described arrangement, and in the case where there is no analog input signal (i.e., the case where a zero voltage value is input), since the period of time during which the output signal is at a high potential is sufficiently short as desired, power consumption can be greatly reduced as compared with the class D amplifier in the related art.

Next, the operation of (analog input signal "+ IN") > (analog input signal "-IN"), i.e., the class-D amplifier IN the case where the differential input is a positive value as shown IN fig. 3, will be described. It should be noted that the triangular waveform signals a, a ', b' are the same as in fig. 2. The phase relationship between the triangular waveform signals a, a ', b' and the outputs c, d of the integrators (i.e., the outputs of the operational amplifiers 11) is the same as that represented in fig. 2. In fig. 3, the first to fourth synthesized waveforms e, f, g, h have waveforms synthesized with the outputs of the integrators. The phase of the synthesized waveform "e" and the phase of the synthesized waveform "f" are different by about 180 degrees, and the phase of the synthesized waveform "g" and the phase of the synthesized waveform "h" are different by about 180 degrees.

In fig. 3, the difference between the negative side output "c" of the integrator and the positive side output "d" of the integrator is larger in the same time period than the case shown in fig. 2. The phase difference between the first synthesized waveform "e" and the fourth synthesized waveform "h" and the other phase difference between the second synthesized waveform "f" and the third synthesized waveform "g" are both larger than in the case shown in fig. 2. As a result, a time period defined from an intersection point (time constant t1 ') between the first synthesized waveform "e" and the second synthesized waveform "f" to another intersection point (time constant t 2') between the third waveform "g" and the fourth synthesized waveform "h" is longer than that in the case of fig. 2 (from time constant t1 to time constant t2), while a time period in which the positive-side output + OUT is high potential is longer than that in the case of fig. 2. In fig. 3, a time period defined from an intersection point (time constant t3 ') between the third synthesized waveform "g" and the fourth synthesized waveform "h" after the time constant t2 ' to another intersection point (time constant t4 ') between the first synthesized waveform "e" and the second synthesized waveform "f" is also longer than that in fig. 2, while the positive-side output "+ OUT" becomes high potential, and then, these operations may be repeated.

The output "j" of the comparator 12 becomes "high" from the intersection point (time constant t1 ') between the first synthesized waveform "e" and the second synthesized waveform "f" to another intersection point (time constant t 4') between the next first synthesized waveform "e" and the next second synthesized waveform "f". Next, the output "j" of the comparator 12 becomes "low" from the time constant t4 'to another intersection point (time constant t 5') between the next first synthesized waveform "e" and the second synthesized waveform "f", and subsequently, the above-described operation is repeatedly performed. In other words, the output "j" of the comparator 12 changes from "high" to "low" or from "low" to "high" at the intersection between the first synthesized waveform "e" and the second synthesized waveform "f".

The output "k" of the comparator 13 becomes "low" from the intersection point (time constant t2 ') between the third waveform "g" and the fourth synthesized waveform "h" to the intersection point (time constant t 3') between the next third synthesized waveform "g" and the next fourth synthesized waveform "h". Next, the output "k" of the comparator 13 becomes "high" from the time constant t3 'to another intersection point (time constant t 6') between the next third synthesized waveform "g" and the fourth synthesized waveform "h", and subsequently, the above-described operation is repeatedly performed. In other words, the output "k" of the comparator 13 changes from "high" to "low" or from "low" to "high" at the intersection between the third synthesized waveform "g" and the fourth synthesized waveform "h".

Next, since the positive side output "+ OUT" is (output j) AND (output "k"), this positive side output "+ OUT" becomes the "high" potential in the period from the time constant t1 'to the time constant t 2', in the period from the time constant t3 'to the time constant t 4', AND in the period from the time constant t5 'to the time constant t 6'. As a result, the energy ratio of the period in which the output "+ OUT" becomes a high potential on the positive side is substantially proportional to the amplitude of the pulse value (differential value) of the analog input signal. In other words, the positive-side output "+ OUT" may constitute a signal obtained by modulating the pulse value (differential value) of the analog input signal in a Pulse Width Modulation (PWM) manner.

On the other hand, the negative side output "-OUT" continuously becomes low potential. This is because there is no period during which the outputs "j" and "k" of the comparators 12 and 13 simultaneously become low when (analog input signal "+ IN") > (analog input signal "-IN") as shown IN fig. 3.

Next, the operation of the class D amplifier will be described (analog input signal "+ IN") < (analog input signal "-IN"), i.e., IN the case where the differential input is positive as shown IN fig. 4. It should be noted that the triangular waveform signals a, a ', b' are the same as in fig. 2. The phase relationship between the triangular waveform signals a, a ', b' and the outputs c, d of the integrators (i.e., the outputs of the operational amplifiers 11) is the same as that represented in fig. 2.

It will be appreciated that in the case shown in figure 4, the phases of the outputs "c" and "d" of the integrators are inverted (i.e. changed by 180 degrees) from the comparisons described above in figures 2 and 3. The temporal relationship regarding the intersection between the first synthesized waveform "e" and the second synthesized waveform "f" and the intersection between the third synthesized waveform "g" and the fourth synthesized waveform "h" is opposite to the case shown in fig. 3.

The output "j" of the comparator 12 becomes "high" from the intersection point (time constant t2 ") between the first synthesized waveform" e "and the second synthesized waveform" f "to another intersection point (time constant t 3") between the next first synthesized waveform "e" and the next second synthesized waveform "f". Next, the output "j" of the comparator 12 becomes "low" from the time constant t3 "to another intersection point (time constant t 6") between the next first synthesized waveform "e" and the second synthesized waveform "f", and subsequently, the above-described operation is repeatedly performed. In other words, the output "j" of the comparator 12 changes from "high" to "low" or from "low" to "high" at the intersection between the first synthesized waveform "e" and the second synthesized waveform "f".

The output "k" of the comparator 13 becomes "low" from the intersection between the third waveform "g" and the fourth synthesized waveform "h" (time constant t1 ") to the intersection between the next third synthesized waveform" g "and the next fourth synthesized waveform" h "(time constant t 4"). Next, the output "k" of the comparator 13 goes from the time constant t4 "to" high "from another intersection point (time constant t 5") between the next third synthesized waveform "g" and the fourth synthesized waveform "h", and then, the above-described operation is repeatedly performed. In other words, the output "k" of the comparator 13 changes from "high" to "low" or from "low" to "high" at the intersection between the third synthesized waveform "g" and the fourth synthesized waveform "h".

Next, since the positive side output "+ OUT" + is (output j) AND (output k), this positive side output "+ OUT" continuously becomes "low" potential. When (output j) AND (output k) is generally "low", the energy ratio of the period during which the negative side output "-OUT" becomes "high" while the negative side output "-OUT" becomes high is substantially directly proportional to the amplitude of the pulse value (differential value) of the analog input signal. In other words, the negative-side output "-OUT" may constitute a signal obtained by modulating the pulse values (differential values) of the analog input signal in a Pulse Width Modulation (PWM) manner.

As a result, according to the class D amplifier of embodiment 1, the analog input signal can be converted into a PWM signal having three values consisting of a zero voltage value, a positive value, and a negative value, and these converted PWM signals are output. According to the class-D amplifier of embodiment 1, in the case where the analog input signal becomes higher than or equal to the predetermined value, the output signal thereof becomes a transition waveform of a one-sided signal of only either one of the positive-side output "+ OUT" and the negative-side output "+ OUT", as represented in fig. 3 and 4. As a result, the class D amplifier according to embodiment 1, in which the conversion power consumption is only half of that of the conventional class D amplifier that converts on the positive side and the negative side at the same time.

According to the class D amplifier of embodiment 1, since analog feedback is realized by providing the resistors R3 and R4, the class D amplifier can amplify an analog input signal with better linearity, which cannot be performed by such digital processing operation as described in the aforementioned japanese patent application laid-open No. 2000-500625. According to the class D amplifier of embodiment 1, unlike in japanese patent laid-open No. 56-27001 described above, such a class D amplifier with low power consumption can provide low distortion when a transformer used in impedance conversion for cutting off a DC voltage is no longer necessary, and a DC output component therein is also approximately equal to zero volts.

Example 2

Next, embodiment 2 of the present invention will be described with reference to fig. 5. Fig. 5 is a circuit diagram showing a configuration example of a class D amplifier according to embodiment mode 2 of the present invention. The class D amplifier is arranged with resistors R51, R52, R53, R54, R55 AND R56, a capacitor C51, optional amplifiers 61 AND 64, comparators 62 AND 63, an AND circuit (low activity) 71, AND another AND circuit 72. The triangular waveform signal "a" is supplied to a positive side input terminal of the comparator 62, and the other triangular waveform signal "b'" is supplied to a positive side input terminal of the comparator 63.

The triangular waveform signal "b'" corresponding to the triangular waveform signal generated by the phase of the triangular waveform signal "b" obtained by inverting the triangular waveform signal "a" (i.e., phase-delayed by 180 degrees) is further delayed by a very small angle "θ". As a result, the triangular waveform signal "a" and the triangular waveform signal "b'" are signals having the same waveform, but different phases from each other (180 degrees + a very small angle "θ"). In this case, predetermined noise called "jitter" may be selectively supplied to the triangular waveform signals a and b', respectively. Since such a jitter noise is applied to each of these triangular waveform signals, distortion of the output waveform can be corrected. In addition to these triangular waveform signals a and b', a sawtooth waveform, an integral waveform, or the like can be selectively used.

One terminal of resistor R51 forms the input terminal for the analog input signal. And the other terminal of the resistor R51 is connected to the negative-side input terminal of the operational amplifier 61. The operational amplifier 61 and the capacitor C51 constitute an integrator. The comparator 62 compares the triangular waveform signal "a" with the output "c" of the integrator, and outputs a comparison result (output "j"). The comparator 63 compares the triangular waveform signal "b'" with the output "c" of the integrator, and also outputs a comparison result (output "k").

The AND circuit 71 corresponds to a buffer circuit having an AND gate function of low activity. When both the output "j" of the first comparator 62 AND the output "k" of the second comparator 63 are "low", the AND circuit 71 outputs a "high" potential signal, AND outputs the calculated signal as the negative side output "-OUT" of the class D amplifier. The AND circuit 72 corresponds to a buffer circuit having an AND gate function. When both the output "j" of the first comparator 62 AND the output "k" of the second comparator 63 are "high", the AND circuit 72 outputs a "high" potential signal, AND outputs the calculation signal as the positive side output "+ OUT" of the class-D amplifier.

The operational amplifier 64 and the resistors R53, R54, R55, R56 constitute a differential amplifier that amplifies the difference between the positive side output "+ OUT" and the negative side output "+ OUT". The output "1" of the differential amplifier is fed back to the input terminal of the operational amplifier 61 (i.e., the input terminal of the class D amplifier) through the resistor R52. As a result, the operational amplifier 64 and the resistors R52, R53, R54, R55, R56 constitute a feedback circuit.

Next, the operation of the class-D amplifier according to embodiment 2 is explained in conjunction with the above-described circuit arrangement. IN the case where the analog input signal is zero (no input signal), that is, "IN" is equal to "1/2 VDD", both the positive side output "+ OUT" and the negative side output "-OUT" are as shown IN fig. 6, and the energy ratio during high potential becomes almost zero to several percent. As a result, when the analog input signal is zero (no input signal), the current flowing from the class D amplifier to the load via the filter becomes very small.

In the case where the analog signal is a positive value, the positive side output "+ OUT" and the negative side output "-OUT" become similar to those in fig. 3. As a result, the positive-side output "+ OUT" becomes a signal generated by modulating the positive value of the analog signal in the pulse width modulation mode (i.e., "positive" when a zero voltage is supplied as a reference value). On the other hand, the negative side output "-OUT" continuously becomes low potential.

In the case where the analog signal is negative, both the positive side output "+ OUT" and the negative side output "-OUT" become similar to the case in fig. 4. As a result, the negative side output "-OUT" becomes a signal generated by modulating the negative value of the analog signal in a pulse width modulation mode (i.e., "negative" when 1/2VDD voltage is provided as a reference value). On the other hand, the positive side output "+ OUT" continuously becomes a low potential.

Similar to the class D amplifier according to embodiment 1 described above, by providing the above-described structural arrangement, the class D amplifier according to embodiment 2 can be greatly reduced in power consumption as compared with the class D amplifier in the related art, in the case where there is no input signal (i.e., in the case where the input is zero volts), since the period during which the output signal is high is sufficiently short to a desired value.

As a result, according to the class-D amplifier of embodiment 2, an analog input signal can be converted into PWM signals having three values consisting of zero, positive, and negative values, and then these converted PWM signals can be output. According to the class-D amplifier of embodiment 2, in the case where the analog input signal becomes higher than or equal to the predetermined value, the output signal thereof becomes a converted waveform of only one-sided signal of either one of the positive-side output "+ OUT" and the negative-side output "-OUT" in a similar manner as shown in fig. 3 and 4. As a result, the class D amplifier according to embodiment 2, in which the conversion power consumption is only half of that of the conventional class D amplifier that converts on the positive side and the negative side at the same time.

According to the class-D amplifier of embodiment 2, since analog feedback is realized by providing the operational amplifier 64 and the resistors R52, R53, R54, R55, R56, the class-D amplifier can amplify an analog input signal with better linearity, which cannot be performed by such digital processing operations as described in the aforementioned japanese patent laid-open No. 2000-500625. According to the class-D amplifier of embodiment 2, unlike in japanese patent laid-open No. 56-27001 described above, such a class-D amplifier with low power consumption can provide low distortion when a transformer used in impedance conversion for cutting off a DC voltage is no longer necessary, and a DC output component therein is also approximately equal to zero volts.

Next, fig. 7A to 7C show examples of output waveforms in the case where a sine wave is input to the analog signal input terminal of the class D amplifier according to embodiment 1 or embodiment 2 shown in fig. 1 or fig. 5. In embodiment 1 and embodiment 2, in the case where sine waves are input to the analog signal input terminals, their output waveforms are similar. Fig. 7(a) shows a low-pass filter and a load (resistor R) connected to the positive side output "+ OUT" and the negative side output "+ OUT" of the class D amplifiers according to embodiments 1 and 2. Fig. 7(b) shows a waveform of the output "POUT" after the output "+ OUT" has passed through the low-pass filter at the positive side of the class-D amplifier. In fig. 7(b), the waveform of the output "NOUT" after the negative side output "-OUT" of the class D amplifier has passed through the low-pass filter is also shown. Both output POUT and output NOUT are simply the top half of a sine wave. However, the output "OUT" corresponding to the signal supplied to the load as shown in fig. 7(c) will be a sine wave. The reason for this is as follows: that is, since a load (speaker, etc.) is connected between the output POUT and the output NOUT (i.e., between the positive-side output terminal "POUT" and the negative-side output terminal "NOUT" of the low-pass filter), as shown in fig. 7(c), the output "OUT" corresponding to a signal supplied to the load becomes a difference (OUT ═ POUT-NOUT) between the output POUT and the output NOUT, and thus a sine wave is formed.

In the class-D amplifiers according to embodiments 1 and 2 shown in fig. 1 and 5, at least the triangular waveform signal "a" and the triangular waveform signal "b'" obtained by inverting the triangular waveform signal "a" and further delaying the inverted triangular waveform signal "a" are used. As a result, even when there is no input signal in the class D amplifier according to embodiment 1 or embodiment 2, similarly to fig. 2 and 6, the positive side output "+ OUT" and the negative side output "+ OUT" are both output for a short time (the energy ratio during high potential is set to zero to several percent) so that a voltage is slightly output to the low-pass filter (outputs POUT, NOUT). Meanwhile, since a voltage defined by the output POUT-output NOUT is supplied to the load, the output OUT corresponding to a signal supplied to the load becomes zero volts. As a result, the class D amplifier according to embodiment 1 or embodiment 2 can supply an amplified signal with low distortion to a load in the case where the analog input terminal is changed from the no-signal state to the small-signal input state even when the state thereof is changed.

Example 3

Next, embodiment 3 of the present invention will be described with reference to fig. 8 to 11. Fig. 8 is a circuit diagram showing a configuration example of a class-D amplifier according to embodiment mode 3 of the present invention. Unlike the class D amplifier according to embodiment 1, in the class D amplifier, the delay circuits 21 and 22 are not provided as structural components. In the class D amplifier, a triangular waveform signal "a" is supplied to one terminal of a resistor R10, and another triangular waveform signal "b" is supplied to one terminal of another resistor R12. Apart from the above-described circuit arrangement of the class D amplifier in fig. 8, the class D amplifier is otherwise similar to the class D amplifier shown in fig. 1. It is to be understood that the respective resistance values of the resistors R5, R6, R7, R8, R9, R10, R11, and R12 constituting the combining circuit in this class-D amplifier are set in a case where the resistors R5, R6, R7, R8, R9, R10, R11, and R12 of the class-D amplifier according to embodiment 1 are not defined. The arrangement of the circuit configuration of the class D amplifier will be explained in detail below.

The class-D amplifier is arranged with resistors R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, AND R12, capacitors C1 AND C2, an operational amplifier 11, comparators 12 AND 13, an AND circuit (low activity) 31, AND another AND circuit 32. The predetermined triangular waveform signal "a" is supplied to one terminal of the resistors R9 and R11, respectively, in the figure. The predetermined triangular waveform signal "b" is supplied to one terminal of the resistors R11 and R12, respectively, in the figure. The triangular waveform signal "a" and the triangular waveform signal "b" have the same waveform but are 180 degrees out of phase. Assume that now the triangular waveform signal "a" is set to a triangular waveform as in claim 6 of the present invention, and the triangular waveform signal "b" is set to a triangular waveform having an opposite phase in the present invention.

One terminal of the resistors R1 and R2 constitutes a different input terminal for the analog input signal. One terminal of the resistor R1 constitutes a positive side input terminal (+ IN), and one terminal of the resistor R2 constitutes a negative side input terminal (-IN). The operational amplifier 11 and the capacitors C1 and C2 form an integrator. Analog input signals inputted by the resistors R1 and R2 in different manners are integrated by the integrator, and the integrated signal is outputted to the resistors R5, R6, R7, and R8.

The resistors R5, R6, R7, R8, R9, R10, R11, and R12 constitute a synthesizing circuit that synthesizes the triangular waveform signal "a '" or "b'" with the output signal of the integrator. The synthesizing circuit generates first to fourth four types of synthesized waveforms "e", "f", "g", "h".

The respective resistance values of the resistors R5, R6, R7, R8, R9, R10, R11, and R12 constituting the composite circuit are determined as follows: a time difference (phase difference) corresponding to an output signal of the synthesizing circuit based on these resistance values and output capacitances of the comparator 12 (first comparator) and the comparator 13 (second comparator) are generated between the first synthesized wave "e" and the second synthesized wave "f" and between the third synthesized waveform "g" and the fourth synthesized waveform "h".

In this circuit, the resistor R5 corresponds to the first resistor in claim 7 to which the invention relates. The resistor R6 corresponds to a fifth resistor in the present invention. The resistor R7 corresponds to the third resistor in the present invention. The resistance R9 corresponds to the second resistance in the present invention. The resistor R10 corresponds to the eighth resistor in the present invention. The resistor R11 corresponds to the fourth resistor in the present invention. The resistor R12 corresponds to the sixth resistor in the present invention.

The above-described synthesizing circuit includes the first synthesizing circuit by the fourth synthesizing unit. The first combining unit combines the negative side output of the operational amplifier 11 constituting the integrator with the triangular waveform signal "a" to generate a first combined waveform "e". The first combining unit includes a resistor R5 (first resistor) having one terminal connected to the negative side output of the operational amplifier 11, and a resistor R9 (second resistor). A triangular waveform "a" is provided to one terminal of the resistor R9. The other terminal of resistor R5 is connected to the other terminal of resistor R9 to form an output terminal.

The second synthesizing unit synthesizes the positive side output of the operational amplifier 11 with the triangular waveform "b" to generate a second synthesized waveform "f". The second combining unit includes a resistor R7 (third resistor) having one terminal connected to the positive side output of the operational amplifier 11, and a resistor R11 (fourth resistor). A triangular waveform "b" is provided to one terminal of the resistor R11. The other terminal of resistor R7 is connected to the other terminal of resistor R11 to form an output terminal.

The third synthesis unit synthesizes the negative side output of the operational amplifier 11 with the triangular waveform "b" to generate a third synthesized waveform "g". The third synthesizing unit includes a resistor R6 (fifth resistor) having one terminal connected to the negative side output of the operational amplifier 11, and a resistor R12 (sixth resistor). A triangular waveform "b" is provided to one terminal of the resistor R12. The other terminal of resistor R6 is connected to the other terminal of resistor R12 to form an output terminal.

The fourth synthesis unit synthesizes the positive side output of the operational amplifier 11 with the triangular waveform "a" to generate a fourth synthesized waveform "h". The fourth combining unit includes a resistor R8 (seventh resistor) having one terminal connected to the positive side output of the operational amplifier 11, and a resistor R10 (eighth resistor). A triangular waveform "a" is provided to one terminal of the resistor R10. The other terminal of resistor R8 is connected to the other terminal of resistor R10 to form an output terminal.

Preferably, the respective resistance values (first to fourth resistances) of the resistances R5, R7, R9, and R11 connected to the comparator 12 may be set to a resistance value obtained by multiplying the respective resistance values of the resistances R6, R8, R10, and R12 connected to the comparator 13 by a value other than "1".

For example, the resistance values of the resistors R5, R7, R9, and R11 and the resistance values of the resistors R6, R8, R10, and R12 are set by:

R6＝R8＝R5×α，R5＝R7，

R10＝R12＝R9×α，R9＝R11，

in the above formula, the symbol "α" is not equal to 1.

As is clear from the above-described formula, the resistance value setting condition can be selectively set by:

r5 ═ R7 ═ R9 ═ R11, or

R5 ═ R7 but not R9 ═ R11.

In the case of (R6 ═ R8) and (R10 ═ R12), it is assumed that (R6, R8, R10, R12) is equal to (R5, R7, R9, R11) multiplied by "α" (or 1/α).

As a specific example, assuming that the resistance values of the resistors R5, R7, R9, R11 are each set to 1[ K Ω ], the resistance values of the resistors R6, R8, R10, R12 may be selectively set to 2[ K Ω ] or 500[ K Ω ]. At this time, the symbol "α" is equal to 0.5.

Now, it is assumed that the resistances of the resistors R5, R7, R9, R11 are each set to 20[ K Ω ], and the resistances of the resistors R6, R8, R10, R12 are optionally set to 30[ K Ω ]. At this time, the symbol "α" is equal to 1.5.

Now, it is assumed that the resistances of the resistors R5, R7, R9, R11 are each set to 1[ K Ω ], and the resistances of the resistors R6, R8, R10, R12 are optionally set to 30[ K Ω ]. At this time, the symbol "α" is equal to 30.

As is apparent from the above description, the above-described synthesizing circuit can establish a time difference (phase difference) between the first synthesized waveform "e" and the second synthesized waveform "f" and between the third synthesized waveform "g" and the fourth synthesized waveform "h" by using a difference between resistance values of the resistors R5, R7, R9, R11 connected to the comparator 12 and the resistors R6, R8, R10, R12 connected to the comparator 13 and further between input capacitances of the comparators 12 and 13.

The comparator 12 (first comparator) compares the first synthesized waveform "e" with the second synthesized waveform "f" to output a comparison result. When the first synthesized waveform "e" is larger than the second synthesized waveform "f", the first comparator 12 outputs a signal of a predetermined "low" potential (for example, zero potential), and when the first synthesized waveform "e" is smaller than the second synthesized waveform "f", the first comparator 12 outputs a signal of a predetermined "high" potential. The comparator 13 (second comparator) compares the third synthesized waveform "g" with the fourth synthesized waveform "h" to output one comparison result. When the third synthesized waveform "g" is larger than the fourth synthesized waveform "h", the second comparator 13 outputs a signal of a predetermined "low" potential (for example, zero potential), and when the third synthesized waveform "g" is smaller than the fourth synthesized waveform "h", the second comparator 13 outputs a signal of a predetermined "high" potential.

The AND circuit 31 corresponds to a buffer circuit having an AND gate function of a negative logic input. The AND circuit 31 performs an AND calculation (low activity) in which the AND circuit 31 outputs a "high" potential signal when both the output of the first comparator 12 AND the output of the second comparator 13 are "low", AND outputs "-OUT" as the negative side of the class-D amplifier. Resistor R3 constitutes a first feedback circuit. The first feedback circuit feeds back the output of the AND circuit 31 functioning as a buffer to the positive side input of the operational amplifier 11.

The AND circuit 32 corresponds to a buffer circuit having an AND calculation function. AND performs an AND calculation operation between the output of the first comparator 12 AND the output of the second comparator 13 AND outputs the calculation result as the positive side output "+ OUT" of the class-D amplifier. Resistor R4 forms a second feedback circuit. The second feedback circuit feeds back the output of the AND circuit 32 functioning as a buffer to the negative side input of the operational amplifier 11.

A load (speaker, etc.) is connected via a low-pass filter between the positive side output "+ OUT" and the negative side output "-OUT" of the class D amplifier. Due to the provision of these circuit arrangements, the class-D amplifier can amplify analog input signals "+ IN" and "-IN" with low distortion without providing a transformer, and further, can drive a load while reducing power consumption.

Next, an operation of the class-D amplifier provided with the arrangement described above according to embodiment 3 is explained with reference to fig. 9 to 11. Fig. 9 to 11 are waveform diagrams illustrating operations of respective circuit portions of the class D amplifier shown in fig. 8. Fig. 9 shows waveforms of the various circuit parts of the class D amplifier when the value of the analog input signal "+ IN" is equal to the value of the analog signal "-IN", i.e. when the differential input is zero volt-age (no input signal). Fig. 10 shows waveforms of the respective circuit portions of the class-D amplifier when (analog input signal "+ IN") > (analog input signal "-IN"), that is, when the differential input is positive. Fig. 11 shows waveforms of the respective circuit parts of the class-D amplifier when (analog input signal "+ IN") < (analog input signal "-IN"), i.e., when the differential input is negative.

As shown in fig. 9 to 11, the main operation parts in the respective circuit parts of the class D amplifier according to embodiment 3 are the same as those in the respective circuit parts of the class D amplifier according to embodiment 1 shown in fig. 2 to 4. But the class D amplifier has the following different operations. That is, two sets of triangular waveform signals "a" and "b" are provided as triangular waveform signals, unlike the class-D amplifier according to embodiment 1 which provides four sets of triangular waveform signals a, a ', b'. The operation of the respective circuit portions in the class D amplifier will be described in detail below.

The operation as in fig. 9, i.e. without differential input (zero volt input), will be explained first. The phase of the triangular waveform signal "a" is different from the phase of the triangular waveform signal "b" by 180 degrees. In this case, a predetermined noise called "jitter" is selectively supplied to the triangular waveform signals a and b, respectively. Since the jitter noise is supplied to each triangular waveform signal, distortion of the output waveform can be corrected. In addition to these triangular waveform signals a and b, a sawtooth waveform, an integral waveform, or the like may be selectively used.

The phase relationship between the triangular waveform signal "a" and the positive side output of the integrator (positive side output of the operational amplifier 11) "d" is substantially equal to each other. The phase relationship between the triangular waveform signal "b" and the negative side output of the integrator (negative side output of the operational amplifier 11) "c" is also substantially equal to each other.

The inputs of the comparators 12 and 13, i.e., the first to fourth synthesized waveforms e, f, g, h have waveforms synthesized with the output of the integrator. Then, the phase of the first synthesized waveform "e" is different from the phase of the second synthesized waveform "f" by about 180 degrees. The phase of the third synthesized waveform "g" is different from the phase of the fourth synthesized waveform "h" by about 180 degrees. The waveform of the first synthesized waveform "e" is substantially equal to the waveform of the fourth synthesized waveform "h", and the first and fourth synthesized waveforms "e" and "h" are different by a very small angle "θ'". The waveform of the second synthesized waveform "f" is substantially equal to the waveform of the third synthesized waveform "g", and the second and third synthesized waveforms "f" and "g" differ by a very small angle "θ'".

As explained earlier, the reason why a very small angle "θ'" is generated between the first synthesized waveform "e" and the fourth synthesized waveform "h" and between the second synthesized waveform "f" and the third synthesized waveform "g" will be given below. That is, the respective resistance values of the resistors R5, R7, R9, and R11 connected to the comparator 12 are set to be obtained by multiplying the respective resistance values of the resistors R6, R8, R10, and R12 connected to the comparator 13 by values other than the value "1". In other words, based on these resistance values and input capacitances of the comparators 12 and 13, the very small angle θ' described above is generated. It will be appreciated that this very small angle theta' corresponds to the very small angle theta that occurs in the operating waveform of the class D amplifier of embodiment 1 shown in figure 2. This very small angle θ' can be adjusted in a simple manner by adjusting the resistance values of the resistors R5 to R12.

The outputs "j" and "k" of the comparators 12 and 13 have the same waveforms as those of the comparators 12 and 13 of the class D amplifier according to embodiment 1 shown in fig. 2. The positive side output "+ OUT" and the negative side output "-OUT" of this class D amplifier have the same waveforms as the positive side output "+ OUT" and the negative side output "-OUT" of the class D amplifier according to embodiment 1 shown in fig. 2. As described above, the operations of the comparators 12, 13 AND the AND circuits 31, 32 provided in the class D amplifier are the same as the operations of the comparators 12, 13 AND the AND circuits 31, 32 of the class D amplifier according to embodiment 1. The operation of the feedback circuit (resistors R3 and R4) and the integrator (operational amplifier 11 and capacitors C1, C2) provided in the class D amplifier is the same as that of the class D amplifier according to embodiment 1.

As a result, similarly to the class D amplifier according to embodiment 1, in the class D amplifier, when the input signal is not supplied, the periods in which the positive side output + OUT and the negative side output-OUT are high potential can both be set to the energy ratio of 0 to several percent. As a result, in the case where the class D amplifier in the present embodiment is used for a small signal, the above-described low pass (LC filter or the like) arranged between the output terminal and the load can be eliminated.

When the above-described arrangement is provided in this class D amplifier, similarly to the class D amplifier of embodiment 1, in the case where there is no analog signal (i.e., in the case of zero-volt value input), since the period of time during which the output signal is high is sufficiently short to a desired value, power consumption can be greatly reduced compared to the class D amplifier in the related art.

Next, description is made of (analog input signal "+ IN") > (analog input signal "-IN"), i.e., the operation of the class-D amplifier IN the case where the differential input is a positive value as shown IN fig. 10. Comparing fig. 10 with fig. 3, it is found that the only difference is that two sets of triangular waveform signals "a" and "b" are provided as triangular waveforms in the class D amplifier. As a result, even in the case where the differential input is positive, the class-D amplifier can operate in the same manner as the class-D amplifier according to embodiment 1 except for its synthesis circuit portion. As a result, in the class D amplifier, when the differential input is positive, the positive side output "+ OUT" becomes a signal generated by modulating the positive value (differential value) of the analog input signal in the pulse width modulation manner, and the negative side output "+ OUT" continuously becomes a low potential.

Next, the operation of the class-D amplifier will be described (analog input signal "+ IN") < (analog input signal "-IN"), i.e., IN the case where the differential input is a positive value as shown IN fig. 11. Comparing fig. 11 with fig. 4, it is found that the only difference is that two sets of triangular waveform signals "a" and "b" are provided as triangular waveforms in the class-D amplifier. As a result, even in the case where the differential input is negative, the class-D amplifier can operate in the same manner as the class-D amplifier according to embodiment 1 except for its synthesis circuit part. As a result, in this class D amplifier, when the differential input is negative, the negative side output "+ OUT" becomes a signal generated by modulating the negative value (differential value) of the analog input signal in the pulse width modulation manner, and the positive side output "+ OUT" continuously becomes a low potential.

As a result, similar to the class D amplifier of embodiment 1, according to the class D amplifier of embodiment 3, the analog input signal can be converted into PWM signals having three values consisting of a zero voltage value, a positive value, and a negative value, and these converted PWM signals are output. According to the class-D amplifier of embodiment 3, in the case where the analog input signal becomes higher than or equal to the predetermined value, the output signal thereof becomes a transition waveform of a one-sided signal of only either one of the positive-side output "+ OUT" and the negative-side output "+ OUT", as represented in fig. 10 and 11. As a result, the class D amplifier according to embodiment 3, in which the conversion power consumption is only half of that of the conventional class D amplifier that converts on the positive side and the negative side at the same time.

According to the class-D amplifier of embodiment 3, since analog feedback is realized by providing the resistors R3 and R4, the class-D amplifier can amplify an analog input signal with better linearity, which cannot be performed by such digital processing operation as described in the aforementioned japanese patent application laid-open No. 2000-500625. According to the class-D amplifier of embodiment 3, unlike in japanese patent laid-open No. 56-27001 described above, such a class-D amplifier with low power consumption can provide low distortion when a transformer used in impedance conversion for cutting off a DC voltage is no longer necessary, and a DC output component therein is also approximately equal to zero volts.

Also, according to the class-D amplifier of embodiment 3, when the delay circuits 21, 22, and 81 are not provided as structural elements, since the resistance values of the resistors R5 to R12 are adjusted, the time differences (phase differences) between the first synthesized waveform "e" and the second synthesized waveform "f", and between the third synthesized waveform "g" and the fourth synthesized waveform "h" are different from those of the class-D amplifiers described in embodiments 1 and 2 described above. As a result, the class D amplifier of this embodiment 3 can be designed and manufactured in a simple manner, and moreover, a class D amplifier having high performance can be provided.

Example 4

Next, embodiment 4 of the present invention will be described with reference to fig. 12 to 17. Fig. 12 is a circuit diagram showing a configuration example of a class D amplifier according to embodiment mode 4 of the present invention. The same reference numerals denote the same elements as those of the class D amplifier according to embodiment 1. The class D amplifier according to embodiment 4 is different from the class D amplifiers according to embodiments 1 and 2 in that a single triangular waveform generating circuit is provided. The class D amplifier will be described in detail below.

The class-D amplifier includes resistors R1, R2, R3, AND R4, capacitors C1, C2, AND C100, an operational amplifier 11, comparators 112 AND 113, converters 121 AND 122, AND circuits 131 AND 132, AND a current source 140. The capacitor 100 and the current source constitute a triangular waveform generation circuit that outputs a triangular waveform to the negative side inputs of the comparators 112 and 113.

One terminal of each of the resistors R1 and R2 is a differential input terminal for the analog input signal. One end of the resistor R1 is a positive side input terminal (+ IN) and one end of the resistor R2 is a negative side input terminal (-IN). The operational amplifier 11 and the capacitors C1 and C2 form an integrator. The analog input signals differentially input to the resistors R1 and R2 are integrated by the integrator and output to the comparators 112 and 113.

The negative side output of the operational amplifier 11 is connected to the positive side input terminal of the comparator 112 (first comparator). The positive side output of the operational amplifier 11 is connected to the positive side input terminal of the comparator 113 (second comparator). The negative side input terminals of the comparators 112 and 113 are respectively connected to one end of the capacitor 100, the other end of the capacitor 100 is connected to ground, and the other end of the current source is connected to ground. With such an arrangement, the comparator 112 compares the negative side output of the operational amplifier 11 with the output of the triangular waveform generating circuit and outputs the comparison result. The comparator 113 compares the positive side output of the operational amplifier 11 with the output of the triangular waveform generation circuit and outputs the comparison result.

The output of the comparator 112 is connected to the input terminal of the converter 121 AND one input terminal of an AND circuit 132 (second buffer). An output of the comparator 113 is connected to an input terminal of the converter 122 AND one input terminal of an AND circuit 131 (first buffer). The output of the converter 121 is connected to the other input terminal of the AND circuit 131. The output of the converter 122 is connected to the other input terminal of the AND circuit 132. With such an arrangement, the AND circuit 131 calculates the logical product of the signals converted from the output of the comparator 112 AND the output of the comparator 113, AND outputs the calculation result. The AND circuit 132 calculates a logical product of signals converted from the output of the comparator 113 AND the output of the comparator 112, AND outputs the calculation result.

The output of the AND circuit 131 is the positive side output + OUT of the class D amplifier. The positive side output + OUT is fed back to the negative side input of the operational amplifier through resistor R4. The output of the AND circuit 132 is the negative side output-OUT of the class D amplifier. The negative side output-OUT is fed back to the positive side input of the operational amplifier through resistor R3.

The circuit diagram of fig. 13 shows a specific configuration of the current source 140 of the class D amplifier. The current source 140 and the capacitor 100 constitute a triangular waveform generating circuit. The current source 140 is constituted by transistors T1 and T2, switches S1 and S2, comparators 141 and 142, and NAND circuits 143 and 144.

The transistors T1 and T2 are formed of Field Effect Transistors (FETs). Voltage V for controlling charging current value of capacitor 100_BPIs provided to the gate of transistor T1. A voltage V for controlling the discharge current value of the capacitor_BNIs provided to the gate of transistor T2. The switches S1 and S2 include analog switches and can be constructed by FETs. The switches S1 and S2 switch the flow direction of the current from the current source 140, that is, switch the charging and discharging of the capacitor 100. The current input/output terminal of the transistor T1, the switches S1 and S2, and the current input/output terminal of the transistor T2 are connected in series with each other as shown in fig. 13. The negative side input terminal of the comparator 141 and the positive side input terminal of the comparator 142 are connected to the connection point of the switches S1 and S2. The connection point is also connected to a capacitor 100 and constitutes the output of the triangular waveform generation circuit.

The comparator 142 compares the required first potential VL with the potential of the connection point, and outputs the comparison result. The comparator 141 compares the required second potential VH with the potential of the connection point, and outputs the comparison result. The second potential is assumed to be higher than the first potential. The difference between the second potential VH and the first potential VL is set to the amplitude of the triangular waveform. The NAND circuits 143 and 144 are connected so as to constitute one flip-flop circuit. The flip-flop has as input the outputs of comparators 141 and 142. The output of the trigger circuit controls the opening/closing of the switches S1 and S2. That is, the output of the trigger circuit switches the charging and discharging of the capacitor 100 to switch the rise and fall of the triangular waveform.

The waveform diagram of fig. 14 shows the operation of the current source 140.

First, the operation of the triangular waveform G in the case where the potential of the connection point is lower than the first potential VL, that is, in the case indicated by the broken line K1, is described. In the case of the broken line K1, the output of the comparator 142 becomes low, and the switch S1 is made open and the switch S2 is made closed. Thus, the charging current flows through the transistor T1 and the switch S1 to the capacitor 100. Accordingly, the triangular waveform G, which is the potential of the capacitor 100, rises.

When the triangular waveform F exceeds the first potential VL and reaches the second potential VH, the output of the comparator 141 becomes low and causes the switch S2 to be opened and the switch S1 to be opened. Thus, the discharge current of the capacitor 100 flows through the transistor T2 and the switch S2 to ground. Therefore, the triangular waveform G falls.

When the triangular waveform G reaches the first potential VL, the output of the comparator 142 becomes low, and causes the switch S1 to be opened and the switch S2 to be closed. Therefore, the triangular waveform G rises again for the charging current. By repeating the operation thereafter, a triangular waveform G as shown in fig. 14 is generated. The inclination of the triangular waveform G at the time of falling is set by the voltage VBN for controlling the discharge current and the capacity of the capacitor 100.

Next, an operation in the case where the potential of the connection point of the triangular waveform G is higher than the first potential VL, that is, in the case indicated by the broken line K2, is described. In the case of the broken line K2, the output of the comparator 141 becomes low, and the switch S2 is made open and the switch S1 is made closed. Thus, the discharge current of the capacitor 100 flows through the transistor T2 and the switch S2. Therefore, the triangular waveform G, which is the potential of the capacitor 100, falls. Thereafter, as described above, the charging and discharging of the capacitor 100 is repeated and a triangular waveform G as shown in fig. 14 is generated.

Therefore, in the class D amplifier of the present embodiment, the triangular waveform generation circuit having a simple structure is constructed by the capacitor 100 and the current source 140 provided. Therefore, a highly efficient and low distortion class D amplifier with low cost can be provided.

Next, the operation of the class D amplifier according to embodiment 4 will be described with reference to fig. 15 to 17. Fig. 15 to 17 show waveforms of the operation of the respective parts of the class D amplifier shown in fig. 12.

Fig. 15 shows waveforms of respective portions of the class-D amplifier at (analog input signal "+ IN") > (analog input signal "-IN"), that is, when the differential input is positive. The triangular waveform G is a triangular waveform in which the first potential VL is a minimum value and the second potential VH is a maximum value.

Since the differential input of the integrator is positive, the negative side output a of the integrator is at a lower potential than the positive side output B of the integrator. Fig. 15 shows the driving waveforms of the switches S1 and S2 of the current source 140. The switch S1 of the current source 140 opens in response to the high signal during the rising phase of the triangular waveform G. The switch S1 opens in response to a low signal during the falling phase of the triangular waveform G. The switch S2 of the current source 140 is opened in response to the low signal during the rising phase of the triangular waveform G. The switch S2 opens in response to the high signal during the falling phase of the triangular waveform G.

The output C of the comparator 112 becomes high when the comparison result of the negative side output a of the integrator with the triangular waveform G is a > G, and becomes low when the comparison result is a < G. The output D of the comparator 113 becomes high when the comparison result of the positive side output B of the integrator with the triangular waveform G is B > G, and becomes low when the comparison result is B < G.

When both the values transitioned from the output C of the comparator 112 AND the output D of the comparator 113 are high, the output (+ OUT) E of the AND circuit 131 becomes high. Therefore, the energy ratio during the period when the positive side output + OUT is at a high potential is substantially proportional to the magnitude of the positive value (difference value) of the analog input signal. In other words, the positive side output + OUT is a pulse width modulated signal of a positive value (differential value) of the analog input signal.

On the other hand, when both the output of the comparator 112 AND the value transitioned from the output D of the comparator 113 are high, the output (-OUT) F of the AND circuit 132 becomes high. Here, the negative side output-OUT is always low.

Fig. 16 shows waveforms of the various parts of the class D amplifier when (analog input signal "+ IN") - (analog input signal "-IN"), i.e. when there is no differential input (0 volt input). The triangular waveform G shown in fig. 16 is the same as the triangular waveform G shown in fig. 15. Since the operations of the switches S1 and S2 of the current source 140 with respect to the triangular waveform F are the same as those shown in fig. 15, the drive signals of the switches S1 and S2 are omitted from fig. 16.

Since the differential input of the integrator is (+ IN) — IN, the negative side input a of the integrator and the positive side input B of the integrator have the same potential. Since the output a is equal to the output B, the output C of the comparator 112 and the output D of the comparator 113 have the same waveform and phase.

Since the output (+ OUT) E of the AND circuit 131 is (the inverted value of the output C) × (the output D), the output E is low potential in most of the entire period. Since the output (-OUT) F is (output C) × (the inverse of output D), the output F is low for most of the entire cycle. As shown in fig. 16, there is only a short period during which the positive side output + OUT and the negative side output-OUT are high potential due to the difference in delay time caused by the difference in offset voltages of the operational amplifier 11 and the elements constituting the comparators 112 and 114 and the inverters 121 and 122. Therefore, the positive side output + OUT and the negative side output-OUT can be simply assumed to be strictly low in the entire period.

As described above, according to the class D amplifier of embodiment 4, since the period in which the output signal is high can be shortened very short when the analog input signal (in the case of 0 volt value input) is not supplied, the power consumption can be remarkably reduced compared to the conventional device having a simple structure.

Fig. 17 shows waveforms of the respective sections of the class D amplifier when (analog input signal "+ IN") < (analog input signal "-IN"), i.e., when the differential input is negative. The triangular waveform F is the same as the triangular waveform G shown in fig. 15. Since the operations of the switches S1 and S2 of the current source 140 according to the triangular waveform G are the same as the operations shown in fig. 15, the driving waveforms of the switches S1 and S2 are omitted from fig. 17.

The negative side output a of the integrator is at a higher potential than the positive side output B of the integrator. When the comparison result of the negative side output a of the integrator with the triangular waveform G is a > G, the output C of the comparator 112 becomes high, and when the comparison result is a < G, the output C of the comparator 112 becomes low. When the comparison result of the positive side output B of the integrator with the triangular waveform G is B > G, the output D of the comparator 113 becomes high, and when the comparison result is B < G, the output D of the comparator 113 becomes low.

When both the output C of the comparator 112 AND the inverted value of the output D of the comparator 113 are high, the output (-OUT) F of the AND circuit 132 becomes high. Therefore, the energy ratio during the period when the positive side output + OUT is high is substantially proportional to the magnitude of the negative value (difference value) of the analog input signal. In other words, the negative side output-OUT is a pulse width modulated signal of the negative value (differential value) of the analog input signal.

On the other hand, when both the values transitioned from the output C of the comparator 112 AND the output D of the comparator 113 are high, the output (+ OUT) E of the AND circuit 131 becomes high. Here, the positive side output + OUT is always low.

As described above, according to the class D amplifier of embodiment 4, an analog signal is output by converting it into a 3-value PWM signal composed of a 0-voltage value, a positive value, and a negative value. According to the class-D amplifier of embodiment 4, when the analog input signal is a value other than 0 volt, the switching waveforms appear only on the positive side output + OUT and the negative side output-OUT, as shown in fig. 15 and 17.

According to the class-D amplifier of embodiment 4, since the resistors R3 and R4 constitute an analog feedback circuit, the analog input signal can be amplified with good linearity without performing digital processing as described in japanese patent laid-open No. 2000-500625. Furthermore, according to the class-D amplifier of embodiment 4, the direct-current output component can be substantially removed without providing a transformer for impedance conversion and direct voltage disconnection as described in, for example, japanese patent laid-open No. 56-27001. Thus, a low distortion, high power efficiency class D amplifier can be provided.

Although the embodiment mode of the present invention has been described in detail with reference to the drawings, the specific structure thereof is not limited to the embodiment mode, but the defined structure can be significantly covered within the scope not departing from the technical spirit of the present invention.

For example, although in the class D amplifier of the above-described embodiment, the integrator is constructed by a basic integrator, the present invention is not limited thereto, and the integrator may be constructed by a high-order integrator. By the similar configuration, the loop gain can be increased and the distortion rate can be further reduced.

In the above description, the present invention has been described as a class D amplifier, but the present invention is not limited thereto. Therefore, the present invention can be provided to a signal processing circuit, as well as various pulse width modulation amplifiers, in addition to the class D amplifier.

Claims (10)

1. A class D amplifier, comprising:

an integrator for integrating the analog input signal;

a first comparator for comparing an output of the integrator with the first triangular waveform;

a second comparator for comparing an output of the integrator with a second triangular waveform that is a waveform obtained by changing a phase of the first triangular waveform by 180 degrees ± a predetermined angle;

a buffer circuit for outputting a positive side output signal and a negative side output signal based on an output of the first comparator and an output of the second comparator; and

a feedback circuit for feeding back a difference between the positive side output signal and the negative side output signal to an input terminal of the integrator.

2. The class D amplifier of claim 1, wherein the buffer circuit comprises:

a first buffer circuit for calculating a logical product of an output of the first comparator and an output of the second comparator to output the calculated result as an output signal of a negative side; and

a second buffer circuit for calculating a logical product of an output of the first comparator and an output of the second comparator to output the calculated result as an output signal of a positive side.

3. A class D amplifier as claimed in claim 1, wherein the feedback circuit comprises a differential amplifier for amplifying the difference between the positive side output signal and the negative side output signal.

4. A class D amplifier, comprising:

an integrator for integrating a difference between a positive-side input signal and a negative-side input signal for constituting an analog input signal;

a delay circuit for delaying the phase of the triangular waveform by an angle;

a synthesizing circuit for synthesizing an output of the integrator, the triangular waveform, and an output of the delay circuit with each other to output a plurality of output signals;

a comparator for comparing a plurality of output signals of the synthesizing circuit with each other;

a buffer circuit for inputting an output of the comparator; and

and the feedback circuit is used for feeding back the output of the buffer to the input end of the integrator.

5. The class D amplifier of claim 4, wherein,

the triangular waveform is composed of a first triangular waveform and a second triangular waveform corresponding to a waveform generated by changing the phase of the first triangular waveform by 180 degrees,

the delay circuit includes a first delay circuit for delaying the phase of the first triangular waveform by an angle, and a second delay circuit for delaying the phase of the second triangular waveform by an angle,

the synthesizing circuit synthesizes a negative side output of the integrator with the first triangular waveform to generate a first synthesized waveform, synthesizes a positive side output of the integrator with the second triangular waveform to generate a second synthesized waveform, synthesizes a negative side output of the integrator with an output of the second delay circuit to generate a third synthesized waveform, and synthesizes a positive side output of the integrator with an output of the first delay circuit to generate a fourth synthesized waveform,

the comparator includes a first comparator for comparing the first synthesized waveform with the second synthesized waveform, and a second comparator for comparing the third synthesized waveform with the fourth synthesized waveform,

the buffer circuit includes a first buffer circuit for calculating a logical product of an output of the first comparator and an output of the second comparator, and a second buffer circuit for calculating a logical product of an output of the first comparator and an output of the second comparator, and

the feedback circuit includes a first feedback circuit for feeding back an output of the first buffer circuit to a positive side input of the integrator, and a second feedback circuit for feeding back an output of the second buffer circuit to a negative side input of the integrator.

6. A class D amplifier, comprising:

an integrator for integrating a difference between a positive-side input signal and a negative-side input signal for constituting an analog input signal;

a synthesizing circuit for synthesizing an output of the integrator with a triangular waveform, the output of the integrator being synthesized with a triangular waveform having an inverted phase from the aforementioned triangular waveform so as to output a plurality of signals, wherein the inverted phase triangular waveform corresponds to a waveform changed by 180 degrees in phase in accordance with the aforementioned triangular waveform;

a comparator for comparing output signals of the synthesizing circuits with each other;

a buffer circuit for inputting an output of the comparator thereto; and

a feedback circuit for feeding back an output of the buffer circuit to an input terminal of the integrator,

wherein the combining circuit includes a plurality of resistors having at least two resistance values and is arranged to generate a phase difference between a plurality of signals corresponding to an output of the combining circuit based on the resistance values of the plurality of resistors and an input capacitance of the comparator.

7. The class D amplifier of claim 6, wherein,

the synthesis circuit includes: a first synthesizing section for synthesizing the negative side output of the integrator with the triangular waveform to generate a first synthesized waveform; a second synthesizing section for synthesizing the positive side output of the integrator with the inverted phase triangular waveform to generate a second synthesized waveform; a third synthesizing section for synthesizing a negative side output of the integrator with the inverted-phase triangular waveform to generate a third synthesized waveform; and a fourth synthesizing section for synthesizing the positive side output of the integrator with the triangular waveform to generate a fourth synthesized waveform;

the first combining section includes a first resistor having one terminal connected to the negative side output of the integrator, and a second resistor, wherein the triangular waveform is supplied to one terminal of the second resistor; the other terminal of the first resistor is connected to the other terminal of the second resistor to form an output terminal;

the two combining sections include a third resistor having one terminal connected to the positive side output of the integrator, and a fourth resistor, wherein the inverted triangular waveform is supplied to one terminal of the fourth resistor; the other terminal of the third resistor is connected to the other terminal of the fourth resistor to form an output terminal;

the third synthesis section includes a fifth resistor having one terminal connected to the negative side output of the integrator, and a sixth resistor, wherein the inverted-phase triangular waveform is supplied to one terminal of the sixth resistor; the other terminal of the fifth resistor is connected to the other terminal of the sixth resistor to constitute an output terminal;

the fourth combining section includes a seventh resistor having one terminal connected to the positive side output of the integrator, and an eighth resistor, wherein the triangular waveform is supplied to one terminal of the eighth resistor; the other terminal of the seventh resistor is connected to the other terminal of the eighth resistor to constitute an output terminal;

the comparator includes a first comparator having one input terminal connected to the output terminal of the first combining section and the other input terminal connected to the output terminal of the second combining section, and a second comparator having one input terminal connected to the output terminal of the third combining section and the other input terminal connected to the output terminal of the fourth combining section;

the buffer circuit includes a first buffer circuit for calculating a logical product of an output of the first comparator and an output of the second comparator, and a second buffer circuit for calculating a logical product of an output of the first comparator and an output of the second comparator;

the feedback circuit comprises a first feedback circuit for feeding back the output of the first buffer circuit to the positive side input of the integrator, and a second feedback circuit for feeding back the output of the second buffer circuit to the negative side input of the integrator; and also

The resistance value of any one of the first resistor, the second resistor, the third resistor and the fourth resistor is different from the resistance value of any one of the fifth resistor, the sixth resistor, the seventh resistor and the eighth resistor.

8. The class-D amplifier of claim 7, wherein a resistance value of each of the first, second, third and fourth resistors is obtained by multiplying a value other than 1 according to a resistance value of each of the fifth, sixth, seventh and eighth resistors.

9. A class D amplifier, comprising:

an integrator for integrating a difference between a positive-side input signal and a negative-side input signal for constituting an analog input signal;

a triangular waveform generating circuit including a current source and a capacitor;

a comparator for comparing an output of the integrator with an output of the triangular waveform generating circuit;

a buffer circuit for inputting an output of the comparator; and

a feedback circuit for feeding back an output of the buffer circuit to an input terminal of the integrator,

wherein,

one end of the capacitor is connected to one input terminal of the comparator, an

The current source converting a direction of an output current to repeatedly charge and discharge a capacitor, one end of the current source being connected to one end of the capacitor,

the current source flows a current in a direction in which the capacitor is charged when the potential of the capacitor is lower than a first potential and flows a current in a direction in which the capacitor is discharged when the potential of the capacitor is higher than a second potential, and

the second potential is higher than the first potential.

10. The class D amplifier of claim 9, wherein,

the comparator includes a first comparator for comparing a negative side output of the integrator with an output of the triangular waveform generating circuit, and a second comparator for comparing a positive side output of the integrator with an output of the triangular waveform generating circuit,

the buffer circuit includes a first buffer circuit for calculating a logical product of an inverted value of an output of the first comparator and an output of the second comparator, and a second buffer circuit for calculating a logical product of inverted values of the first comparator and the second comparator, and

the feedback circuit includes a first feedback circuit for feeding back an output of the first buffer circuit to a negative side input of the integrator, and a second feedback circuit for feeding back an output of the second buffer circuit to a positive side input of the integrator.

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