CN100468741C - Memory device and manufacturing method of the same - Google Patents
Memory device and manufacturing method of the same Download PDFInfo
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- CN100468741C CN100468741C CNB200580018287XA CN200580018287A CN100468741C CN 100468741 C CN100468741 C CN 100468741C CN B200580018287X A CNB200580018287X A CN B200580018287XA CN 200580018287 A CN200580018287 A CN 200580018287A CN 100468741 C CN100468741 C CN 100468741C
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Abstract
An easy-to-use and inexpensive memory device is provided while maintaining product specifications and productivity even when a memory is formed on the same substrate as other functional circuits. The memory device of the invention includes a memory cell formed on an insulating surface. The memory cell includes a semiconductor film having two impurity regions, a gate electrode, and two wirings connected to the respective impurity regions. The two wirings are insulated from each other by applying a voltage between the gate electrode and at least one of the two wirings to alter the state of the semiconductor film.
Description
Technical field
The present invention relates to memory device, relate in particular to nonvolatile semiconductor memory member.
Background technology
In modern society, use many electronic equipments and produce and use various data, thereby need storage memory of data part.The various memory devices of making today and using all respectively have pluses and minuses, and depend on that the data that will store and use select.
For example, the volatile memory of the time losing its memory content in outage comprises DRAM and SRAM.Volatile memory is used because of volatibility limitedly; Yet it is used as main storage or utilizes the cache memory of of short duration access time.Because each memory cell all has reduced size, thus big capacity DRAM can easily be made, although it is controlled with complex way and very power consumption.Simultaneously, SRAM comprises the memory cell that is made of CMOS and is easy to make and control, although big capacity SRAM needs 6 transistors and be difficult to make because of a memory cell.
Even after outage, still keep the nonvolatile memory of memory content to comprise: recordable memory, wherein data can rewrite many times; The Write-once memory, wherein data can only be write once by the user; And mask rom, wherein data content is determined when making memory and after this can not rewritten.As recordable memory, EPROM, flash memory, ferroelectric storage etc. are arranged.EPROM allows the easy of data to write, and the unit cost of each is relatively low, although need special-purpose programming device and be used to write the eraser of wiping.Flash memory and ferroelectric storage permission rewrite, have than the short access time on employed substrate and be low power consumption, although the manufacturing step of floating gate and ferroelectric layer need increase the unit cost of each.
Each memory cell of Write-once memory is made of by other device that heat or light change fuse, anti-fuse, cross pointer diode, OLED (Organic Light Emitting Diode), bistable liquid crystal cell and its state.Generally speaking, one of memory device two states by selecting each memory cell are stored data.The Write-once memory device manufactures all memory cell and has first state, and has only by the write operation designated memory locations and just can become second state.Change from first state to second state is irreversible, and the memory cell that is changed is irrecoverable.
The temperature and the material of the manufacturing step of Write-once memory are restricted, thereby it does not form on silicon substrate in many situations.Promptly, the Write-once memory is to make with (hereinafter being referred to as other functional circuit, to distinguish mutually with the Write-once memory) diverse modes such as the CPU (hereinafter being called CPU) that forms on silicon substrate usually, arithmetical circuit, rectification circuit, control circuits.For example, anti-fuse Write-once memory has wiring, antifuse layer and the control element (referring to patent documentation 1) that forms on plastics or metal substrate.Low-cost, big capacity, low-power consumption and shorter access time have been realized with the memory device that this mode is made.Yet, having in the situation of semiconductor device of certain function in formation, memory is not by working independently and essential other functional circuit.Therefore, be necessary to be individually formed memory and other functional circuit such as the Write-once memory.
In recent years, the IC mark is well-known as an example of semiconductor device, and wherein memory and other functional circuit are integrated on the same silicon substrate.The IC mark comprises the memory such as SRAM, mask rom, flash memory and ferroelectric storage.To be data content just determine when making memory mask rom and the memory that can not be rewritten by IC mark user.In addition, an item number is according to determining by a photomask; Therefore, mask rom need with the as many photomask of data type.Thereby mask rom is for cost reason and impracticable.
Flash memory and ferroelectric storage need other step to come to form floating gate and ferroelectric layer in gate insulating film.Simultaneously, all circuit except that memory can obtain by the CMOS manufacturing step in the IC mark.
In recent years, the technology that is used for forming thin-film transistor (hereinafter being called TFT) on dielectric substrate has obtained effective exploitation, to make the display device such as LCD and EL display.For example, drive circuit and the pixel portion that is used for display image uses TFT to form on same substrate.Because dielectric substrate is not capacitively coupled to wiring, so can realize the high-speed cruising of circuit.Therefore, proposition use TFT forms various functional circuits and the memory circuitry such as arithmetical circuit.Another advantage that forms functional circuit on dielectric substrate is to save cost.Glass substrate is with quite cheap plastic is compared silicon substrate.In addition, use that to have more large-area dielectric substrate be possible than being subject to silicon substrate than small size.Thereby, increasing that the quantity of the product of making on the dielectric substrate is made on than silicon substrate, thereby cause as cheap as dirt semiconductor device.
The memory device that uses the TFT manufacturing technology to form comprises mask rom, SRAM and flash memory.The SRAM that comprises TFT can easily form on the substrate identical with other functional circuit, although it is owing to volatibility is restricted on using.Mask rom is impracticable because of different pieces of information is needed different photomasks.Flash memory need be used to form other step of floating gate, although other functional circuit such as arithmetical circuit also can form by the TFT manufacturing step on dielectric substrate.
As mentioned above, the present invention makes according to two kinds of technology: be used to form the technology of memory device and be used for forming on such as the dielectric substrate of glass substrate or dielectric substrate the technology of circuit.
[patent documentation 1]
The open No.2003-36684 of Japan Patent.
Summary of the invention
No matter semiconductor integrated circuit still is being to form on dielectric substrate on the silicon substrate, forming nonvolatile memory with routine techniques on same substrate is difficult with other functional circuit.Yet, when forming separately, memory and other functional circuit need externally be connected them when obtaining a device, and cause the product size of devices to increase.In addition, the manufacturing as at least two circuit of memory and other functional circuit is expensive.Even when memory and other functional circuit can form on same substrate with flash memory and ferroelectric storage, also need other step to form memory.When making semiconductor device, that the increasing of manufacturing step causes is expensive, the specification of limits product and reduced productivity ratio.
In other words, almost all need particular step with all memory devices of routine techniques manufacturing.Therefore, they can not form on same substrate with other functional circuit, even perhaps form on same substrate with other functional circuit, they also need to be different from other step of TFT manufacturing step.This problem causes having in manufacturing the semiconductor device of function, all can cause the extra cost of memory during such as the IC mark.
According to aforementioned content, the invention provides the manufacture method of the Write-once memory that can form by the TFT manufacturing step that is similar to other functional circuit that on dielectric substrate, forms.In addition, the invention provides and be easy to use and cheap memory device,, still keep product specification and productivity ratio on same substrate even simultaneously when memory and other functional circuit form.
Consider foregoing problems, the invention provides a kind of memory device, it has the Write-once memory function by changing going up the semiconductive thin film that forms such as the dielectric substrate of glass substrate and plastic or substrate (hereinafter being referred to as dielectric substrate) with insulating surface.
According to a kind of pattern of the present invention, memory device is included in the memory cell that forms on the insulating surface.This memory cell comprises semiconductive thin film with the zone between two extrinsic regions and described two extrinsic regions, is formed on the described zone and has the grid that is clipped in dielectric film wherein and two wiring that connect respective impurity regions.By described grid and described two wiring one of at least between the described semiconductive thin film that applies between two wiring that voltage will be clipped in described memory cell change into state of insulation.
According to another kind of pattern of the present invention, memory device is included in first memory cell and second memory cell that forms on the insulating surface.Each of first memory cell and second memory cell all comprises the semiconductive thin film with the zone between two extrinsic regions and described two extrinsic regions, two wiring that are formed on the described zone and have the grid that is clipped in dielectric film wherein and be connected to respective impurity regions.By described grid and described two wiring one of at least between the semiconductive thin film that applies between two wiring that voltage will be clipped in described second memory cell change into state of insulation.First memory cell comprises initial condition.
According to another pattern of the present invention, memory device is included in the memory cell that forms on the insulating surface.This memory cell comprises semiconductive thin film with one or two extrinsic region, be formed on the described extrinsic region and have the grid that is clipped in dielectric film wherein and be connected to two wiring of respective impurity regions or be connected to two wiring of a described extrinsic region.By described grid and described two wiring one of at least between the described semiconductive thin film that applies between two wiring that voltage will be clipped in described memory cell change into state of insulation.
According to another kind of pattern of the present invention, memory device is included in first memory cell and second memory cell that forms on the insulating surface.Each of first memory cell and second memory cell all comprises semiconductive thin film with one or two extrinsic region, be formed on the described extrinsic region and have the grid that is clipped in dielectric film wherein and be connected two wiring of respective impurity regions or be connected to two wiring of a described extrinsic region.By described grid and described two wiring one of at least between the semiconductive thin film that applies between two wiring that voltage will be clipped in described second memory cell change into state of insulation.First memory cell has initial condition.According to the present invention, memory device can comprise one or more grids.
In addition, the present invention also provides a kind of manufacture method of only writing memory device once, may further comprise the steps: form island shape semiconductor film on insulating surface; On described island shape semiconductor film, form grid insulating film; On described grid insulating film, form grid; Doped N-type impurity element and described grid form N type high concentration impurity thus as mask in described island shape semiconductor film; On described grid insulating film and described grid, form interlayer film; In described interlayer film be connected in the wiring of described high concentration impurity and form contact hole, form memory cell thus, and voltage is put between the wiring of described grid and described memory cell, the channel region with described island shape semiconductor film becomes state of insulation thus.
According to aforementioned structure, the Write-once memory can form on dielectric substrate by the TFT manufacturing step.That is, memory device of the present invention can form by the TFT manufacturing step similar to form other functional circuit on dielectric substrate, and this can suppress the increase of the extra cost that causes because of the additional manufacturing step of memory.In addition, because memory and other functional circuit can form by same steps as, so memory limits product specification and do not reduce productivity ratio not.
Glass substrate is compared quite cheap with plastic with silicon substrate.In addition, use that to have more large-area dielectric substrate be possible than being subject to silicon substrate than small size.Thereby, increasing that the quantity of the product of making on the dielectric substrate is made on than silicon substrate, thereby cause as cheap as dirt semiconductor device.
According to the present invention, thereby the Write-once memory forms by the TFT manufacturing step and is easy to use, and cheap memory device can be provided, simultaneously even also keep product specification and productivity ratio when memory and other functional circuit form on same substrate.
Description of drawings
Figure 1A and 1B are the schematic diagrames that the operation of memory cell in the memory device of the present invention is shown.
Fig. 2 is the diagrammatic sketch that an example of memory cell array is shown.
Fig. 3 A is the vertical view and the cross sectional view of resistor to 3E.
Fig. 4 is the diagrammatic sketch that an example of memory cell array is shown.
Fig. 5 A is the diagrammatic sketch that the manufacturing step of TFT is shown to 5E.
Fig. 6 A is the diagrammatic sketch that the manufacturing step of TFT is shown to 6D.
Fig. 7 A and 7B are the diagrammatic sketch that the manufacturing step of TFT is shown.
Fig. 8 A and 8B are the diagrammatic sketch that the application of memory device of the present invention is shown respectively.
Fig. 9 A is the diagrammatic sketch that an example of memory cell in the memory device of the present invention is shown respectively to 9E.
Figure 10 A and 10B illustrate TFT of the present invention at the photo that applies the voltage front and back respectively.
Embodiment
Although by each execution mode and embodiment the present invention is described, be appreciated that various variations and change it will be apparent to those skilled in the art that with reference to accompanying drawing.Therefore, unless these variations and change deviate from scope of the present invention, they should be interpreted as being included in wherein.Notice that in institute's drawings attached, same components or the assembly with identical function are marked by same numeral, and omit its description.
[execution mode 1]
When required higher voltage was applied between one of at least (the comprising high concentration impurity) of the grid that is formed at the TFT on the dielectric substrate and two extrinsic regions than the normal running of TFT, the channel region of TFT was insulated.This operates in shown in Figure 1A and the 1B, and Figure 1A and 1B are that TFT is respectively before applying voltage and viewgraph of cross-section afterwards.For example, the TFT shown in Figure 1A has at the semiconductive thin film 102 that forms on the dielectric substrate 101, grid insulating film 105 and the grid on grid insulating film 105 106 on the semiconductive thin film 102.Semiconductive thin film 102 comprises two high concentration impurity 103 and channel region 104.Figure 1B illustrates and applies voltage TFT afterwards.In this TFT, the channel region 104 of semiconductive thin film 102 is modified at least, and insulating regions 108 forms under grid 106.Then, grid 106 and two high concentration impurity 103 are insulated from each other.Insulating regions 108 shown in Figure 1B is typical cases, and in fact it can have each shape.
For example, among the TFT that on glass substrate, forms, its channel length (hereafter is L) is that 4 μ m, channel width (hereafter is W) are that the thickness (hereafter is GI) of 4 μ m and grid insulating film is 20nm, the voltage of 25V be applied to grid and two high concentration impurity one of at least between reach 500 μ s.Then, the channel region of TFT is insulated, and grid and two high concentration impurity are insulated from each other.TFT is applying practical photograph before and after the voltage shown in Figure 10 A and 10B.Figure 10 A is the photo of TFT before applying voltage, and Figure 10 B is the picture of TFT after applying voltage, and this is to see from the reverse side of glass substrate.
Change in this specification is represented to become state of insulation as Figure 10 A visible at least one channel region in Figure 10 B because putting on the voltage of TFT particularly.Much less, apply situation by changing voltage, even TFT has and different size shown in Figure 10 A and the 10B, at least one channel region of TFT also can be insulated.Notice that state of insulation is represented the state of non-conducting electricity and heat.
Use this mode, when than TFT normal running required higher voltage be applied to be formed at grid and two extrinsic regions one of at least (be high concentration impurity in this execution mode) between the time, electric current flows through grid insulating film.This insulation film is made by the high resistance material in many situations, and produces heat when electric current flows through wherein.When producing big calorimetric among the TFT on being formed at dielectric substrate, heat can not be overflowed because of the low thermal conductiv-ity of dielectric substrate, thereby grid insulating film or semiconductive thin film can burn out.As a result, grid and two high concentration impurity can be insulated from each other.On the other hand, in the transistor that forms on having the silicon substrate of high thermal conductivity, the heat that is produced when electric current flows through grid insulating film can not burn out insulation film and silicon substrate.
Experiment in according to the present invention, when voltage put on grid and two high concentration impurity one of at least between the time, channel region be no less than this time 97% on become state of insulation, grid and two high concentration impurity are insulated from each other thus, promptly they enter non-conduction condition.Detect defective element in all the other of this time on 3%, wherein channel region after applying voltage as resistor and three terminals conduct each other.Defective element can cause because of the dust in semiconductive thin film or the insulation film.Therefore, the improvement accuracy allowable defect element of the TFT of manufacturing reduces further.Being created in when TFT has double-grid structure or provides redundant circuit in addition of defective element also can be inhibited.
As another defective, can conduct each other as two in three terminals of grid and two wiring linking to each other with extrinsic region.Can cause by writing fashionable voltage that applies and dust such as the defective of conducting between three terminals or two terminals.Therefore, the quantity of defective element can write voltage and the voltage application time reduces by optimization.
Memory device is stored data when one of two states of memory cell selecting.Memory device of the present invention can be when selecting one of two states as the TFT of memory cell the storage data: no matter the channel region of TFT is in initial condition, or state of insulation.In the Write-once memory of Zhi Zaoing, the TFT that was in initial condition before applying voltage has state ' 1 ' in the present invention, and comprises by applying the TFT that voltage becomes the channel region of state of insulation having state ' 0 '.This relation between the state ' 0 ' and ' 1 ' and the state of TFT are not limited to this, so use although be for convenience's sake in this manual.
Fig. 2 is the circuit diagram that 4 memory cell arrays of a memory device example of the present invention are shown.This memory cell array comprises two word lines 201, two bit lines 202, two source lines 204 and four TFT206 to 209.Word line 201, bit line 202 and source line 204 are denoted as W0, W1, B0, B1, S0 and S1 respectively.When 25V or higher voltage be applied in grid and two extrinsic regions one of at least between when reaching 500 μ s, as mentioned above, each channel region of TFT206 to 209 becomes state of insulation.
What at first describe is to be used for a circuit operation example writing TFT206 with ' 0 '.Write operation can be by voltage being put on TFT 206 grid and two extrinsic regions one of at least between carry out.For example, the voltage of 25V is applied in W0, and the voltage of 0V is applied in B0 and S0 reaches 500 μ s.At this moment, be necessary to determine the voltage of W1, B1 and S1, thereby can be applied on other TFT ' 0 '.For example, the voltage of 0V is applied in W1, and the voltage of 10V is applied in B1 and S1.By applying these voltage, the voltage of 25V put on the grid of TFT 206 and two extrinsic regions one of at least between, the channel region of TFT 206 can be insulated thus.
The operation of other TFT is briefly described in the time of can writing TFT 206 to general ' 0 '.Because the voltage of 25V puts on W0, and the voltage of 10V puts on B1 and S1, thus the voltage of 15V put on the grid of TFT 207 and two extrinsic regions one of at least between.Yet ' 0 ' is not written into TFT 207, because 25V or higher voltage do not apply on it.Similarly, ' 0 ' is not written into TFT 208, because 0V voltage puts on W1, B0 and S0.The voltage of 0V is applied in W1, and simultaneously the voltage of 10V is applied in B0 and S0, so the voltage of 10V puts between the grid and semiconductive thin film of TFT 209, although ' 0 ' does not write wherein.Notice that the voltage that applies only is example herein, and by at random determining the voltage of each word line 201, bit line 202 and source line 204, signal only can write selected TFT.
Described below is to be used for a circuit operation example writing TFT 206 with ' 1 '.When will ' 1 ' writing TFT 206, do not have voltage be applied in grid and two extrinsic regions one of at least between, keep TFT 206 to be in initial condition simultaneously.Therefore, for example all word lines 201, bit line 202 and source line 204 all can have identical voltage, thereby do not write TFT 206 with ' 0 '.This only is an example, and the electromotive force of each word line 201, bit line 202 and source line 204 all can be determined by the method for control circuit.
The read operation of TFT 206 is then described.Read operation determines that TFT 206 is in state ' 1 ', promptly is in initial condition not applying under the voltage condition, still is in state ' 0 ', promptly becomes state of insulation.Thereby, threshold voltage or more high voltage be applied on the grid of TFT 206, whether between two high concentration impurity, flow to determine electric current.At first, before reading, B0 is pre-charged to 5V.Then, the voltage of 5V and 0V is put on W0 and S0 respectively, to read the electromotive force of B0.At this moment, thus be necessary that the voltage of determining W1, B1 and S1 do not select other TFT.For example, the voltage of 0V is applied in W1 and S1, not read the electromotive force of B1.When TFT 206 under not applying voltage condition was in the state ' 1 ', the conduction of two extrinsic regions was so and be applied in B0 because the voltage of 5V is applied in the voltage that W0 goes up 0V.On the other hand, when TFT 206 has been applied in voltage and gets the hang of ' 0 ' time, so because B0 and S0 B0 insulated from each other remains 5V.The read operation of TFT 206 thereby can carry out by the variation that applies the voltage that is equal to or higher than threshold value to W0 and read in the B0 electromotive force.
Concise and to the point description is carried out in the operation of other TFT during to the read operation of TFT 206.Because do not select to read B1, so read operation does not relate to TFT 207 and TFT 209.TFT 208 does not change the electromotive force of bit line, because W0 has the voltage of 0V.Therefore, other TFT does not influence the read operation of TFT 206.
As mentioned above, in the present embodiment, memory cell has two states: on off state and state of insulation.Thereby memory cell can only be made of a TFT, thereby causes the area of memory cell array to reduce, and memory capacity increases.
[execution mode 2]
In memory device of the present invention, high concentration impurities can be added on the whole surface of the semiconductive thin film of TFT, as memory cell.On the contrary, impurity can add arbitrary part of semiconductive thin film to, and two wiring can be connected wherein; Yet when at random forming extrinsic region, element is not as transistor.Simultaneously, when high concentration impurities is added on the whole surface of semiconductive thin film, by electrode and two wiring one of at least on apply voltage and make whole three terminals insulated from each other.
What describe in the present embodiment is a such example: an extrinsic region (being high concentration impurity in the present embodiment) forms on the semiconductive thin film on the dielectric substrate, and two wiring is connected to semiconductive thin film, and one of them electrode holder betwixt.Fig. 3 A and 3C are the vertical views with element of this structure.Fig. 3 B, 3D and 3E are the viewgraph of cross-section with element of this structure.Fig. 3 A and 3B illustrate a kind of normal TFT, wherein add high concentration impurities to semiconductive thin film before forming grid on the insulation film.Fig. 3 C, 3D and 3E illustrate the TFT that is included in the hole 307 that has any width in the grid, and wherein high concentration impurities is added on the semiconductive thin film after forming electrode.The width in hole 307 should be defined as: make two wiring insulation when applying voltage between electrode and semiconductive thin film.Element shown in Fig. 3 A and the 3C all makes the high concentration impurity conduction of two wiring by semiconductive thin film, thereby these elements are called as resistor element in this manual, to distinguish mutually with TFT.
In each resistor element shown in the 3E, semiconductive thin film 301 forms on dielectric substrate 303 at Fig. 3 A, and insulation film 305 forms on semiconductive thin film 301, and electrode 302 forms on insulation film 305.Article two, wiring 306 is connected to the high concentration impurity 304 in the semiconductive thin film 301.High concentration impurity 304 in the semiconductive thin film 301 can form anywhere with the wiring 306 that is connected to semiconductive thin film 301, as long as electrode 302 forms between two wiring 306.The form of electrode 302 also can determine at random that shown in Fig. 3 C the hole 307 that wherein has any width forms in grid.In addition, the form of resistor element also can at random be determined, and Fig. 3 A only illustrates example to 3E.
For example, it is that 4 μ m, W are that 4 μ m and GI are 20nm that resistor element as shown in Figure 3A is similar to execution mode 1:L, the voltage of 25V be applied to grid and two wiring one of at least between reach 500 μ s.Then, electrode and two wiring are insulated from each other.Much less, even have with different when big or small shown in this paper when element, apply state by changing voltage, three terminals also can be insulated from each other.In the present embodiment, the Write-once memory uses this structure to make.
Fig. 4 is the circuit diagram of 4 memory cell arrays that an example of present embodiment is shown.This memory cell array comprises that two word lines 31, two bit lines 32, two select control line 33, four resistor elements 34 and four to select transistors 35.Word line 31, bit line 32 and selection control line 33 are denoted as W0, W1, B0, B1, W ' 0 and W ' 1 respectively.Memory cell 22 is selected by W0 and B0, and memory cell 24 is selected by W0 and B1, and memory cell 42 is selected by W1 and B0, and memory cell 44 is selected by W1 and B1.Be similar to the example shown in Fig. 3 A and the 3B, when 25V or higher voltage are put on grid and two extrinsic regions one of at least between the time, insulated from each other between the electrode of resistor element 34 and two extrinsic regions.Notice that extrinsic region can form, thereby voltage is applied between electrode and the semiconductive thin film in the present embodiment on the whole surface of semiconductive thin film.
What at first describe is a circuit operation example that is used for ' 0 ' write storage unit 22.Write operation can be carried out by voltage is put between electrode and the insulation film, promptly be connected to the resistor element 34 in the memory cell 22 semiconductive thin film two wiring one of at least.For example, the voltage of 25V is applied in W0, and the voltage of 0V is applied in B0 and W ' 0 reaches 500 μ s.At this moment, must determine the voltage of W1, B1 and W ' 1, thereby can not be applied on other resistor element ' 0 '.For example, the voltage of 0V is applied in W1 and W ' 1, and the voltage of 10V is applied in B1.By applying these voltage, the voltage of 25V puts between the electrode and semiconductive thin film of resistor element 34 in the memory cell 22, and electrode and two wiring can be insulated from each other thus.The voltage that applies shown in this article only is example, but the wiring operation also can be carried out by other situation.
Can the operation of other memory cell be briefly described to ' 0 ' write storage unit 22 time.Because the voltage of 25V puts on W0, the voltage of 10V puts on B1, and the voltage of 0V puts on W ' 0, so the voltage of 15V puts between the electrode and insulation film of memory cell 24.Yet ' 0 ' is not written into memory cell 24, because 25V or higher voltage do not apply on it.Similarly, ' 0 ' is not written into memory cell 42, because 0V voltage puts on W1, W ' 1 and B0.The voltage of 0V is applied in W1 and W ' 1, and simultaneously the voltage of 10V is applied in B0, so the voltage of 10V puts between the electrode and semiconductive thin film of memory cell 44, although ' 0 ' does not write wherein.Like this, by at random determining the voltage of word line 31, bit line 32 and selection control line 33, ' 0 ' only can write selected memory cell.
Described below is a circuit operation example that is used for ' 1 ' write storage unit 22.When with ' 1 ' write storage unit 22, there is not voltage to be applied between the electrode and semiconductive thin film of resistor element 34, keep memory cell 22 to be in initial condition simultaneously.Therefore, for example all word lines 31, bit line 32 and selection control line 33 all can have the identical voltage such as 0V, thereby not with ' 0 ' write storage unit 22.This only is an example, and the electromotive force of each word line 31, bit line 32 and selection control line 33 all can at random be determined by the method for control circuit.
The read operation of memory cell 22 is then described.Read operation determines that the resistor element 34 in the memory cell 22 is to be in state ' 1 ', promptly be in initial condition not applying under the voltage condition, or resistor element 34 has been applied in voltage and has been in state ' 0 ', promptly becomes state of insulation.Thereby, threshold voltage or more high voltage be applied on the grid of selection transistor 35 of memory cell 22, whether be grounding to two high concentration impurity selecting transistor 35 to determine B0.At first, before reading, B0 is pre-charged to 5V.Then, the voltage of 5V is applied in W ' 0.At this moment, must determine W ' thus 1 and the voltage of B1 do not select other transistor.W0 and W1 only are used for write operation, and are unwanted when read operation.For example, the voltage of 0V is applied in W ' 1, not read the electromotive force of B1.When the resistor element in the memory cell 22 under not applying voltage condition 34 is in the state ' 1 ', when being initial condition, the voltage of B0 ground connection and 0V is applied in B0.On the other hand, when the resistor element in the memory cell 22 34 has been applied in voltage and has got the hang of ' 0 ' time, so because B0 and ground insulation in addition when the voltage of 5V is applied in W0 B0 still remain 5V.The read operation of memory cell 22 thereby can carry out by the variation that applies voltage to W ' 0 and read in the B0 electromotive force.
Concise and to the point description is carried out in the operation of other memory cell during to the read operation of memory cell 22.Because do not select to read B1, so read operation does not relate to memory cell 24 and memory cell 44.Memory cell 42 does not change the electromotive force of bit line, because W ' 0 has the voltage of 0V.Therefore, other memory cell does not influence the read operation of memory cell 22.
In the present embodiment, each memory cell comprises two elements, and this has increased the area of memory cell array.Yet in this case, the element (for example decoder that links to each other with W0 or W1) of writing fashionable use high pressure uses when reading the element (for example decoder that links to each other with W ' 0 or W ' 1) of low pressure to separate and forms.When using high pressure, need TFT to have bigger L and bear high pressure.Yet the TFT with big L is unsuitable for high speed operation, thereby uses the TFT of low pressure to have less L usually.Therefore, it is very favourable high speed operation and easy operation control being formed element respectively.In the present embodiment, TFT can replace resistor element 34 to be used, and memory TFT can separate formation with selection TFT in memory cell.
[embodiment]
[embodiment 1]
In the present embodiment, to 5E, Fig. 6 A to 6D and Fig. 7 A and 7B, the manufacture method of TFT on the glass substrate is described particularly with reference to Fig. 5 A.Viewgraph of cross-section with reference to N channel TFT and P channel TFT is described.
At first, on substrate 500, form peel ply 501 (Fig. 5 A).In the present embodiment, thickness be the a-Si film (noncrystalline silicon film) of 50nm by low pressure chemical vapor deposition at glass substrate (for example product of Corning Incorporated-1737 substrate).For substrate 500, can adopt quartz substrate, by the substrate of making such as insulating material such as aluminium oxide, silicon wafer substrate, the heat treatment temperature in the subsequent step is had enough stable on heating plastic and glass substrate.Peel ply 501 preferably forms by mainly comprising such as polysilicon, monocrystalline silicon and SAS (being also referred to as half amorphous silicon of microcrystal silicon) and the silicon of amorphous silicon, although the present invention is not limited to this.Peel ply 501 can be by plasma CVD or sputter and low pressure chemical vapor deposition formation.Also can adopt with film such as the doping impurity of phosphorus.The thickness of peel ply 501 is required to be 50 to 60nm, although it can be 30 to 50nm in the situation that adopts SAS.
Then, diaphragm 502 (being also referred to as basement membrane or insulating basement membrane) forms (Fig. 5 A) on peel ply 501.In the present embodiment; diaphragm 502 has three-decker; wherein thickness is that the SiON film that the SiON film of 100nm, SiNO film that thickness is 50nm and thickness are 100nm piles up from substrate side in this order, although the material of these layers, thickness and quantity are not limited in this.For example, on bottom,, be the heat resistanceheat resistant resin of the siloxanes of 0.5 to 3 μ m but can form such as thickness by spin coating, slit coating, droplet discharging etc. without the SiON film.Perhaps, can adopt silicon nitride film (SiN, Si
3N
4Deng).The thickness of each layer is preferably in the scope of 0.05 to 3 μ m, and can select in this scope as required.Silicon oxide film can pass through hot CVD, plasma CVD, air pressure CVD, bias voltage ECRCVD etc. and use SiH
4And O
2, TEOS (tetraethyl orthosilicate) and O
2Deng mist form.Silicon nitride film can use SiH by plasma CVD usually
4And NH
3Mist form.SiON film or SiNO film can use SiH by plasma CVD usually
4And N
2The mist of O forms.
Subsequently, TFT forms on diaphragm 502.Note, can form other film active element and thin film diode and TFT such as organic tft.In order to form TFT, at first on diaphragm 502, form island shape semiconductor film 503 (Fig. 5 B).Island shape semiconductor film 503 is to use amorphous semiconductor, crystalline semiconductor or comprises mainly that half amorphous semiconductor of silicon, SiGe (SiGe) etc. forms.Notice that if the material that mainly comprises such as the silicon of a-Si is used for peel ply 501 and island shape semiconductor film 503, then contacted with it diaphragm 502 can use SiO according to viscosity
xN
yForm.In the present embodiment, having formed thickness is the amorphous silicon membrane of 70nm, and handle with the solution that comprises nickel on its surface.Thermal crystalline is carried out on 500 to 750 ℃ of temperature, thereby can obtain crystalline silicon semiconductor film.Then, its degree of crystallinity can be improved by laser crystallization.Notice that film can wait by plasma CVD, sputter, LPCVD and form.As a kind of method for crystallising, can adopt the thermal crystalline of laser crystallization, thermal crystalline or the catalyst (Fe, Ru, Rh, Pd, Os, Ir, Pt, Cu, Au etc.) of use except nickel, perhaps can repeatedly alternately carry out these methods.
Perhaps, the semiconductive thin film with non-crystal structure can pass through the continuous wave laser crystallization.In order during crystallization, to obtain to have crystal than coarsegrain, can use can continuous wave solid-state laser, and preferably apply twice of first-harmonic to four-time harmonic (crystallization is called CWLC in this case).Usually, apply Nd:YVO
4Laser (first-harmonic: two subharmonic (532nm) 1064nm) or triple-frequency harmonics (355nm).When using continuous wave laser, from being output as the continuous wave YVO of 10W
4The laser that laser sends converts harmonic wave to by nonlinear optical element.Also have a kind of passing through with YVO
4Crystal or GdVO
4Crystal and nonlinear optical element are inserted the method that resonator is launched harmonic wave.Then, preferably on irradiating surface, form rectangle or oval-shaped laser, with irradiating object with optical system.In this case, need about 0.01 to 100MW/cm
2(preferably 0.1 arrive 10MW/cm
2) energy density.Then, the most handy laser radiation semiconductive thin film moves relative to laser with about speed of 10 to 2000cm/s simultaneously.
When using pulse laser, service band is tens to hundreds of Hz pulse laser usually, has much higher 10MHz or the pulse laser of high oscillation frequency (crystallization is called as MHzLC in this case) more although also can use.It is said, in the time that will spend tens to hundreds of ns with full solidification semiconductive thin film after the pulsed laser irradiation semiconductive thin film.When pulse laser has 10MHz or higher frequency of oscillation, be possible shining next pulse laser before the curing semiconductor film, after by last laser fusion.Therefore, different with the situation of conventional pulse laser, the interface between solid phase and the liquid phase can be moved in semiconductive thin film continuously, thereby can form the semiconductive thin film that crystal grain is grown continuously along the scanning direction.More specifically, may form the set of crystal grain, its width on the scanning direction is 10 to 30 μ m, and width is about 1 to 5 μ m on the direction vertical with the scanning direction.At least on the channel direction of TFT, has the seldom semiconductive thin film of grain boundary by being formed on this single grain of extending on the scanning direction, can forming than length.Note, when using siloxanes as heat-resisting organic resin partly to form diaphragm 502, can when above-mentioned crystallization, prevent heat leak, thereby produce effective crystallization from semiconductive thin film.
The crystal silicon semiconductor film forms by abovementioned steps.Its crystal preferably aligns with source electrode, raceway groove and drain directions.The thickness of its crystal layer preferably is 20 to 200nm (being generally 40 to 170nm, more preferably is 50 to 150nm).Subsequently, the amorphous silicon membrane that is used to absorb metallic catalyst forms on semiconductive thin film, and sull is clipped in therebetween, and heat treatment is carried out so that air-breathing on 500 to 750 ℃ temperature.In addition, in order to control the threshold value as the TFT element, the boron ion is with 10
13/ cm
2Dosage be ejected into the crystal silicon semiconductor film.Then, carry out etching, to form island shape semiconductor film 503 with resist as mask.Perhaps, by using disilane (Si
2H
6) and fluoridize germanium (GeF
4) source gas directly form polycrystalline semiconductor thin film by LPCVD (low pressure chemical vapor deposition), can obtain crystalline semiconductor film.The flow velocity of gas makes Si
2H
6/ GeF
4=20/0.9, the temperature that is used to form film is 400 to 500 ℃, and He or Ar are as carrier gas, although the present invention is not limited to these conditions.
TFT, particularly its channel region are preferably used 1x10
19To 1x10
22Cm
-3, more preferably use 1x10
19To 5x10
20Cm
-3Hydrogen or halogen add.In the situation of using SAS, the most handy 1x10
19To 2x10
21Cm
-3Hydrogen or halogen add.In arbitrary situation, the amount of hydrogen or halogen need be bigger than the amount that silicon single crystal body comprised that is used for IC chip etc.In view of the above, the local cracks that can produce on the TFT part can stop by hydrogen or halogen.
Then, gate insulating film 504 forms (Fig. 5 B) on island shape semiconductor film 503.This gate insulating film 504 preferably forms method by single thin film that comprises silicon nitride, silica, silicon oxynitride or silicon oxynitride or stack layer film by the film such as plasma CVD and sputter and forms.In the situation of stack layer, can adopt for example three-decker, wherein silicon oxide film, silicon nitride film and silicon oxide film pile up from substrate side in this order.
Subsequently, form grid 505 (Fig. 5 C).In this embodiment, Si and W (tungsten) pile up by sputter and with as resist 506 etchings of mask, to form grid 505.Much less, the material of grid 505, structure and formation method are not limited to these, and can suitably select.For example, can adopt Si and the stacked structure of NiSi (nickle silicide) or the stacked structure of TaN (tantalum nitride) and W (tungsten) of using N type doping impurity.Perhaps, grid 505 can adopt any conductive material to form individual layer.Can use SiO
xDeng mask replace Etching mask.In this case, also need be such as SiO
xWith the graphical step of the mask (being called as hard mask) of SiON such as the mask of making by inorganic material, compare mask film with resist simultaneously and when etching, reduce lessly, can form grid layer thus with required width.Perhaps, grid 505 can be under the situation of not using resist 506 discharges optionally by droplet and forms.For conductive material, the function that can be depending on conducting membranes is selected various types of materials.When grid and antenna form simultaneously, can consider that its function selects material.As the etching gas that is used for etching grid, adopt CF at this
4, Cl
2And O
2Mist or Cl
2Gas is although the present invention is not limited to this.
Subsequently, resist 509 is formed the several portions of covering as P channel TFT 507.N type impurity element 510 (being generally P (phosphorus) or arsenic (As)) is doped to the island shape semiconductor film of N channel TFT 508 low concentration, and grid is as mask (the first doping step, Fig. 5 D).The first doping step is being 1x10 such as dosage
13To 6x10
13/ cm
2And accelerating voltage is to carry out under 50 to 70keV the condition, although the present invention is not limited in these conditions.In the first doping step, on whole gate insulating film 504, mix with the extrinsic region 511 that forms a pair of low concentration comprehensively.Notice that the first doping step can be carried out whole surface under the situation that covers the P channel TFT without resist 509.
After resist 509 is by removals such as ashing, form another resist 512 to cover N channel TFT zone.P type impurity element 513 (being generally B (boron)) is doped in to high concentration the island shape semiconductor film of P channel TFT 507, and wherein grid is as mask (the second doping step, Fig. 5 E).This second doping step is being 1x10 such as dosage
13To 3x10
16/ cm
2And accelerating voltage is to carry out under 20 to 40keV the condition.In this second doping step, on whole gate insulating film 504, mix to form a pair of P type high concentration impurity 514 comprehensively.
After resist 512 is by removals such as ashing, on the whole surface of substrate, form dielectric film 601 (Fig. 6 A).In the present embodiment, thickness is the SiO of 100nm
2Film forms by plasma CVD.Cover the whole surface of substrates then with resist 602, and resist 602, dielectric film 601 and gate insulating film 504 remove by dark etching, with from alignment thereof formation sidewall 603 (Fig. 6 B).As a kind of etching gas, adopt CHF
3Mist with He.Notice that if also formed dielectric film 601 at the reverse side of substrate, then the dielectric film of reverse side is with etchant 602 etchings and removal (this step is called reverse side and handles) as mask.
The formation method of sidewall 603 is not limited to preceding method.For example, also can adopt method shown in Fig. 7 A and 7B.Fig. 7 A illustrates the dielectric film 701 with two or more layers of stacked structure.This dielectric film 701 for example has, and thickness is the SiON (silicon oxynitride) of 100nm and the double-decker of the LTO (low temperature oxide) that thickness is 200nm.In the present embodiment, the SiON film forms by plasma CVD, and the LTO film uses SiO
2Film forms by low pressure chemical vapor deposition.Then, carry out dark etching, thereby form L shaped and sidewall 603 arc with resist 602 as mask.Fig. 7 B illustrates and carries out etching is not removed dielectric film 702 by dark etching situation.Dielectric film 702 in this case can be formed by single layer or stack layer.When at subsequent step middle and high concentration ground doped N-type impurity, sidewall 603 is used as mask to form low concentration impurity zone or non-doping offset area for 603 times at sidewall.In the arbitrary aforementioned formation method of sidewall, dark etched condition can be depending on the width of the low concentration impurity zone that will form or offset area and changes.
In semiconductor device of the present invention, memory cell is operate as normal under the situation of no sidewall.Therefore, after Fig. 6 B neutralization, two TFT in left side have sidewall, and two TFT on right side do not have sidewall.
Subsequently, form another resist 604 so that cover P channel TFT zone.N type extrinsic region 605 (being generally P or As) is mixed by high concentration ground, and its grid 505 and sidewall 603 are as mask (the 3rd doping step, Fig. 6 C).The 3rd doping step is being 1x10 such as dosage
13To 5x10
15/ cm
2And accelerating voltage is to carry out under 60 to 100keV the condition.In the 3rd doping step, form a pair of N type high concentration impurity 606.After resist 604 is by removals such as ashing, can carry out the thermal activation of extrinsic region.For example, forming thickness is the SiON film of 50nm, the heat treatment that to carry out temperature then in nitrogen atmosphere be 550 ℃, reach 4 hours.Perhaps, also may form the hydrogeneous SiN that thickness is 100nm
xFilm, and to carry out temperature in nitrogen atmosphere be 410 ℃, the heat treatment that reaches 1 hour.In view of the above, can improve defective in the crystalline semiconductor film.Unsaturated bond energy in the feasible for example crystalline silicon of this step is removed, and is called hydrotreating step.Subsequently, forming thickness is that the SiON film of 600nm is as the lid dielectric film that is used to protect TFT.Notice that above-mentioned hydrotreating step can be carried out after forming this SiON film.In this case, can form SiN continuously thereon
xFilm and SiON film.Like this, insulation film comprises SiON, SiN
xThree layers that pile up from substrate side on TFT in this order with SiON are although this structure and material is not limited in this.Note, be preferably formed as this insulation film, because it also has the function of protection TFT.
Subsequently, on TFT, form interlayer film 607 (Fig. 6 D).For this interlayer film 607, can adopt heat-resisting organic resin such as polyimides, acrylic acid, polyamide and siloxanes.Interlayer film 607 depends on that its material can apply by spin coating, dipping, spraying plating, droplet discharges (ink jet printing, silk screen printing, biasing printing etc.), medical knife, cylinder covers the material machine, curtain coater, blade coating machine wait and form.Perhaps, can adopt inorganic material such as silica, silicon nitride, silicon oxynitride, PSG (phosphosilicate glass), BPSG (phosphorus borosilicate glass) and aluminium oxide.These dielectric films also can pile up to form interlayer film 604.Diaphragm 608 can form on interlayer film 607.As diaphragm 608, can adopt the film that contains such as the carbon of DLC (diamond-like-carbon) and carbonitride (CN), silicon oxide film, silicon nitride film, silicon oxynitride film etc.Diaphragm 608 can pass through formation such as plasma CVD, air pressure plasma.Perhaps, can adopt such as the sensitization of polyimides, acrylic acid, polyamide, resist and benzocyclobutene or non-sensitization inorganic material or such as the heat-resisting organic resin of siloxanes.Inserts can be sneaked into interlayer film 607 or diaphragm 608, so that prevent that these films are because of separating or the crack that the difference of the thermal coefficient of expansion between the conductive material of interlayer film 607 or diaphragm 608 and the wiring that formed afterwards etc. causes.
After forming resist, be etched with the formation contact hole and make wiring 609 form (Fig. 6 D).As the etching gas that is used to form contact hole, adopt CHF
3With the mist of He, although the present invention is not limited to this.Wiring 609 is by sputter and graphically form and have 5 layers of structure, and wherein Ti, TiN, Al-Si, Ti and TiN pile up from substrate side in this order.By Si being sneaked into the Al layer, can prevent from when graphical wiring, in the resist baking, to produce hillock.Can mix about 0.5% Cu and replace Si.When the Al-Si layer is clipped between Ti and the TiN, can further improve hillock resistance.When graphical, preferably adopt the hard mask of aforementioned SiON etc.Notice that the material of wiring and formation method are not limited in this, and also can adopt the previous materials that is used to form grid.
By abovementioned steps, finished semiconductor device with TFT.This semiconductor device comprises IC mark, IC chip, wireless chip etc.Although adopted top gate structure in the present embodiment, also can adopt bottom gate structure (the reverse structure of reporting to the leadship after accomplishing a task).The zone that does not mainly form such as the film active element of TFT comprises insulating basement membrane material, interlayer dielectic and wiring material.This zone preferably occupy entire semiconductor device 50% or more than, more preferably occupy 70 to 95%.Simultaneously, comprise that preferably the island semiconductor zone (island) of the active element of TFT part occupies 1 to 30% of entire semiconductor device, more preferably occupy 5 to 15%.Shown in Fig. 6 D, the diaphragm in this semiconductor device or the thickness of interlayer film need be controlled so as to: the distance (t between the semiconductor layer of TFT and the following diaphragm
Under) can and this semiconductor layer and top interlayer film (if or protect film formed words) between distance (t
Over) identical or substantially the same.By with the middle depositing semiconductor layers of this mode at semiconductor device, can reduce the stress that puts on this semiconductor layer, can prevent to produce the crack thus.
[embodiment 2]
What describe in the present embodiment is in conjunction with an example of the semiconductor device of memory device of the present invention on same substrate.The IC mark is got an example making semiconductor device, and wherein memory and other functional circuit are bonded on the same substrate.Fig. 8 A is the block diagram of IC mark.IC mark 801 comprises RF circuit 802, power circuit 803, command control circuit 804, clock 805, congested control circuit 806, memorizer control circuit 807, memory 808 and antenna 809.These functional circuits form on same dielectric substrate.Notice that antenna 809 can form or be arranged on the outside, and is connected to the terminal that forms on same substrate on same substrate, thus antenna 809 in diagrammatic sketch by dotted line.
In IC mark 801, all circuit except that memory 808 can form by the TFT manufacturing step.When memory device of the present invention was combined in the memory 808, all circuit can form by identical manufacturing step.In the situation that semiconductor device forms on a substrate as shown in this embodiment, improved productivity ratio can form all circuit by identical manufacturing step with cost savings and realize.
The Write-once memory can suitably be applied to the IC mark, since similar to bar code, in case just needn't change the data content of memory after determining.The fail safe that is used for the IC mark of individual recognition and material handling can improve by preventing that data content is rewritten.In addition, the IC mark should be preserved data for prolonged period of time; Therefore, the Write-once memory of carrying out the irreversible operation write data suitably is combined in the IC mark.In addition, if data should write, then can keep available memory as required between use IC mark phase.Like this, by with memory device of the present invention in conjunction with in the IC mark, high security and wieldy product can be provided.
The IC mark is worked with the semiconductor device that forms on dielectric substrate.Memory device of the present invention can be used as the part of device.An example of this situation is shown in Fig. 8 B.Household electrical appliance 810 such as electric cooker and air conditioner comprise CPU 812, memory 811, I/O controller 813 and external equipment 814.The operational data that is incorporated into memory 811 in this electrical equipment and is this electrical equipment just write program ROM wherein before deliver goods.
CPU 812, memory 811 and I/O controller 813 generally form single IC; Yet they can use TFT to form on same dielectric substrate.Even for the part of as shown in this embodiment electrical equipment, it also is very favorable that each circuit forms on same substrate.For example, when CPU 812, memory 811 and I/O controller 813 formed single IC, they were connected to each other with external cabling.Simultaneously, when they form, just no longer need external cabling on same substrate, thereby reduced the size of product greatly.In addition, step of connecting and cost have also reduced, and cause the cost savings of product.
Because the operational data of write memory need not rewrite after deliver goods, the Write-once memory is applicable to electrical equipment.In addition, data can easily rewrite, so data content can consider that the final stage that writes the change of data or be updated in the product manufacturing determines and write.
[execution mode 3]
What describe in the present embodiment is the method that writes defective that is used to reduce memory cell.Be described with reference to Fig. 9 A and 9C that the vertical view of TFT is shown.Description is carried out with reference to Fig. 9 B, 9D and the 9E of the cross sectional view that TFT is shown.TFT is included in semiconductive thin film 901, the grid insulating film 905 on the semiconductive thin film 901 and the grid on grid insulating film 905 902 that forms on the dielectric substrate 903.Semiconductive thin film 901 has the high concentration impurity 904 that two wiring 906 are attached thereto respectively.Memory cell in the memory device of the present invention has write defective 907 shown in Fig. 9 A and 9B.When voltage put between grid and the semiconductive thin film, three terminals of TFT were generally insulated from each other; Yet in a defective element, semiconductive thin film 901 and grid insulating film 905 conduct each other as resistor and three terminals.
As a kind of method that is used to prevent this defective element, suggestion TFT adopts the double-gate structure with two grids shown in Fig. 9 C and 9D.Defective element produces randomly, because its hypothesis is what to be caused by the dust in semiconductive thin film or the insulation film.Even when defective 907 takes place in a channel region of for example two grids shown in Fig. 9 E, if other channel region becomes insulating regions 908, then two wiring 906 insulation, so TFT can be used as normal memory cell.Particularly, according to the data that occurred, defective element this time about 3% on detect.Because defective element produces at random, thus if adopted double-gate structure, but then reduce to its generation probability 0.1% or below.
By using said method, TFT can have multi grid and reduce defective element.The two or more grids of multiple-grid in this expression TFT.Along with increasing of grid quantity among the TFT, can reduce the generation of defective element.The number needs of grid will consider to use the area of the current drain of storage component part or the voltage that is applied, memory cell array to wait optimization.
Along with the increase of memory span, still produce defective element.The redundant circuit of the memory device that is similar to current manufacturing can be provided in this case, in addition.Perhaps, by the control external circuit, can forbid access to defective element as flash memory.
Claims (12)
1. memory device of only writing once, be included in the memory cell that forms on the insulating surface, described memory cell comprises the semiconductive thin film with the zone between two extrinsic regions and described two extrinsic regions, two wiring that are formed on the described zone and have the grid that is clipped in dielectric film wherein and be connected to respective impurity regions
Wherein by described grid and described two wiring one of at least between the described semiconductive thin film that applies between two wiring that voltage will be clipped in described memory cell change into state of insulation.
2. the memory device of only writing once as claimed in claim 1 is characterized in that, each memory cell of described memory device comprises two or more grids.
3. memory device of only writing once, be included in first memory cell and second memory cell that form on the insulating surface, each of described first memory cell and second memory cell all comprises the semiconductive thin film with the zone between two extrinsic regions and described two extrinsic regions, two wiring that are formed on the described zone and have the grid that is clipped in dielectric film wherein and be connected to respective impurity regions
Wherein said first memory cell comprises initial condition; And
By described grid and described two wiring one of at least between the semiconductive thin film that applies between two wiring that voltage will be clipped in described second memory cell change into state of insulation.
4. the memory device of only writing once as claimed in claim 3 is characterized in that, each memory cell of described memory device comprises two or more grids.
5. memory device of only writing once, be included in the memory cell that forms on the insulating surface, described memory cell comprises semiconductive thin film with one or two extrinsic region, be formed on the described extrinsic region and have the grid that is clipped in dielectric film wherein and be connected to two wiring of corresponding extrinsic region or be connected to two wiring of a described extrinsic region
Wherein by described grid and described two wiring one of at least between the described semiconductive thin film that applies between two wiring that voltage will be clipped in described memory cell change into state of insulation.
6. the memory device of only writing once as claimed in claim 5 is characterized in that, described grid clip is between described two wiring.
7. the memory device of only writing once as claimed in claim 5 is characterized in that, each memory cell of described memory device comprises two or more grids.
8. memory device of only writing once, be included in first memory cell and second memory cell that form on the insulating surface, each of first memory cell and second memory cell all comprises semiconductive thin film with one or two extrinsic region, be formed on the described extrinsic region and have the grid that is clipped in dielectric film wherein and be connected to two wiring of corresponding extrinsic region or be connected to two wiring of a described extrinsic region
Wherein said first memory cell has initial condition; And
By described grid and described two wiring one of at least between the semiconductive thin film that applies between two wiring that voltage will be clipped in described second memory cell change into state of insulation.
9. the memory device of only writing once as claimed in claim 8 is characterized in that, described grid clip is between described two wiring.
10. the memory device of only writing once as claimed in claim 8 is characterized in that, each memory cell of described memory device comprises two or more grids.
11. a manufacture method of only writing memory device once may further comprise the steps:
On insulating surface, form island shape semiconductor film;
On described island shape semiconductor film, form grid insulating film;
On described grid insulating film, form grid;
Doped N-type impurity element and described grid form N type high concentration impurity thus as mask in described island shape semiconductor film;
On described grid insulating film and described grid, form interlayer film;
In described interlayer film be connected in the wiring of described high concentration impurity and form contact hole, form memory cell thus, and
Voltage is put between the wiring of described grid and described memory cell, the channel region with described island shape semiconductor film becomes state of insulation thus.
12. the memory device manufacture method of only writing once as claimed in claim 11 is characterized in that each memory cell of described memory device comprises two or more grids.
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2004166274 | 2004-06-03 | ||
| JP166274/2004 | 2004-06-03 | ||
| JP270418/2004 | 2004-09-16 |
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| Publication Number | Publication Date |
|---|---|
| CN1965408A CN1965408A (en) | 2007-05-16 |
| CN100468741C true CN100468741C (en) | 2009-03-11 |
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ID=38083532
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|---|---|---|---|
| CNB200580018287XA Expired - Fee Related CN100468741C (en) | 2004-06-03 | 2005-05-31 | Memory device and manufacturing method of the same |
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| Country | Link |
|---|---|
| CN (1) | CN100468741C (en) |
-
2005
- 2005-05-31 CN CNB200580018287XA patent/CN100468741C/en not_active Expired - Fee Related
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