Embodiment
Below, specify the switching power unit of embodiment of the present invention with reference to accompanying drawing.
Fig. 1 represents the block diagram of switching power unit one configuration example of present embodiment.
Among Fig. 1, switching power unit control constitutes with the control circuit of semiconductor device 100 by the switch motion of switch element 1 and control switch element 1.
In addition, the external input terminals of semiconductor device 100 has four ends, is the GND end (SOURCE end) of control circuit comprising the output of input (DRAIN end), accessory power supply voltage input end (VCC end), secondary current cut-off time test side (TR end) and the switch element 1 of switch element 1.
Transformer 110 has elementary winding 110A, secondary winding 110B and auxiliary winding 110C.The polarity of elementary winding 110A and secondary winding 110B is opposite, and this switching power unit is a flyback.
Assist winding 110C and link to each other with the current rectifying and wave filtering circuit that capacitor 121 constitutes by diode 120.This current rectifying and wave filtering circuit is used as the accessory power supply portion of semiconductor device 100.That is to say that accessory power supply portion carries out rectification and filtering to the alternating voltage (secondary side alternating voltage) that produces at auxiliary winding 110C by the switch motion of switch element 1, generate accessory power supply voltage VCC, be added on the VCC end.Auxiliary winding 110C is identical with the polarity of secondary winding 110B, and accessory power supply voltage VCC is directly proportional with VD VO.
In addition, auxiliary winding 110C links to each other with resistance 123,124 through diode 122, and the tie point of this resistance 123,124 links to each other with the TR end.
As described later, the voltage that applies on the TR end (hereinafter referred to as TR terminal voltage VTR) is used to detect the mobile moment (hereinafter referred to as cut-off time) of secondary current end of flowing through secondary winding 110B by the switch motion of switch element 1.
Secondary winding 110B with link to each other with the current rectifying and wave filtering circuit that capacitor 131 constitutes by diode 130.This current rectifying and wave filtering circuit is used as the output voltage generating unit of this switching power unit.That is to say that the output voltage generating unit is carried out rectification and filtering to the alternating voltage (primary side alternating voltage) that produces at secondary winding 110B by the switch motion of switch element 1, generate VD VO, be added in the load 132.
Fig. 2 is the block diagram that a configuration example of semiconductor device 100 is used in the switching power unit control of the switching power unit of expression formation present embodiment.
Among Fig. 2, a certain end of adjuster 2 from DRAIN end or VCC end powered with power supply VDD to the internal circuit of semiconductor device 100, makes internal circuit be stabilized in certain value with the voltage of power supply VDD.
Promptly, adjuster 2 is before the switch motion of switch element 1 begins, power with power supply VDD to internal circuit from the DRAIN end, hold through of capacitor 121 power supplies of VCC end from DRAIN simultaneously, make the voltage rising of internal circuit with power supply VDD and accessory power supply voltage VCC to accessory power supply portion.Then, when adjuster 2 reaches certain value when internal circuit with the voltage of power supply VDD, will be from the low transition to the high level to the output signal of NAND circuit 20, the switch motion of beginning switch element 1.
After the switch motion of switch element 1 began, adjuster 2 stopped from the DRAIN end to the power supply of VCC end.Deciding with the electric current supply end of power supply VDD value after in addition, switch motion begins according to accessory power supply voltage VCC to internal circuit.
That is to say, if the switch motion by switch element 1 makes accessory power supply voltage VCC reach certain value and when above, then adjuster 2 from the VCC end to internal circuit with power supply VDD power supply.Reduce the power consumption of semiconductor device 100 according to this structure.
On the other hand, if accessory power supply voltage VCC drops to certain value when following when the VD VO in constant current zone descends etc., adjuster 2 from the DRAIN end to internal circuit with power supply VCC power supply.
By such action, adjuster 2 makes internal circuit be stabilized in certain value with power supply VDD.
Error amplifier 3 will be stablized with reference voltage and accessory power supply voltage VCC and compare, and generate error voltage signal VEAO according to its difference.
Drain current testing circuit (element current testing circuit) 4 detects and flows through electric current (drain current) ID of switch element 1, and the element current detection signal VCL that will become the voltage corresponding with its current value is to drain current control circuit (element current control circuit) 5 outputs.
Drain current control circuit 5 is imported as the overcurrent protection reference voltage V MILIT of reference voltage and the error voltage signal VEAO that exports from error amplifier 3.When if the voltage of element current detection signal VCL reaches voltage lower in the voltage of overcurrent protection reference voltage V LINIT and error voltage signal VEAO, the signal (being high level signal here) that drain current control circuit 5 is closed to AND circuit 18 output determine switch elements 1.
Oscillator 6 is selected the clock signal set_1 (the 1st clock signal) of circuit 13 output determine switch elements 1 action to clock signal.The frequency of oscillation of the switch element 1 in constant current zone when the frequency of this clock signal set_1 determines underloading.
Voltage as if the error voltage signal VEAO that exports from error amplifier 3 surpasses overcurrent protection reference voltage V LIMIT, and then frequency of oscillation is adjusted circuit 7 improves clock signal set_1 according to its difference frequency (shortening cycle).That is to say; frequency of oscillation is adjusted 7 in circuit under the high situation of the voltage ratio overcurrent protection reference voltage V LIMIT of error voltage signal VEAO; to the signal of oscillator 6 outputs the becoming current value corresponding, the feasible frequency that improves clock signal set_1 along with the increasing of this voltage difference with this voltage difference.According to this structure,, also can make VD VO be stabilized in certain value even load 132 increases the weight of.
The underloading intermittent oscillation control circuit 8 that is made of comparator 9, reference voltage source 10 and AND circuit 14 is according to the voltage from the error voltage signal VEAO of error amplifier 3 outputs, stop/beginning again selecting of the input of the clock signal of circuit 13 outputs to the set end of trigger 15 from clock signal, the switch motion of switch element 1 is stopped/beginning again, make switch element 1 intermittent oscillation.
Comparator (underloading comparator) 9 will compare with voltage VR from reference voltage source 10 outputs from the voltage of the error voltage signal VEAO of error amplifier 3 output, to the output signal of reference voltage source 10 and AND circuit 14 these comparative results of output expression.
Set the reference voltage V R2 (the 2nd reference voltage) of reference voltage V R1 (the 1st reference voltage) and the high potential higher than this reference voltage V R1 at reference voltage source (underloading reference voltage source) 10, reference voltage source 10 is according to the output signal of comparator 9, and one of them the voltage of reference voltage V R1 and reference voltage V R2 is provided to the inverting input of comparator 9.
That is to say, when the voltage of error voltage signal VEAO reduces and reaches reference voltage V R1, the output signal of comparator 9 from high level when low level is overturn, the voltage that reference voltage source 10 will provide to the inverting input of comparator 9 is changed to reference voltage V R2 from reference voltage V R1, when the voltage of error voltage signal VEAO rises and reaches reference voltage V R2, when high level overturn, changed to reference voltage V R1 from reference voltage V R2 by the voltage that reference voltage source 10 will provide to the inverting input of comparator 9 from low level for the output signal of comparator 9.
As above the voltage of 8 couples of error voltage signal VEAO of underloading intermittent oscillation control circuit of Gou Chenging compares with the reference voltage V R1 that exports from reference voltage source 10, if the voltage of error voltage signal VEAO descends and when reaching reference voltage V R1, then to the signal of AND circuit 14 output low levels, stop the set end input of clock signal, stop by the switch motion that makes switch element 1 like this to trigger 15.In addition, the voltage of 8 couples of error voltage signal VEAO of underloading intermittent oscillation control circuit compares with the reference voltage V R2 that exports from reference voltage source 10, if the voltage of error voltage signal VEAO rises and when reaching reference voltage V R2, then export the signal of high level to AND circuit 14, make clock signal begin again to import, begin again by the switch motion that makes switch element 1 like this to the set end of trigger 15.
The secondary current that links to each other with TR end detects cut-off time of secondary current by testing circuit 11 according to TR terminal voltage VTR (secondary side alternating voltage), after switch element 1 disconnects to detect till secondary current cut-off time during limit circuit 12 to oscillator 6 and secondary duty ratio in (being between the secondary current flow periods) and export the output signal D2_on that becomes high level.
In the switching power unit of flyback,, flow through electric current among the elementary winding 110A of transformer 110 in the conduction period of switch element 1, stored energy in transformer 110, between the off period of switch element 1, emit the energy of storage, flow through secondary current among the secondary winding 110B of transformer 110.Then, when the secondary current vanishing, because of the inductance of transformer 110 and the parasitic capacitance of switch element 1 produce resonance phenomena.This resonance phenomena appears at each winding of transformer 110.Secondary current passes through the trailing edge that 1 shutoff of sense switch element assists the voltage waveform of winding 110C to occur afterwards by testing circuit 11, detects the cut-off time of secondary current.
With secondary current by the output signal D2_on of testing circuit 11 detect as the secondary duty ratio restriction circuit 12 of input turn-off from switch element 1 the time till being carved into cut-off time of secondary current during, and be the moment of certain setting in the conducting duty ratio of secondary current, the signal set_2 that selects circuit 13 output determine switch elements 1 to open to clock signal.
That is to say, the output signal set_2 of secondary duty ratio restriction circuit 12 becomes the clock signal (the 2nd clock signal) that determine switch element 1 is opened, make the conducting duty ratio of secondary current maintain setting, its frequency carries along with flowing through that 132 electric current increases, the conduction period of secondary current (flow through secondary current during) prolongs and descend.The frequency of oscillation of the frequency decision constant current zone of this clock signal set_2 and the switch element 1 of Off font protection zone.Also have, the setting of the conducting duty ratio of secondary current for example is about 50% (being preferably 50%).
Select circuit 13 to the lower signal of AND circuit 14 output frequencies as the clock signal of input the output signal set_1 of oscillator 6 and the output signal set_2 of secondary duty ratio restriction circuit 12.
That is to say, when load is light, when the frequency of frequency ratio the 2nd clock signal set_2 of the 1st clock signal set_1 is low when following (or), clock signal is selected circuit 13 outputs the 1st clock signal set_1.On the other hand, when load increased the weight of, utilizes frequency of oscillation to adjust circuit 7 to make the frequency of the 1st clock signal set_1 be the frequency of the 2nd clock signal set_2 and above (or being higher than) thereof, clock signal was selected circuit 13 outputs the 2nd clock signal set_2.
Therefore, when the conducting duty ratio of secondary current during less than setting, clock signal selects circuit 13 to AND circuit 14 outputs the 1st clock signal set_1.On the other hand, if load increases the weight of, when the conducting duty ratio of secondary current reaches setting, clock signal selects circuit 13 to AND circuit 14 outputs the 2nd clock signal set_2, makes the conducting duty ratio of secondary current maintain setting.
The output signal that AND circuit 14 is selected the output signal (clock signal) of circuit 13 and the comparator 9 in the underloading intermittent oscillation control circuit 8 since clock signal is in the future exported (asserts signal set) with output signal to the set end of trigger 15 as input.
Here, clock signal control circuit selects circuit 13 and AND circuit 14 to constitute by clock signal.
That is to say, clock signal control circuit is when the conducting duty ratio of secondary current during less than setting, output is from the clock signal set_1 of oscillator 6, if when the conducting duty ratio of secondary current reaches setting, then exports the clock signal set_2 from secondary duty ratio restriction circuit 12.
In addition, clock signal control circuit is accepted the comparative result that the comparator 9 in the underloading intermittent oscillation control circuit 8 obtains, if the voltage of error voltage signal VEAO descends and when reaching reference voltage V R1, then stop the 1st or the 2nd clock signal set_1 to trigger 15, the output of set_2, if the voltage of error voltage signal VEAO rises and when reaching reference voltage V R2, then begin to trigger 15 output the 1st or the 2nd clock signal set_1, set_2 again.
Like this, when underloading, clock signal control circuit stops/beginning the switch motion of switch element 1 again according to the output signal of comparator 9, makes switch element 1 carry out the intermittent oscillation action.
Trigger 15 if through AND circuit 14 to its set end input clock signal set_1 or clock signal set_2, then rise thereon along constantly being in SM set mode.On the other hand, trigger 15 is if during to signal that its reset terminal input is turn-offed from the determine switch element 1 of drain current control circuit 5, then be in reset mode through AND circuit 18.Trigger 15 will be exported to NAND circuit 20 with the corresponding input signal of set/reset state.
Here, ON-OFF control circuit is made of trigger 15, NAND circuit 20 and gate drivers 21.ON-OFF control circuit is come the switch motion (conduction and cut-off action repeatedly) of control switch element 1 according to the set/reset state of trigger 15.
If accessory power supply voltage VCC is lower than set point, then the overcurrent protection reference voltage is adjusted circuit 16 along with its decline, and overcurrent protection reference voltage V LIMIT is also descended.According to this structure, during overload when load short circuits etc., the peak current value that flows through the drain current ID of switch element 1 descends along with the decline of VD VO, and the conducting duty ratio of secondary current is certain setting.
Thereby according to this switching power unit, during overload when load short circuits etc., VD VO descends more, can suppress output current IO more little, can realize the protection of safe Off font.
During the setting-up time of the action pulse signal that switch element 1 is opened after gate drivers 21 outputs, close pulse generating circuit 17 to AND circuit 18 output low level signals during conducting.
Thereby according to this switching power unit, the flase drop that the peak current in the time of can preventing because of action produces is surveyed action.
The output signal of closing pulse generating circuit 17 of AND circuit 18 during with the output signal of drain current control circuit 5 and conducting is as input, with the reset terminal output of output signal to trigger 15.
When the temperature of semiconductor device 100 reaches design temperature and when above, overheating protection circuit 19 is to NAND circuit 20 output low level signals, with the switch motion of shutdown switch element 1.
NAND circuit 20 with the output signal of the output signal of the output signal of adjuster 2, trigger 15, overheating protection circuit 19 as input, with output signal to gate drivers 21 outputs.
With the output signal of NAND circuit 20 as the gate drivers 21 of input action pulse signal to the switch motion of control end (gate terminal) the output control switch element 1 of switch element 1.Switch element 1 carries out repeatedly the switch motion of conduction and cut-off action according to the action pulse signal from gate drivers 21.
Switch element 1 is by carrying out switch motion, the DC input voitage VIN of the elementary winding 110A of input transformer 110 carried out switch control, and produce the primary side alternating voltage at secondary winding 110B, simultaneously at auxiliary winding 110C generation secondary side alternating voltage.
As mentioned above; the switch motion of the such control switch element 1 of control circuit; the peak current value that it makes the drain current ID that flows through switch element 1 is the certain value according to the current value of overcurrent protection reference voltage V LIMIT decision; if when the conducting duty ratio of the secondary current that begins to flow through after switch element 1 turn-offs in the secondary winding 110B of transformer 110 reached setting, the conducting duty ratio of secondary current maintained this setting.According to this control circuit, can detect resistance and optical coupler without constant-current control circuit, the output current of primary side, can realize high-precision constant current droop characteristic with low-cost, minimum component number and minimum power loss.
Thereby, according to this switching power unit, can constitute high-precision charger Switching Power Supply with less component number, can realize low cost, miniaturization and energy-conservationization of charger with Switching Power Supply.
In addition, constitute semiconductor device 100 on the same semiconductor substrate, can reduce the component number that forming circuit is used, can be easy to realize miniaturization and lightweight, and then reduce cost by switch element 1 and its control circuit are formed on.
Fig. 3 is that the switching power unit control of the switching power unit of expression formation present embodiment ends the block diagram of a configuration example of testing circuit 11 and secondary duty ratio restriction circuit 12 with the secondary current of the part of semiconductor device 100.
Secondary current by testing circuit 11 by comparator 22, single pulse signal generation circuit 23 and 24 and trigger 25 constitute, each element connects as shown in Figure 3.
Is trailing edge (the moment that switch element 1 turn-off) the generation single pulse signal of action pulse signal as the single pulse signal generation circuit of importing 24 in the output signal of gate drivers 21 with the output signal of gate drivers 21, to the set end input of trigger 25.
Comparator 22 compares TR terminal voltage VTR and reference voltage, detects the trailing edge of TR terminal voltage VTR, and the trailing edge that the voltage waveform of the auxiliary winding 110C after promptly switch element 1 turn-offs occurs is exported output signal to single pulse signal generation circuit 23.Like this, secondary current detects the cut-off time of secondary current by testing circuit 11.
With the output signal of comparator 22 single pulse signal generation circuit 23, in the moment (cut-off time of secondary current) in that TR terminal voltage VTR is lower than reference voltage, produce single pulse signal, to the reset terminal input of trigger 25 as input.Therefore, the initial trailing edge of the TR terminal voltage VTR after switch element 1 turn-offs is (cut-off time of secondary current) constantly, with the output signal and the reversed-phase output signal upset of trigger 25.
According to as above structure, turn-off secondary current at switch element 1 and finish between flow periods, promptly flow through (conduction period of secondary current) during the secondary current, the output signal of trigger 25 is a high level, reversed-phase output signal is a low level.Then, in the cut-off time of secondary current, the output signal of trigger 25 and reversed-phase output signal upset, import next action pulse signal to switch element 1, during till switch element 1 becomes shutoff (during not flowing through secondary current), output signal becomes low level, and reversed-phase output signal becomes high level.
Secondary duty ratio restriction circuit 12 is made of negative circuit 26, AND circuit 27,36, constant-current source 28, switch 29,30,31, N-channel MOS FET32,33, capacitor 34, comparator 35 and single pulse signal generation circuit 37, and each element connects as shown in Figure 3.
Switch 29,30 utilizes secondary current to end the output signal of the trigger 25 in the testing circuit 11 and reversed-phase output signal to carry out conducting and end.Then, carry out discharging and recharging of capacitor 34 by the action of this switch 29,30.
That is to say, during after switch element 1 shutoff, finishing to flow (during flowing through secondary current) to secondary current, because the output signal of trigger 25 is a high level, reversed-phase output signal is a low level, therefore switch 29 conductings, switch 30 ends, and utilizes the constant current I2 of constant-current source 28 that capacitor 34 is charged, and the voltage VC2 of capacitor 34 is risen.On the other hand, after secondary current finish to flow to next unbalanced pulse signal input, switch element 1 become shutoff during (secondary current do not flow through during), owing to switch 29 ends, switch 30 conductings, so capacitor 34 discharges.At this moment discharging current is decided by the constant current I2 of constant-current source 28 and the current mirroring circuit that is made of N-channel MOS FET32,33.
In addition, the output signal of gate drivers 21 is exported high level signal as the negative circuit 26 of input between the off period of switch element 1.
With the output signal of the reversed-phase output signal of trigger 25 and negative circuit 26 as the AND circuit 27 of input during secondary current does not flow through and between the off period of switch element, make switch 31 conductings, and the drain electrode end of N-channel MOS FET32 is applied reference voltage (VA-α).
Thereby by, switch 30 conductings and 31 conduction periods of switch, during promptly secondary current does not flow through and switch element between 1 off period, the voltage VC2 of capacitor 34 remains on reference voltage (VA-α) at switch 29.That is to say, at the interdischarge interval of capacitor 34, form this voltage VC2 remain on certain value (VA-α) during.According to this spline structure, the discharge ionization voltage of the capacitor 34 the during unlatching of switch element 1 is fixed.
Comparator 35 compares the voltage VC2 and the reference voltage V A of capacitor 34, to AND circuit 36 output signals (comparative result).When the voltage VC2 of capacitor 34 was lower than reference voltage V A, comparator 35 was output as high level signal, and when the voltage VC2 of capacitor 34 was higher than reference voltage V A, comparator 35 was output as low level signal.
AND circuit 36 with the output signal of the reversed-phase output signal of trigger 25 and comparator 35 as input, with output signal to 37 outputs of single pulse signal generation circuit.
Single pulse signal generation circuit 37 in the output signal of AND circuit 36 from the moment of low level to the high level upset, the voltage VC2 that is middle capacitor 34 during secondary current does not flow through drops to the following moment of reference voltage V A, selects circuit 13 output single pulse signal (clock signal) set_2 to clock signal.
According to as above structure, the unlatching with the fixing capacitor 34 of reference voltage (VA-α) and switch element 1 when switch element 1 is opened begins discharge simultaneously.And capacitor 34 is transformed into charging in the moment that switch element 1 turn-offs from discharge, charges during flowing through secondary current, is transformed into discharge from charging once more in the cut-off time of secondary current.Then, when the voltage VC2 of capacitor 34 drops to reference voltage V A when following once more, single pulse signal generation circuit 37 output single pulse signal (clock signal) set_2.
Thereby output single pulse signal set_2 makes that the conducting duty ratio at secondary current is moment switch element 1 unlatching of setting.
Like this, to select circuit 13 outputs to make the conducting duty ratio of secondary current to clock signal be the clock signal set_2 of setting to secondary duty ratio restriction circuit 12.
Fig. 4 is a configuration example of circuit 13 is selected in the switching power unit control of the switching power unit of expression formation present embodiment with the clock signal of the part of semiconductor device 100 a block diagram.
Clock selection circuit 13 is made of single pulse signal generation circuit 38,39,44, OR circuit 40, trigger 41,42 and AND circuit 43, and each element connects as shown in Figure 4.
With the output signal of gate drivers 21 single pulse signal generation circuit 38, be that the trailing edge (moment that switch element 1 turn-offs) of unbalanced pulse signal produces single pulse signal in the output signal of gate drivers 21, to 40 inputs of OR circuit as input.
In addition, with the output signal of the comparator 9 in the underloading intermittent oscillation control circuit 8 single pulse signal generation circuit 39 as input, rising edge in the output signal of comparator 9, it is the moment that the switch motion of the switch element 1 during the underloading intermittent oscillation begins again, produce single pulse signal, to 40 inputs of OR circuit.
OR circuit 40 is with the reset terminal input of output signal to trigger 41,42.That is, OR circuit 40 is in the moment that switch element 1 turn-offs, or moment of beginning again of the switch motion of the switch element during the underloading intermittent oscillation 1, to the reset terminal input high level of trigger 41,42.
About trigger 41, be output signal (clock signal set_1) to its set end input oscillator 6, to the output signal of its reset terminal input OR circuit 40, output signal is exported to AND circuit 43.
About trigger 42, be output signal (clock signal set_2) from secondary duty ratio restriction circuit 12 to its set end that import, to the output signal of its reset terminal input OR circuit 40, output signal is exported to AND circuit 43.
AND circuit 43 with the output signal of trigger 41,42 as input, with output signal to 44 outputs of single pulse signal generation circuit.
Single pulse signal generation circuit 44 is exported single pulse signal sets to the moment of high level upset to AND circuit 14 from low level in the output signal of AND circuit 43.That is to say that single pulse signal generation circuit 44 is just exported single pulse signal set after clock signal set_1 and these two clock signals of clock signal set_2 all rise.
According to as above structure, clock signal selects circuit 13 to the output signal set_1 of AND circuit 14 output oscillators 6 and the low signal of output signal set_2 medium frequency of secondary duty ratio restriction circuit 12.
Thereby, when the conducting duty ratio of secondary current during less than setting, clock signal select circuit 13 with the 1st clock signal set_1 to 14 outputs of AND circuit.On the other hand, if when the conducting duty ratio of secondary current reaches setting, clock signal selects circuit 13 to AND circuit 14 outputs the 2nd clock signal set_2, and makes the conducting duty ratio of secondary current maintain this setting.
Fig. 5 is the block diagram that the switching power unit control of the switching power unit of expression formation present embodiment is adjusted a configuration example of circuit 7 with the oscillator 6 and the frequency of oscillation of the part of semiconductor device 100.
Oscillator 6 is made of comparator 45, reference voltage source 46, capacitor 47, single pulse signal generation circuit 48, negative circuit 49, AND circuit 50, constant-current source 51, switch 52,53,54 and N-channel MOS FET55,56, and each element connects as shown in Figure 5.
Comparator 45 compares the voltage VC1 of capacitor 47 and the reference voltage of reference voltage source 46, if the voltage VC1 of capacitor 47 is lower than reference voltage, then output low level if the voltage VC1 of capacitor 47 is higher than reference voltage, is then exported high level.
At two different reference voltage V 1, V2 that the output signal of reference voltage source 46 set basis comparators 45 is changed, reference voltage V 2 is than reference voltage V 1 height.About the reference voltage of reference voltage source 46, when the output signal of comparator 45 from high level when low level is overturn, be transformed into reference voltage V 2 from reference voltage V 1, when from low level when high level overturns, be transformed into reference voltage V 1 from reference voltage V 2.
If the voltage VC1 of capacitor 47 is lower than reference voltage V 1, then the output signal of comparator 45 is overturn to low level from high level, switch 52 conductings, and switch 53 ends, and the constant current I1 of constant-current source 51 charges to capacitor 47, and the voltage VC1 of capacitor 47 is risen.Then, if the voltage VC1 of capacitor 47 is higher than reference voltage V 2, then the output signal of comparator 45 is overturn to high level from low level, and switch 52 ends, switch 53 conductings, capacitor 47 discharges.At this moment the current mirroring circuit decision that discharging current is made of the constant current I1 and the N-channel MOS FET55,56 of constant-current source 51.
Like this, switch 52,53 utilizes the output signal of comparator 45 to carry out conducting, end, and capacitor 47 is discharged and recharged, and the voltage VC1 of capacitor 47 becomes the waveform that vibrates between two reference voltage V 1, V2.
In addition, AND circuit 50 with the output signal of the output signal D2_on of the trigger 25 of secondary current in testing circuit 11 and comparator 45 as input, during output signal D2_on is promptly to flow through secondary current between high period, switch 54 conductings apply reference voltage V B to the drain electrode end of N-channel MOS FET55.
Thereby if the voltage VC1 of capacitor 47 drops to reference voltage V B at interdischarge interval, then secondary current remains on reference voltage V B before finishing to flow.
Single pulse signal generation circuit 48 from the moment of high level to the low level upset, that is to say at capacitor 47 from the moment that interdischarge interval is changed output single pulse signal (clock signal) set_1 in the output signal of comparator 45 between charge period.
As mentioned above, the voltage VC1 of capacitor 47 can not be lower than reference voltage V B during flowing through secondary current.That is to say and just can not export single pulse signal set_1 as long as secondary current does not finish to flow.That is, this switching power unit must move with discontinuous mode.
According to as above structure, oscillator 6 is selected the clock signal set_1 of the frequency of oscillation of circuit 13 output determine switch elements 1 to clock signal.
Frequency of oscillation is adjusted circuit 7 and is made of NPN transistor 57,58, resistance 59,60, P channel mosfet 61,62,63,64,67,68 and N-channel MOS FET65,66, and each element connects as shown in Figure 5.
Base terminal input error voltage signal VEAO to NPN transistor 57.Therefore, the electric current that flows through N-channel MOS FET66 becomes the electric current that is directly proportional with the voltage of error voltage signal VEAO.Also have, constitute current mirroring circuit, constitute current mirroring circuit by N-channel MOS FET65,66 by P channel mosfet 61,62.
On the other hand, import overcurrent protection reference voltage V LIMIT to the base terminal of NPN transistor 58.Therefore, the electric current that flows through P channel mosfet 64 becomes the electric current that is directly proportional with overcurrent protection reference voltage V LIMIT.Also have, constitute current mirroring circuit by P channel mosfet 63,64.
When the electric current that flows through N-channel MOS FET66 when flowing through the electric current of P channel mosfet 64, do not have electric current to flow through in the current mirroring circuit that constitutes by P channel mosfet 67,68.On the other hand, when the electric current that flows through N-channel MOS FET66 when flowing through the electric current of P channel mosfet 64, the electric current that flows through N-channel MOS FET66 flows through the current mirroring circuit that is made of P channel mosfet 67,68 with the electric current that flows through the difference between currents of P channel mosfet 64.Then, will flow through the constant current I1 addition of P channel mosfet 68 and constant-current source 51, the cycle that discharges and recharges of capacitor 47 is shortened.
Thereby if the voltage of error voltage signal VEAO is higher than overcurrent protection reference voltage V LIMIT, then the frequency from the clock signal set_1 of oscillator 6 outputs also improves, and its difference is big more, and frequency is high more.
According to as above structure; when 7 voltages at error voltage signal VEAO of frequency of oscillation adjustment circuit are higher than overcurrent protection reference voltage V LIMIT; signal to oscillator 6 outputs the becoming current value corresponding with this voltage difference; if the voltage of error voltage signal VEAO is higher than overcurrent protection reference voltage V LIMIT, then the frequency from the clock signal set_1 of oscillator 6 outputs rises along with the increasing of its difference.
Fig. 6 is a configuration example of circuit 16 is adjusted in the switching power unit control of the switching power unit of expression formation present embodiment with the overcurrent protection reference voltage of the part of semiconductor device 100 a block diagram.
The overcurrent protection reference voltage is adjusted circuit 16 and is made of resistance 69,70,73,86, comparator 71, NPN transistor 72, P channel mosfet 74,75,84,85, N-channel MOS FET76,77,79,80,82,83, constant- current source 78,81 and switch 87.Each element connects as shown in Figure 6.
Comparator 71 will be compared by the accessory power supply voltage VCC and the reference voltage of resistance 69 and resistance 70 dividing potential drops, if accessory power supply voltage VCC is lower than set point, then exports high level, makes switch 87 conductings.
In addition, the accessory power supply voltage VCC by resistance 69 and resistance 70 dividing potential drops is transformed to the electric current I 6 that is directly proportional with accessory power supply voltage VCC by NPN transistor 72 and resistance 73.
This electric current I 6 flows through current mirroring circuit that is made of P channel mosfet 74,75 and the current mirroring circuit that is made of N-channel MOS FET76,77.
When accessory power supply voltage VCC was lower than set point, because switch 87 conductings, so the constant current I4 that constant-current source 78 is set flow through switch 87, and the electric current of the difference of constant current I4 and electric current I 6 flows through the current mirroring circuit that is made of N-channel MOS FET79,80.And then, the constant current I5 that constant-current source 81 is set deduct constant current I4 and electric current I 6 difference electric current and the electric current I 7 that obtains flows through current mirroring circuit that is made of N-channel MOS FET82,83 and the current mirroring circuit that is made of P channel mosfet 84,85.
Then, the voltage that is obtained by the resistance value R1 of electric current I 7 and resistance 86 is exported as overcurrent protection reference voltage V LIMIT.Be that overcurrent protection reference voltage V LIMIT is shown below.
VLIMIT=R1×I7=R1×(I5-(I4-I6))
Because electric current I 6 is the electric currents that are directly proportional with accessory power supply voltage VCC, so overcurrent protection reference voltage V LIMIT becomes the voltage that is directly proportional with accessory power supply voltage VCC.
Just, when the accessory power supply voltage VCC by resistance 69,70 dividing potential drops was higher than the reference voltage of comparator 71, because switch 87 ends, the electric current that therefore flows through resistance 86 equated with the constant current I5 that constant-current source 81 is set.
Thereby when accessory power supply voltage VCC is a set point and when above, overcurrent protection reference voltage V LIMIT is constant, if accessory power supply voltage VCC is lower than set point, then overcurrent protection reference voltage V LIMIT reduces along with the decline of accessory power supply voltage VCC.
Like this, when overcurrent protection reference voltage adjustment circuit 16 just thinks that accessory power supply voltage VCC is lower than set point, overcurrent protection reference voltage V LIMIT is reduced.
The below as above action of the switching power unit of formation of explanation.
Before switch motion begins, if the input of this switching power unit is for example imported commercial ac power source through the DC input voitage VIN of over commutation and filtering, then this DC input voitage VIN is added in the DRAIN end of semiconductor device 100 through the elementary winding 110A of transformer 110.Adjuster 2 is supplied with the electric current that is produced by DC input voitage VIN from the DRAIN end to internal circuit with power supply VDD, supply with the electric current that produces by DC input voitage VIN through the VCC end to the capacitor 121 of accessory power supply portion simultaneously, internal circuit is risen with the voltage of power supply VDD and accessory power supply voltage VCC.If internal circuit reaches certain value with the voltage of power supply VDD, then switch element 1 beginning switch motion.
If switch element 1 beginning switch motion then to each winding energize of transformer 110, produces alternating voltage at secondary winding 110B and auxiliary winding 110C, and flows through electric current.
The power (primary side alternating voltage and secondary current) that secondary winding 110B produces carries out rectification and filtering by diode 130 and capacitor 131, becomes direct current power (VD VO and output current IO), supplies with to load 132.
The power (secondary side alternating voltage and secondary side electric current) that auxiliary winding 110C produces carries out rectification and filtering by diode 120 and capacitor 121, is used as the accessory power supply of semiconductor 110.Because the polarity of auxiliary winding 110C is identical with secondary winding 110B, so accessory power supply voltage VCC becomes the voltage that is directly proportional with VD VO.
If switch element 1 beginning switch motion, then VD VO and accessory power supply voltage VCC rise.If accessory power supply voltage VCC rises, then the voltage of the error voltage signal VEAO of error amplifier 3 descends.If the voltage of error voltage signal VEAO descends, then drain current control circuit 5 such control switch elements 1 make the drain current ID that flows through switch element 1 descend.By adding such negative feedback, make VD VO stable.That is to say that accessory power supply voltage VCC also is used for the stable of VD VO.
In addition, the secondary side alternating voltage that auxiliary winding 110C produces carries out rectification by diode 122, by resistance 123 and resistance 124 dividing potential drops, to the input of TR end.If the secondary current that flows through secondary winding 110B is zero, then cause the resonance phenomena that the parasitic capacitance by the inductance of transformer 110 and switch element 1 produces.The trailing edge that the voltage waveform of the auxiliary winding 110C of secondary current after testing circuit 11 sense switch elements 1 turn-off occurs, the cut-off time of detection secondary current.
Adjuster 2 stops to accessory power supply portion power supply after switch motion begins, if accessory power supply voltage VCC reach certain value and more than, then supply with the electric current that produces by accessory power supply voltage VCC with power supply VDD to internal circuit from the VCC end.Thereby, the power consumption that the semiconductor device 100 when this switching power unit can reduce common action produces.
On the other hand, if accessory power supply voltage VCC drops under the certain value, then adjuster 2 is supplied with the electric current that is produced by DC input voitage VIN from the DRAIN end to internal circuit with power supply VDD.
Switch element 1 carries out switch motion according to the output signal through the trigger 15 of NAND circuit 20 and gate drivers 21 inputs.
To the set end of trigger 15, select some signals among output signal (single pulse signal) set_2 of output signal (single pulse signal) set_1 of circuit 13 and AND circuit 14 input oscillators 6 or secondary duty ratio restriction circuit 12 through clock signal.If the set end of trigger 15 is imported output signal set_1 or output signal set_2, then to switch element 1 input unbalanced pulse signal, switch element 1 action.
On the other hand, the reset terminal of trigger 15 when importing conductings, AND circuit 18 is closed the output signal of pulse generating circuit 17 and drain current control circuit 5.When if the voltage of the element current detection signal VCL of drain current testing circuit 4 reaches lower voltage in the voltage of overcurrent protection reference voltage V LIMIT and error voltage signal VEAO, the output signal of output drain current control circuit 5.Thereby when if drain current ID reaches the current value that voltage or overcurrent protection reference voltage V LIMIT by error voltage signal VEAO determined, switch element 1 turn-offs.
As mentioned above, the elemental motion of this switching power unit is the action of carrying out with the fixing peak current control mode of frequency of oscillation.In addition, the action about switch element 1 beginning switch motion and VD VO after stable, then as shown in Figure 7, different because of flowing through the state that carries 132 output current IO.
Below; be downloaded to the order that heavy duty changes on the lenient side according to load 132, each state that is divided into<during (1) underloading 〉,<(2) constant voltage zone 1 〉,<(3) constant voltage zone 2 〉,<borderline region in (4) constant voltage zone 2 and constant current zone 〉,<(5) constant current zone 〉,<(6) Off font protection zone〉illustrates the action of this switching power unit.
<during (1) underloading 〉
Fig. 8 is the sequential chart of this switching power unit of expression in the various piece action of<during underloading 〉.So-called<during underloading〉is meant the zone when being lower than reference voltage V R from reference voltage source 10 outputs from the voltage of the error voltage signal VEAO of error amplifier 3 outputs.
Also have, in Fig. 8~13, VCC represents accessory power supply voltage.VD represents that the input of switch element 1 is the voltage of DRAIN end.ID represents drain current (being the voltage of element current detection signal VCL).ID2 represents to flow through the electric current of secondary side diode 130.VTR represents the TR terminal voltage.VEAO represents the voltage of error voltage signal.VR represents the reference voltage of reference voltage source 10.VC1 represents the voltage of the capacitor 47 in the oscillator 6.Set_1 represents the clock signal (single pulse signal) of oscillator 6 outputs.VC2 represents the voltage of the capacitor 34 in the secondary duty ratio restriction circuit 12.Set_2 represents the clock signal (single pulse signal) of secondary duty ratio restriction circuit 12 outputs.Set represents the asserts signal (output signal of AND circuit 14) to the set end input of trigger 15.Reset represents the reset signal (output signal of AND circuit 18) to the reset terminal input of trigger 15.VG represents the voltage of the control end (gate terminal) of switch element.
Carry 132 output current IO when very little when flowing through, because it is also very little to flow through the electric current of secondary winding 110B, also very short during the secondary current circulation, therefore export moment of output signal (single pulse signal) set_1 of moment specific output oscillator 6 of output signal (single pulse signal) set_2 of secondary duty ratio restriction circuit 12 and want fast.Thus, the set end of trigger 15 is imported the output signal set_1 (asserts signal set) of oscillator 6.
On the other hand, carry 132 output current IO and descend if flow through, then VD VO and accessory power supply voltage VCC rise a little.If along with accessory power supply voltage VCC rises, the voltage of error voltage signal VEAO and descending, then drain current control circuit 5 control switch elements 1 make drain current ID reduce.
At this moment, when if the voltage of error voltage signal VEAO reaches the reference voltage V R1 of the low potential side among two reference voltage V R1, the VR2 that reference voltage source 10 sets, the output signal of the comparator 9 in the underloading intermittent oscillation control circuit 8 is a low level, and to 14 inputs of AND circuit, the asserts signal set that imports to the set end of trigger 15 is a low level.Thereby, in bistable state the set end of resonance oscillation circuit 15 is not imported the clock signal of the unlatching of determine switch element 1, the switch motion of switch element 1 stops.In addition, at this moment, the reference voltage V R of reference voltage source 10 changes to the reference voltage V R2 of hot side from reference voltage V R1 simultaneously.
If the switch motion of switch element 1 stops, then because the energy of supplying with through transformer 110 stops, so VD VO and accessory power supply voltage VCC descend gradually.If accessory power supply voltage VCC descends, then the voltage of error voltage signal VEAO rises, but because the reference voltage V R of reference voltage source 10 becomes the reference voltage V R2 of hot side, thus asserts signal set still to keep low level constant, the switch motion of switch element 1 can not begin immediately again.
If VD VO and accessory power supply voltage VCC further descend, when the voltage of error voltage signal VEAO reaches reference voltage V R2, the output signal of comparator 9 becomes high level, and, utilize the output signal set_1 of oscillator 6 to begin the switch motion of switch element 1 again to 14 inputs of AND circuit.In addition, at this moment, the reference voltage V R of reference voltage source 10 changes to the reference voltage V R1 of low potential side from reference voltage V R2 simultaneously.
The voltage of error voltage signal VEAO when the switch motion of switch element 1 begins again is reference voltage V R2, the electric current when the drain current ID that flows through switch element 1 stops greater than switch motion.Thereby VD VO and accessory power supply voltage VCC rise, and the voltage of error voltage signal VEAO descends.Then, if when the voltage of error voltage signal VEAO reaches reference voltage V R1, the switch motion of switch element 1 stops once more.
Like this, carry 132 output current IO when very little when flowing through, the switch motion of switch element 1 becomes repeatedly and stops/the intermittent oscillation action that beginning again.The stopping period of this switch motion and depend on VD VO again between elementary period and the rising of accessory power supply voltage VCC and the speed of decline.That is to say that because it is more little to flow to the output current IO of load 132, VD VO and accessory power supply voltage VCC rise soon more, descend slowly more, so the switch motion stopping period of switch element 1 prolongs.
As mentioned above, the action of this switching power unit of<during underloading〉becomes the action that intermittent oscillation control mode that the switch motion with switch element 1 stops repeatedly/begin is carried out, the output current IO that flows to load 132 is more little, and the switch motion stopping period of switch element 1 is long more.Thereby,, can reduce the loss that the switch motion of the switch element 1 of<during underloading〉produces according to this switching power unit, can improve power consumption and efficient.In addition, by this intermittent oscillation control, can suppress the rising of the VD VO of<during underloading 〉.
Also have, when intermittent oscillation was controlled, the frequency of oscillation of switch element 1 descended.Therefore, when entering voiced band, can hear the magnetostriction noise of transformer usually as if frequency of oscillation.But, in this switching power unit,, therefore in fact can't hear the magnetostriction noise because the peak current value of the drain current ID intermittent oscillation can be controlled the time can be controlled lowlyer with the current value of reference voltage V R1 and reference voltage V R2 decision.Thus,, the influence of the magnetostriction noise of transformer need not be considered, the frequency of intermittent oscillation can be fully reduced, the power consumption in the time of reducing standby significantly according to this switching power unit.
For example; as long as about 15% (being preferably 15%) and about 20% (being preferably 20%) that the 1st reference voltage V R1 and the 2nd reference voltage V R2 of reference voltage source 10 is set in overcurrent protection reference voltage V LIMIT respectively; the peak current value of drain current ID when then intermittent oscillation is controlled is just enough little, can't hear the magnetostriction noise of transformer.
<(2) constant voltage zone 1 〉
Fig. 9 is the action timing diagram of this switching power unit of expression in the various piece in<constant voltage zone 1 〉.So-called should<constant voltage zone 1 〉, be meant from the voltage of the error voltage signal VEAO of error amplifier 3 outputs to be higher than from the reference voltage V R of reference voltage source 10 outputs and to be lower than the zone of overcurrent protection reference voltage V LIMIT.
Carry 132 output current IO greater than underloading if flow through; VD VO is low a little during than underloading; the voltage of error voltage signal VEAO is in the state that is higher than reference voltage V R and is lower than overcurrent protection reference voltage V LIMIT; then the output signal of the comparator 9 in the underloading intermittent oscillation control circuit 8 becomes high level, and to 14 inputs of AND circuit.
In addition, in this<constant voltage zone 1 〉, because the secondary current that flows through secondary winding 110B is very little, flow through secondary current during very short, therefore export moment of output signal set_1 of moment specific output oscillator 6 of the output signal set_2 of secondary duty ratio restriction circuit 12 and want fast.Therefore, the set end of trigger 15 is imported the output signal set_1 (asserts signal set) of oscillator 6.
Thereby, in<constant voltage zone 1 〉, because the clock signal set_1 from oscillator 6 becomes asserts signal set, the output signal of the drain current control circuit 5 that will compare from the voltage of the voltage of the element current detection signal VCL of drain current testing circuit 4 output and error voltage signal VEAO and export becomes reset signal reset, therefore this switching power unit has broken away from the intermittent oscillation state of a control, is in the state that moves with the peak current control mode of built-in oscillation frequency.
<(3) constant voltage zone 2 〉
Figure 10 is the action timing diagram of the various piece of this switching power unit of expression<constant voltage zone 2 〉.So-called should<constant voltage zone 2 〉, be meant the zone that is higher than overcurrent protection reference voltage V LIMIT from the voltage of the error voltage signal VEAO of error amplifier 3 outputs.
Carry 132 output current IO greater than<constant voltage zone 1〉if flow through; VD VO is lower a little than<constant voltage zone 1 〉; the voltage of error voltage signal VEAO is higher than overcurrent protection reference voltage V LIMIT, and then drain current control circuit 5 compares voltage and the overcurrent protection reference voltage V LIMIT of the element current detection signal VCL of drain current testing circuit 4 outputs.Thereby in constant voltage zone 2, the peak current value that flows through the drain current ID of switch element 1 is fixed in order to the current value that overcurrent protection reference voltage V LIMIT is determined.
In addition, in this<constant voltage zone 2 〉, reach maximum though flow through the secondary current of secondary winding 110B, but, therefore export moment of output signal set_1 of moment specific output oscillator 6 of the output signal set_2 of secondary duty ratio restriction circuit 12 and want soon because the conducting duty ratio of secondary current reaches the setting of setting with secondary duty ratio restriction circuit 12.Therefore, the set end of trigger 15 is imported the output signal set_1 (asserts signal set) of oscillator 6.
And then,
The voltage of error voltage signal VEAO〉overcurrent protection reference voltage V LIMIT
State under,
Frequency of oscillation is adjusted circuit 7 poor according to the voltage of error voltage signal VEAO and overcurrent protection reference voltage V LIMIT, to the signal of the frequency of oscillation of oscillator 6 output raising switch elements 1.
Like this; in<constant voltage zone 2 〉; because load clock signal set_1 heavy more, that frequency of oscillation is high more becomes asserts signal set; the output signal of the drain current control circuit 5 that the voltage of element current detection signal VCL and overcurrent protection reference voltage V LIMIT is compared and export becomes reset signal reset, so this switching power unit becomes the state that moves with the frequency of oscillation control mode of constant peak electric current.
Also have, carry 132 output current IO and strengthen if flow through, though then the frequency of oscillation of switch element 1 improves, but since from secondary current by testing circuit 11 to the output signal D2_on of oscillator 6 output be high level during, do not export next single pulse signal set_1 from oscillator 6, so secondary current finishes the mobile next unbalanced pulse signal that produces afterwards.That is to say that this switching power unit becomes the discontinuous mode action.
<borderline region in (4) constant voltage zone 2 and constant current zone 〉
Figure 11 is the action timing diagram of the various piece of this switching power unit of expression<borderline region in constant voltage zone 2 and constant current zone 〉.So-called being somebody's turn to do<borderline region in constant voltage zone 2 and constant current zone 〉; be meant from the voltage of the error voltage signal VEAO of error amplifier 3 output and be higher than overcurrent protection reference voltage V LIMIT and be zone simultaneously constantly with rising edge from the 2nd clock signal set_2 of secondary duty ratio restriction circuit 12 outputs from the 1st clock signal set_1 of oscillator 6 outputs; that is, the conducting duty ratio of secondary current is the zone that reaches set point.
<constant voltage zone 2〉in; the peak current value that flows through the drain current ID of switch element 1 is fixed in order to the current value that overcurrent protection reference voltage V LIMIT is determined; frequency of oscillation is adjusted circuit 7 control generators 6, makes that along with load increases the weight of, the frequency of oscillation of clock signal set_1 improves.Thereby, in<constant voltage zone 2〉in, carry 132 output current IO and strengthen if flow through, then the frequency of oscillation of clock signal set_1 improves, and the conducting duty ratio of secondary current improves.
Then, if the conducting duty ratio of secondary current reaches the setting that secondary duty ratio restriction circuit 12 is set, output signal (single pulse signal) set2 of then secondary duty ratio restriction circuit 12 equates with the output time of output signal (single pulse signal) set_1 of oscillator 6.Thereby, this<borderline region in constant voltage zone 2 and constant current zone in, the conducting duty ratio of secondary current reaches the setting with 12 settings of secondary duty ratio restriction circuit.
Also have, because this switching power unit is the discontinuous mode action, therefore the energy of supplying with to load 132 can be expressed as follows with the peak current value Ip of inductance L p, the drain current ID of the elementary winding 110A of VD VO, output current IO, transformer 110 and the frequency of oscillation fosc of switch element 1
VO×IO=(1/2)×Lp×Ip×Ip×fosc ...(1)
This<borderline region in constant voltage zone 2 and constant current zone in; because the voltage of error voltage signal VEAO is higher than overcurrent protection reference voltage V LIMIT, so the peak current value Ip of drain current ID fixes in order to the current value that overcurrent protection reference voltage V LIMIT is determined.That is to say that when drain current ID reached the current value that is determined with overcurrent protection reference voltage V LIMIT, switch element 1 turn-offed.Then, because switch element 1 turn-offs and the peak current value of the current value when beginning to flow through secondary current in secondary winding 110B, secondary current becomes the current value that the turn ratio with the elementary winding 110A of transformer 110 and secondary winding 110B decides, so is certain.
Under VD VO is certain situation because the gradient of secondary current also be certain, so the peak current value of secondary current be regularly a secondary current flow through during be constant always.Thereby, this<borderline region in constant voltage zone 2 and constant current zone in, secondary current flow through during always for certain.Its result, in<borderline region in constant voltage zone 2 and constant current zone 〉, the frequency of oscillation of clock signal set_2 is a certain value always.That is to say, because at the borderline region in<constant voltage zone 2 and constant current zone〉in clock signal set_1 equate that with the frequency of oscillation of clock signal set_2 so the frequency of oscillation fosc of switch element 1 is a certain value always.
In addition, when the inductance L p of the elementary winding 110A of transformer 110 changes, because the gradient of secondary current also changes, therefore the peak current value when secondary current is a timing, if inductance L p strengthens, then the gradient of secondary current also becomes greatly, flow through secondary current during also extend.Its result, the frequency of oscillation of clock signal set_2 descends.That is to say, because clock signal set_1 equates that with the frequency of oscillation of clock signal set_2 therefore if inductance L p strengthens, then the frequency of oscillation fosc of switch element 1 descends in<borderline region in constant voltage zone 2 and constant current zone 〉.On the other hand, in contrast, if inductance L p reduces, then the frequency of oscillation fosc of switch element 1 improves.
As mentioned above, in<borderline region in constant voltage zone 2 and constant current zone 〉, because the product of the inductance L p of the elementary winding 110A of transformer 110 and the frequency of oscillation fosc of switch element 1 is certain, therefore according to the relation of above-mentioned (1) formula, output current IO is certain.Thereby, the borderline region in<constant voltage zone 2 and constant current zone〉in output current IO be not subjected to the influence of the error of the inductance value of transformer and frequency of oscillation.
<(5) constant current zone 〉
Figure 12 is the action timing diagram of this switching power unit of expression in the various piece in<constant current zone 〉.So-called should<constant current zone 〉, be meant the zone that is higher than overcurrent protection reference voltage V LIMIT and utilizes the clock signal set_2 of secondary duty ratio restriction circuit 12 outputs to carry out the switch motion of switch element 1 from the voltage of the error voltage signal VEAO of error amplifier 3 outputs.
If add heavy duty 132, make to flow through and carry 132 output current IO output current IO greater than<borderline region in constant voltage zone 2 and constant current zone 〉, then as mentioned above, because the peak current value of secondary current and the conducting duty ratio of secondary current have been certain, the energy of supplying with to secondary winding 110B is maximum, so VD VO descends.
If VD VO descends, then the gradient of secondary current strengthens, flow through secondary current during prolong, export moment of output signal (single pulse signal) set_1 of moment specific output oscillator 6 of output signal (single pulse signal) set2 of secondary duty ratio restriction circuit 12 and want slow.Therefore, select circuit 13 that output signal set_2 is exported from clock signal.
Owing to output signal set_2 output, make that the conducting duty ratio of secondary current is certain setting, it is constant therefore the conducting duty ratio of secondary current to be controlled at setting, and the frequency of oscillation of switch element 1 descends.
Thereby along with load increases the weight of, the conducting duty ratio of the peak current value of secondary current and secondary current still remains necessarily, and the frequency of oscillation of switch element 1 descends.
At this moment, when the conducting duty ratio of secondary current is setting, be D2 if establish the conducting duty ratio of secondary current, the peak current value of secondary current is I2p, then output current IO is represented with following formula.
IO=(1/2)×I2p×D2 ...(2)
Control in order to the current value that overcurrent protection reference voltage V LIMIT is determined owing to flow through the peak current value of the drain current of switch element 1, so the peak current value I2p of secondary current is certain.Thereby, irrelevant according to this switching power unit with the frequency of oscillation fosc of the inductance L p of the elementary winding 110A of transformer 110 and switch element 1, can access certain output current IO, can obtain very little, the high-precision constant current droop characteristic of error.
<(6) Off font protection zone 〉
Figure 13 is the action timing diagram of the various piece of this switching power unit of expression in<Off font protection zone 〉.So-called should<Off font protection zone 〉, be in<constant current zone〉in auxiliary power unit VCC be lower than the overcurrent protection reference voltage and adjust magnitude of voltage that circuit 16 sets and the zone of adjusting by 16 pairs of overcurrent protection reference voltage V of overcurrent protection reference voltage adjustment circuit LIMIT.
In<constant current zone 〉,, then constant and VD Vo and accessory power supply voltage VCC are constantly sagging thereupon keeping certain output current IO if the load of load 132 increases the weight of.And here, if accessory power supply voltage VCC is lower than the overcurrent protection reference voltage and adjusts the magnitude of voltage that circuit 16 is set, then the overcurrent protection reference voltage is adjusted the decline of circuit 16 along with accessory power supply voltage VCC, and overcurrent protection reference voltage V LIMIT is reduced.
Thus, descend owing to flow through the peak current value of peak current value and the secondary current that flows through secondary winding 110B of the drain current ID of switch element 1, therefore according to following formula (2), output current IO also reduces.According to this action, because the output current IO of VD VO when descending reduce, suppress output current IO very little during overload that therefore can be when load short circuits etc., can realize the protection of safe Off font.
For example, the set point of the overcurrent protection reference voltage being adjusted circuit 16 is set in<the constant voltage zone〉in about 30% (about 30% of the stable usefulness reference voltages of accessory power supply voltage VCC when stablize.Preferably 30%).According to such setting, because VD VO can make output current IO reduce after fully sagging, therefore can fully guarantee the sagging zone of constant current of charger, and the output current IO the during overload can fully reduce load short circuits the time etc.
In addition, for example overcurrent protection reference voltage adjustment circuit 16 constitutes like this, makes and can adjust overcurrent protection reference voltage V LIMIT to its peaked about 20% (being preferably 20%).Like this, because the output current IO during load short circuits also is about 20% of the output current IO in the sagging zone of constant current, the output current IO during overload in the time of therefore can be with load short circuits etc. suppresses enough for a short time, can realize the protection of safe Off font.
In addition, if VD VO descends, then because the conducting duty ratio of secondary current is controlled at setting, so the frequency of oscillation of switch element 1 reduces.Usually if frequency of oscillation reduces, enter voiced band, then can hear the magnetostriction noise of transformer, but in this switching power unit, if VD VO reduces, frequency of oscillation descends, then since the peak current value of drain current ID and the peak current value of secondary current also descend, therefore the decline of frequency of oscillation can be suppressed, voiced band can be prevented to enter.In addition, even under the situation that has entered voiced band,, therefore in fact can can't hear the magnetostriction noise because the peak current value of drain current ID and secondary current is very little.
As mentioned above,, can detect resistance and optical coupler, can realize high-precision constant current droop characteristic with low cost, minimum component number and minimum power consumption without constant-current control circuit, the output current of primary side according to present embodiment.Therefore, high-precision charger Switching Power Supply can be constituted, low cost, miniaturization, energy-conservationization of charger can be realized with Switching Power Supply with component number seldom.
In addition, in the constant current zone, the peak current value by making drain current and the peak current value of secondary current are constant, can make the conducting duty ratio of secondary current be controlled at setting, to realize the constant current droop characteristic.And then because the constant current value of output current is not subjected to the influence of error of the inductance of frequency of oscillation or transformer, the error of whole characteristic is very little, can realize high-precision constant current droop characteristic.
In addition, during underloading, owing to become the intermittent oscillation of the peak current value that reduces drain current, the output voltage in the time of therefore can suppressing underloading rises, and reduces power consumption, energy-conservationization in the time of also realizing standby.
In addition; during overload; owing to the decline of the peak current value that makes drain current along with output voltage descends; the conducting duty ratio of secondary current is controlled at setting; therefore the Off font defencive function that output voltage is more little, output current is also more little can be realized, safe supply unit can be constituted.
In addition, about switch element and control circuit,, therefore realize singualtion easily owing to can be arranged on in the semiconductor.Thereby, by main circuit elements device is arranged in the single semiconductor, can reduce the component number that forming circuit is used, can easily realize miniaturization and lightweight, and then reduce cost.
As mentioned above, the switching power unit of present embodiment can be realized high-precision constant current droop characteristic with low-cost and minimum component number, to mancarried devices such as mobile phone or digital cameras with charger etc. of great use.