CN100459157C - Thin film transistor structure for plane display device and its producing method - Google Patents
Thin film transistor structure for plane display device and its producing method Download PDFInfo
- Publication number
- CN100459157C CN100459157C CNB2004100579241A CN200410057924A CN100459157C CN 100459157 C CN100459157 C CN 100459157C CN B2004100579241 A CNB2004100579241 A CN B2004100579241A CN 200410057924 A CN200410057924 A CN 200410057924A CN 100459157 C CN100459157 C CN 100459157C
- Authority
- CN
- China
- Prior art keywords
- poly
- layer
- pattern layer
- silicon pattern
- film transistor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 239000010409 thin film Substances 0.000 title claims abstract description 80
- 238000000034 method Methods 0.000 title claims abstract description 30
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 95
- 239000012535 impurity Substances 0.000 claims abstract description 20
- 239000000758 substrate Substances 0.000 claims description 49
- 238000004519 manufacturing process Methods 0.000 claims description 20
- 229910021417 amorphous silicon Inorganic materials 0.000 claims description 19
- 239000010408 film Substances 0.000 claims description 4
- 238000005224 laser annealing Methods 0.000 claims description 4
- 229920005591 polysilicon Polymers 0.000 abstract description 12
- 239000010410 layer Substances 0.000 description 137
- 150000002500 ions Chemical class 0.000 description 31
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 12
- 238000005516 engineering process Methods 0.000 description 8
- 238000001259 photo etching Methods 0.000 description 8
- 239000011521 glass Substances 0.000 description 7
- 238000002425 crystallisation Methods 0.000 description 6
- 230000008025 crystallization Effects 0.000 description 6
- 239000011248 coating agent Substances 0.000 description 5
- 238000000576 coating method Methods 0.000 description 5
- 229910052581 Si3N4 Inorganic materials 0.000 description 4
- 230000015572 biosynthetic process Effects 0.000 description 4
- 230000000694 effects Effects 0.000 description 4
- 229910052751 metal Inorganic materials 0.000 description 4
- 239000002184 metal Substances 0.000 description 4
- 238000000059 patterning Methods 0.000 description 4
- -1 phosphonium ion Chemical class 0.000 description 4
- 239000000377 silicon dioxide Substances 0.000 description 4
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 4
- 229910052796 boron Inorganic materials 0.000 description 3
- 238000005229 chemical vapour deposition Methods 0.000 description 3
- 238000002347 injection Methods 0.000 description 3
- 239000007924 injection Substances 0.000 description 3
- HAYXDMNJJFVXCI-UHFFFAOYSA-N arsenic(5+) Chemical compound [As+5] HAYXDMNJJFVXCI-UHFFFAOYSA-N 0.000 description 2
- HPNSNYBUADCFDR-UHFFFAOYSA-N chromafenozide Chemical compound CC1=CC(C)=CC(C(=O)N(NC(=O)C=2C(=C3CCCOC3=CC=2)C)C(C)(C)C)=C1 HPNSNYBUADCFDR-UHFFFAOYSA-N 0.000 description 2
- 238000010276 construction Methods 0.000 description 2
- 238000005137 deposition process Methods 0.000 description 2
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 2
- 239000011159 matrix material Substances 0.000 description 2
- 229920002120 photoresistant polymer Polymers 0.000 description 2
- 239000010453 quartz Substances 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- 239000002210 silicon-based material Substances 0.000 description 2
- 239000002356 single layer Substances 0.000 description 2
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 2
- 229910052721 tungsten Inorganic materials 0.000 description 2
- 239000010937 tungsten Substances 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- 239000013039 cover film Substances 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000001788 irregular Effects 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
Images
Landscapes
- Thin Film Transistor (AREA)
Abstract
The invention provides a method for forming thin film transistor with different electrical characteristics on base board with a driving circuit area and an image element area. First and second polysilicon pattern layers are formed separately above driving circuit area and image element area of the base board, a mask layer covers on first polysilicon pattern layer, it is used as injecting mask to proceed first ion injecting process to second polysilicon pattern layer to make impurity concentration of first polysilicon pattern layer being defferent from second polysilicon pattern layer. After mask layer being removed, a grid dielectric layer and a grid electrode are formed one by one on first and second polysilicon pattern layers separately, and a source electrode/drain electrode area is formed and a channel are is defined.
Description
Technical field
The present invention relates to a kind of flat display apparatus, particularly relate to a kind of thin-film transistor (thin film transistor that is used for flat display apparatus, TFT) structure, it has different electrical characteristics (electrical characteristic) in pixel region and drive circuit area.
Background technology
In recent years, (flat panel display, demand FPD) constantly increased active matric (active-matrix) flat-panel screens, thereby was badly in need of the manufacturing technology that development is used for the thin-film transistor (TFT) of active matric flat display apparatus.In traditional thin-film transistor manufacturing technology, adopt the amorphous silicon layer be formed on the glass substrate channel layer as thin-film transistor.
Amorphous silicon material is compared to polycrystalline silicon material, the little and irregular alignment of its crystal grain (grain), cause the electronics locomotivity to reduce and the usefulness that makes thin-film transistor with reduction.Generally speaking, the locomotivity of electronics in polysilicon layer is more than 100 times of amorphous silicon layer.In semiconductor process techniques, polysilicon layer is usually by the tempering program of low-pressure chemical vapor deposition (LPCVD) and 900 ℃ and form it.Apparently, this kind mode also can't be applied in the Display Technique of plane, because the temperature that glass can bear only has only 650 ℃.Therefore, (low temperature polysilicon, LTPS) technology becomes a kind of emerging technology to low temperature polycrystalline silicon, is used for the manufacturing of flat display apparatus thin-film transistor.The LTPS technology can be integrated drive circuit on the glass substrate with pixel, uses the reduction manufacturing cost.
Yet, active array formula organic light emitting display (active-matrix organic light emittingdisplay, AMOLED) in, the electrical characteristics of the thin-film transistor of drive circuit are different from the thin-film transistor of pixel region.For example, the P type thin-film transistor (PTFT) of drive circuit needs unanimous on the whole with starting voltage (threshold voltage) absolute value of N type thin-film transistor (NTFT).For in the pixel region as for the PTFT of Organic Light Emitting Diode switch element, then need have less starting voltage, with the effect that reaches power saving and prolong the Organic Light Emitting Diode life-span.Therefore in the LTPS technology, be difficult in drive circuit area and pixel region and produce thin-film transistor simultaneously with required electrical characteristics.
Summary of the invention
In view of this, the object of the present invention is to provide a kind of thin-film transistor structure and manufacture method thereof that is used for flat display apparatus, it is by adopting a mask layer to carry out passage doping process (channeldoping), uses the thin-film transistor that pixel region on same substrate and drive circuit area form different electrical characteristics.
According to above-mentioned purpose, the invention provides a kind of thin-film transistor structure that is used for flat display apparatus, it comprises: one has the substrate of an one drive circuit district and a pixel region, at least one the first film transistor and at least one second thin-film transistor.The first film transistor is arranged on the drive circuit area of substrate, it comprises a first grid electrode, one first source/drain regions, reaches a first passage district, second thin-film transistor then is arranged on the pixel region of substrate, and it comprises a second grid electrode, one second source/drain regions, reaches a second channel district.Wherein, electrical (conductivity) of first and second thin-film transistor is identical, and the impurity concentration in first passage district is different from the second channel district.
According to above-mentioned purpose, the invention provides a kind of thin-film transistor structure manufacture method that is used for flat display apparatus again.One substrate with drive circuit area and pixel region is provided.Above the drive circuit area of substrate, form one first poly-silicon pattern layer and above pixel region, form one second poly-silicon pattern layer simultaneously.Above the drive circuit area of substrate, form a mask layer and expose the second poly-silicon pattern layer to cover the first poly-silicon pattern layer.Utilize mask layer to come the second poly-silicon pattern layer that exposes is carried out one first ion injecting program, make the impurity concentration of the first poly-silicon pattern layer be different from the second poly-silicon pattern layer as injecting mask.After removing this mask layer, respectively first and this second poly-silicon pattern layer above form a gate dielectric and a gate electrode in regular turn.Utilize each gate electrode as injecting mask come to first and this second poly-silicon pattern layer carry out one second ion injecting program, to form source respectively therein and to define a channel region.
According to above-mentioned purpose, the invention provides the thin-film transistor structure manufacture method that another kind is used for flat display apparatus again.One substrate with drive circuit area and pixel region is provided.Above the drive circuit area of substrate, form one first poly-silicon pattern layer and above pixel region, form one second poly-silicon pattern layer simultaneously.First and second poly-silicon pattern layer is carried out one first type ion injecting program.Above the pixel region of substrate, form a mask layer to cover the second poly-silicon pattern layer and to expose the first poly-silicon pattern layer.Utilize mask layer to come the first poly-silicon pattern layer that exposes is carried out the second type ion injecting program in contrast to the first type ion injecting program, make the impurity concentration of the first poly-silicon pattern layer be different from the second poly-silicon pattern layer as injecting mask.After removing mask layer, above first and second poly-silicon pattern layer, form a gate dielectric and a gate electrode respectively in regular turn.Utilize each gate electrode to come first and second poly-silicon pattern layer is carried out source ion injecting program, to form source respectively therein and to define a channel region as injecting mask.
Moreover the first type ion injecting program is any of a N type ion injecting program and P type ion injecting program.
For above-mentioned purpose of the present invention, feature and advantage can be become apparent, preferred embodiment cited below particularly, and conjunction with figs. elaborates.
Description of drawings
Figure 1A to 1F shows the manufacture method according to the thin-film transistor structure that is used for flat display apparatus of first embodiment of the invention.
Fig. 2 A to 2G shows the manufacture method according to the thin-film transistor structure that is used for flat display apparatus of second embodiment of the invention.
The simple symbol explanation
10～drive circuit area; 20～pixel region; 100～substrate; 102～resilient coating; 104～amorphous silicon layer; 106～crystallization treatment; 108～polysilicon layer; 108a, 108c, the 108d～first poly-silicon pattern layer; 108b～second poly-silicon pattern the layer; 110～mask layer; 112,113,118～ion injecting program; 114～dielectric layer; 116a, 116b～gate electrode; 120a～the first film transistor; 120b～second thin-film transistor; 119a, 123a～source area; 119b, 123b～drain region; 121,125～channel region; 126～inner layer dielectric layer; 127a, 127b, 129a, 129b～intraconnections.
Embodiment
In with the formed flat-panel screens of low temperature polycrystalline silicon (LTPS) technology, active array formula organic light emitting display (AMOLED) for example, drive circuit can be integrated on the glass substrate to reduce cost of manufacture.Yet as described above, the electrical characteristics of the thin-film transistor in the drive circuit also are different from the thin-film transistor of pixel region.In order to meet the electrical characteristics demand of the thin-film transistor on drive circuit area and the pixel region simultaneously, can be after finishing the thin-film transistor making, form the channel region of different impurities concentration, make the thin-film transistor starting voltage of drive circuit area be different from the thin-film transistor of pixel region.That is, when utilizing LTPS fabrication techniques thin-film transistor, can produce thin-film transistor simultaneously in drive circuit area and pixel region with required electrical characteristics.
First embodiment
The manufacture method that below cooperates the thin-film transistor structure that is used for flat display apparatus of Figure 1A to 1F explanation first embodiment of the invention.At first, please refer to Figure 1A, a substrate 100 is provided, it has an one drive circuit district 10 and a pixel region 20.This substrate 100 can be a glass substrate, quartz base plate or plastic substrate.Then, above substrate 100, form an amorphous silicon (amorphous silicon) layer 104.Amorphous silicon layer 104 is for the usefulness of the channel layer of follow-up making thin-film transistor, its can by chemical vapour deposition technique (chemical vapor deposition, CVD) or other deposition process form it, and its thickness is about 300 to 1000 dusts
Scope.In order to increase the tack between amorphous silicon layer 104 and the substrate 100, can between substrate 100 and amorphous silicon layer 104, form a resilient coating 102 herein.Resilient coating 102 can be a single layer structure, for example one silica layer, or sandwich construction, and the silicon oxide layer above for example being positioned at by a silicon nitride layer and is constituted.
Next, please refer to Figure 1B, the amorphous silicon layer 104 of substrate 100 tops is carried out crystallization treatment 106, make original amorphous silicon layer 104 be transformed into polysilicon layer 108.This crystallization treatment 106 can be a laser annealing and handles, and the type of laser can be excimer laser (excimer laser), continuous wave laser (continue wave laser) or laser beam pulses (laser beam plus).Because crystallization treatment 106 temperature are below 600 ℃, so be applicable to transparent glass substrate.
Next, please refer to Fig. 1 C, by existing photoetching and etch process, above the drive circuit area 10 of substrate 100, to form at least one first poly-silicon pattern layer 108a and above pixel region 20, to form at least one second poly-silicon pattern layer 108b simultaneously.Then, carry out the committed step of present embodiment, form a mask layer 110 above the drive circuit area 10 of substrate 100, for example a photoresist layer exposes the second poly-silicon pattern layer 108b that is positioned at pixel region 20 tops to cover the first poly-silicon pattern layer 108a.Then, utilize mask layer 110, the second poly-silicon pattern layer 108b that exposes carried out one first ion injecting program 112 (passage doping program) as injecting mask.Herein, the element of ion injection depends on that the thin-film transistor of follow-up formation is electrical.For example, if N type thin-film transistor, then the element of ion injection can be phosphonium ion or arsenic ion.On the contrary, if P type thin-film transistor then the element that injects of ion can be the boron ion.Thus, the impurity concentration of the first poly-silicon pattern layer 108a is different from the second poly-silicon pattern layer 108b.Because 110 covering of the masked layer of the first poly-silicon pattern layer 108a, therefore the impurity concentration of the first poly-silicon pattern layer 108a can be lower than the second poly-silicon pattern layer 108b.In the present embodiment, to form P type thin-film transistor as example.
Next, please refer to Fig. 1 D, remove mask layer 110.Afterwards, form a dielectric layer 114 above substrate 100, for example an one silica layer or a silicon nitride layer are to cover first and second poly-silicon pattern layer 108a and 108b.This dielectric layer 114 is as a gate dielectric.Then, on dielectric layer 114, form a conductive layer (not illustrating), for example doped polycrystalline silicon layer or metal level.Afterwards, utilize existing photoetching and etch process to come this conductive layer of patterning, above first and second poly- silicon pattern layer 108a and 108b, to form gate electrode 116a and 116b respectively respectively.
Next, please refer to Fig. 1 E, utilize gate electrode 116a and 116b to come first and second poly- silicon pattern layer 108a and 108b are carried out one second ion injecting program (source/drain injection) 118 as injecting mask, also therebetween define a channel region 121 with a formation one source pole district 119a and a drain region 119b in the first poly-silicon pattern floor 108a, and in the second poly-silicon pattern floor 108b, form an one source pole district 123a and a drain region 123b and therebetween define a channel region 125.Thus, just can above drive circuit area 10 and pixel region 20, form thin- film transistor 120a and 120b respectively with identical electrical (P type).The channel region 121 and 125 that is noted that the thin-film transistor 120a of drive circuit area 10 and pixel region 20 tops and 120b has different impurity concentrations because of the first ion injecting program 112 (shown in Fig. 1 C).Therefore, the starting voltage of the P type thin-film transistor 120b of pixel region 20 can reduce because of the first ion injecting program 112.When its as active array formula organic light emitting display in during the switch element of Organic Light Emitting Diode, the effect that can reach power saving and prolong the Organic Light Emitting Diode life-span.Moreover the thin-film transistor of drive circuit area 10 is not subjected to the effect of the first ion injecting program 112, makes that the starting voltage absolute value of P type thin-film transistor 120b on it and N type thin-film transistor (not illustrating) is unanimous on the whole.
At last, please refer to Fig. 1 F, above dielectric layer 114 and each gate electrode 116a and 116b, cover an inner layer dielectric layer 126.Afterwards, utilize existing photoetching and etch process with patterning inner layer dielectric layer 126, and form a plurality of holes therein, and expose source area 119a and 123a and drain region 119b and 123b.Then, on inner layer dielectric layer 126, form a conductive layer (not illustrating), tungsten metal level for example, and insert in each hole.Afterwards, utilize existing photoetching and etching program, forming intraconnections 127a and 127b above the source area 119a of drive circuit area 10 and the drain region 119b respectively and above the source area 123a of pixel region 20 and drain region 123b, forming intraconnections 129a and 129b.Thus, just can finish the thin-film transistor structure with different electrical characteristics of the present invention.
Second embodiment
Below cooperate the manufacture method of the thin-film transistor structure that is used for flat display apparatus of Fig. 2 A to 2G explanation second embodiment of the invention, the parts that wherein are same as first embodiment use identical label.At first, please refer to Fig. 2 A, a substrate 100 is provided, it has an one drive circuit district 10 and a pixel region 20.This substrate 100 can be a glass substrate, quartz base plate or plastic substrate.Then, above substrate 100, form an amorphous silicon layer 104.Amorphous silicon layer 104 is for the usefulness of the channel layer of follow-up making thin-film transistor, and it can form it by chemical vapour deposition technique or other deposition process, and its thickness is about the scope of 300 to 1000 dusts.In order to increase the tack between amorphous silicon layer 104 and the substrate 100, can between substrate 100 and amorphous silicon layer 104, form a resilient coating 102 herein.Resilient coating 102 can be a single layer structure, for example one silica layer, or sandwich construction, and the silicon oxide layer above for example being positioned at by a silicon nitride layer and is constituted.
Next, please refer to Fig. 2 B, the amorphous silicon layer 104 of substrate 100 tops is carried out crystallization treatment 106, make original amorphous silicon layer 104 be transformed into polysilicon layer 108.This crystallization treatment 106 can be a laser annealing and handles, and the type of laser can be excimer laser, continuous wave laser or laser beam pulses.
Next, please refer to Fig. 2 C, by existing photoetching and etch process, above the drive circuit area 10 of substrate 100, to form at least one first poly-silicon pattern layer 108c and above pixel region 20, to form at least one second poly-silicon pattern layer 108b simultaneously.
Then, carry out the committed step of present embodiment, first and second poly- silicon pattern layer 108c and 108b are carried out one first type ion injecting program (passage doping program) 112.As described in first embodiment, the element that ion injects depends on that the thin-film transistor of follow-up formation is electrical.For example, if N type thin-film transistor, then the first type ion injecting program 112 can be phosphonium ion or arsenic ion injecting program.On the contrary, if P type thin-film transistor, then the first type ion injecting program 112 can be boron ion injecting program.In the present embodiment, to form P type thin-film transistor as example.Afterwards, form a mask layer 110 above the pixel region 20 of substrate 100, for example a photoresist layer exposes the first poly-silicon pattern layer 108c that is positioned at drive circuit area 10 tops to cover the second poly-silicon pattern layer 108b.Then, utilize mask layer 110 as injecting mask, come the second poly-silicon pattern layer 108c that exposes carried out the second type ion injecting program 113 in contrast to the first type ion injecting program 112, use forming the first poly-silicon pattern layer 108d that comprises P type and N type impurity, shown in Fig. 2 D.
In the present embodiment, to form P type thin-film transistor as example, so the first type ion injecting program 112 can be boron (P type) ion injecting program, and the second type ion injecting program 113 can be phosphorus or arsenic (N type) ion injecting program.Thus, the impurity concentration of the first poly-silicon pattern layer 108d is different from the second poly-silicon pattern layer 108b.Because 110 covering of the masked layer of the second poly-silicon pattern layer 108b, therefore the impurity concentration of the first poly-silicon pattern layer 108d can be higher than the second poly-silicon pattern layer 108b.
Next, please refer to Fig. 2 E, remove mask layer 110.Afterwards, form a dielectric layer 102 above substrate 100, for example an one silica layer or a silicon nitride layer are to cover first and second poly-silicon pattern layer 108d and 108b.This dielectric layer 102 is as a gate dielectric.Then, on dielectric layer 102, form a conductive layer (not illustrating), for example doped polycrystalline silicon layer or metal level.Afterwards, utilize existing photoetching and etch process to come this conductive layer of patterning, above first and second poly- silicon pattern layer 108d and 108b, to form gate electrode 116a and 116b respectively respectively.
Next, please refer to Fig. 2 F, utilize gate electrode 116a and 116b to come first and second poly- silicon pattern layer 108d and 108b are carried out source ion injecting program 118 as injecting mask, also therebetween define a channel region 121 with a formation one source pole district 119a and a drain region 119b in the first poly-silicon pattern floor 108d, and in the second poly-silicon pattern floor 108b, form an one source pole district 123a and a drain region 123b and therebetween define a channel region 125.Thus, just can above drive circuit area 10 and pixel region 20, form thin- film transistor 120a and 120b with identical electrical (P type).The channel region 121 and 125 that is noted that the thin-film transistor 120a of drive circuit area 10 and pixel region 20 tops and 120b has different impurity concentrations because of ion injecting program 112 and 113 (shown in Fig. 2 C to 2D).Therefore, the starting voltage of the P type thin-film transistor 120b of pixel region 20 can reduce because of the first type ion injecting program 112.When its as active array formula organic light emitting display in during the switch element of Organic Light Emitting Diode, the effect that can reach power saving and prolong the Organic Light Emitting Diode life-span.Moreover, being positioned at the thin-film transistor 120a of drive circuit area 20, its channel region contains P type and N type impurity, makes that the starting voltage absolute value of P type thin-film transistor 120a on it and N type thin-film transistor (not illustrating) is unanimous on the whole.
At last, please refer to Fig. 2 G, above dielectric layer 114 and each gate electrode 116a and 116b, cover an inner layer dielectric layer 126.Afterwards, utilize existing photoetching and etch process with patterning inner layer dielectric layer 126, and form a plurality of holes therein, and expose source area 119a and 123a and drain region 119b and 123b.Then, on inner layer dielectric layer 126, form a conductive layer (not illustrating), tungsten metal level for example, and insert in each hole.Afterwards, utilize existing photoetching and etching program, forming intraconnections 127a and 127b above the source area 119a of drive circuit area 10 and the drain region 119b respectively and above the source area 123a of pixel region 20 and drain region 123b, forming intraconnections 129a and 129b.Thus, just can finish the thin-film transistor structure with different electrical characteristics of the present invention.
Please refer to Fig. 1 F or 2G, it shows the thin-film transistor structure generalized section that is used for flat-panel screens according to the embodiment of the invention.This thin-film transistor structure comprises: substrate 100, thin- film transistor 120a and 120b, an inner layer dielectric layer 126 and intraconnections 127a, the 127b with drive circuit area 10 and pixel region 20,129a, and 129b.Thin-film transistor 120a is arranged on the drive circuit area 10 of substrate 100, and it comprises a gate electrode 116a and contains source area 119a, drain region 119b, and first poly-silicon pattern layer 108a or the 108d of channel region 121.Thin-film transistor 120b then is arranged on the pixel region 20 of substrate 100, and it comprises a gate electrode 116b and contains source area 123a, drain region 123b, and the second poly-silicon pattern layer 108b of channel region 125.Inner layer dielectric layer 126, cover film transistor 120a and 120b, it has a plurality of holes to expose source area 119a and 123a and drain region 119b and 123b.Intraconnections 127a and 127b are arranged in the hole of source area 119a and drain region 119b top to be electrically connected with it. Intraconnections 129a and 129b are arranged in the hole of source area 123a and drain region 123b top to be electrically connected with it.
Thin- film transistor 120a and 120b's is electrically identical, for example be P type thin-film transistor or N type thin-film transistor, and the impurity concentration of channel region 121 is different from channel region 125.In first embodiment, the impurity concentration of channel region 121 is lower than channel region 125.In addition, in a second embodiment, the impurity concentration of channel region 121 can be higher than channel region 125.
Though the present invention discloses as above with preferred embodiment; yet it is not in order to limit the present invention; those skilled in the art can do a little change and retouching without departing from the spirit and scope of the present invention, thus protection scope of the present invention should with accompanying Claim the person of being defined be as the criterion.
Claims (8)
1, a kind of thin-film transistor structure that is used for flat display apparatus comprises:
One substrate, it has an one drive circuit district and a pixel region;
At least one the first film transistor is arranged on this drive circuit area of this substrate, and it comprises a first grid electrode, one first source/drain regions, reaches a first passage district; And
At least one second thin-film transistor is arranged on this pixel region of this substrate, and it comprises a second grid electrode, one second source/drain regions, reaches a second channel district;
Wherein this first and this second thin-film transistor electrically identical, and the impurity concentration in this first passage district is lower than this second channel district.
2, the thin-film transistor structure that is used for flat display apparatus as claimed in claim 1 also comprises:
One inner layer dielectric layer, cover this first and this second thin-film transistor, its have a plurality of holes with expose this first and this second source/drain regions;
One first intraconnections is arranged in this hole of this first source/drain regions top to be electrically connected with it; And
One second intraconnections is arranged in this hole of this second source/drain regions top to be electrically connected with it.
3, a kind of manufacture method that is used for the thin-film transistor structure of flat display apparatus comprises the following steps:
One substrate is provided, and it has an one drive circuit district and a pixel region;
Above this drive circuit area of this substrate, form one first poly-silicon pattern layer and above this pixel region, form one second poly-silicon pattern layer simultaneously;
Above this drive circuit area of this substrate, form a mask layer and expose this second poly-silicon pattern layer to cover this first poly-silicon pattern layer;
Utilize this mask layer to come this second poly-silicon pattern layer that exposes is carried out one first ion injecting program, make the impurity concentration of this first poly-silicon pattern layer be different from this second poly-silicon pattern layer as injecting mask;
Remove this mask layer;
Respectively this first and this second poly-silicon pattern layer above form a gate dielectric and a gate electrode in regular turn;
Utilize each gate electrode as injecting mask come to this first and this second poly-silicon pattern layer carry out one second ion injecting program, forming source respectively therein and to define a channel region,
Wherein before carrying out this second ion injecting program, the impurity concentration of this first poly-silicon pattern layer is lower than this second poly-silicon pattern layer.
4, the thin-film transistor structure manufacture method that is used for flat display apparatus as claimed in claim 3 also comprises the following steps:
Cover an inner layer dielectric layer above each gate electrode, it has a plurality of holes to expose each source/drain regions; And
In each hole, insert a conductive layer, with as an intraconnections.
5, the thin-film transistor structure manufacture method that is used for flat display apparatus as claimed in claim 3, wherein this first and this second poly-silicon pattern layer by amorphous silicon layer being carried out quasi-molecule laser annealing and forming.
6, a kind of manufacture method that is used for the thin-film transistor structure of flat display apparatus comprises the following steps:
One substrate is provided, and it has an one drive circuit district and a pixel region;
Above this drive circuit area of this substrate, form one first poly-silicon pattern layer and above this pixel region, form one second poly-silicon pattern layer simultaneously;
To this first and this second poly-silicon pattern layer carry out one first type ion injecting program;
Above this pixel region of this substrate, form a mask layer to cover this second poly-silicon pattern layer and to expose this first poly-silicon pattern layer;
Utilize this mask layer to come this first poly-silicon pattern layer that exposes is carried out the second type ion injecting program in contrast to this first type ion injecting program, make the impurity concentration of this first poly-silicon pattern layer be lower than this second poly-silicon pattern layer as injecting mask;
Remove this mask layer;
Respectively this first and this second poly-silicon pattern layer above form a gate dielectric and a gate electrode in regular turn;
Utilize each gate electrode as injecting mask come to this first and this second poly-silicon pattern layer carry out source ion injecting program, to form source respectively therein and to define a channel region.
7, the thin-film transistor structure manufacture method that is used for flat display apparatus as claimed in claim 6 also comprises the following steps:
Cover an inner layer dielectric layer above each gate electrode, it has a plurality of holes to expose each source/drain regions; And
In each hole, insert a conductive layer, with as an intraconnections.
8, the thin-film transistor structure manufacture method that is used for flat display apparatus as claimed in claim 6, wherein this first and this second poly-silicon pattern layer by amorphous silicon layer being carried out quasi-molecule laser annealing and forming.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2004100579241A CN100459157C (en) | 2004-08-26 | 2004-08-26 | Thin film transistor structure for plane display device and its producing method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2004100579241A CN100459157C (en) | 2004-08-26 | 2004-08-26 | Thin film transistor structure for plane display device and its producing method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1588644A CN1588644A (en) | 2005-03-02 |
| CN100459157C true CN100459157C (en) | 2009-02-04 |
Family
ID=34603301
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB2004100579241A Expired - Fee Related CN100459157C (en) | 2004-08-26 | 2004-08-26 | Thin film transistor structure for plane display device and its producing method |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN100459157C (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100399574C (en) * | 2006-01-24 | 2008-07-02 | 友达光电股份有限公司 | Organic light-emitting diode display panel and its polysilicon channel layer forming method |
| CN104599959A (en) * | 2014-12-24 | 2015-05-06 | 深圳市华星光电技术有限公司 | Manufacturing method and structure of low-temperature polycrystalline silicon TFT substrate |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2000114537A (en) * | 1998-10-07 | 2000-04-21 | Toshiba Corp | Semiconductor device and manufacture thereof |
| JP2000315798A (en) * | 1999-03-04 | 2000-11-14 | Semiconductor Energy Lab Co Ltd | Semiconductor device and its manufacture |
| JP2000353811A (en) * | 1999-04-07 | 2000-12-19 | Semiconductor Energy Lab Co Ltd | Electro-optic device and manufacture thereof |
| US6613620B2 (en) * | 2000-07-31 | 2003-09-02 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and method of manufacturing the same |
| US20040124418A1 (en) * | 2000-11-28 | 2004-07-01 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and method of manufacturing the same |
-
2004
- 2004-08-26 CN CNB2004100579241A patent/CN100459157C/en not_active Expired - Fee Related
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2000114537A (en) * | 1998-10-07 | 2000-04-21 | Toshiba Corp | Semiconductor device and manufacture thereof |
| JP2000315798A (en) * | 1999-03-04 | 2000-11-14 | Semiconductor Energy Lab Co Ltd | Semiconductor device and its manufacture |
| JP2000353811A (en) * | 1999-04-07 | 2000-12-19 | Semiconductor Energy Lab Co Ltd | Electro-optic device and manufacture thereof |
| US6613620B2 (en) * | 2000-07-31 | 2003-09-02 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and method of manufacturing the same |
| US20040124418A1 (en) * | 2000-11-28 | 2004-07-01 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and method of manufacturing the same |
Also Published As
| Publication number | Publication date |
|---|---|
| CN1588644A (en) | 2005-03-02 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US7323716B2 (en) | Manufacturing method of thin film transistor substrate | |
| KR100915159B1 (en) | Display Device and Method of Producing The Same | |
| US20100133541A1 (en) | Thin film transistor array substrate, its manufacturing method, and liquid crystal display device | |
| WO2017070868A1 (en) | Manufacturing method for n-type tft | |
| US20080299693A1 (en) | Manufacturing method for display device | |
| KR100458710B1 (en) | A Crystalline Silicon Thin Film Transistor Panel for OELD and a Fabrication Method Thereof | |
| US6818967B2 (en) | Fabricating method of low temperature poly-silicon film and low temperature poly-silicon thin film transistor | |
| JP2008147516A (en) | Thin film transistor and its manufacturing method | |
| WO2019200824A1 (en) | Method for manufacturing ltps tft substrate and ltps tft substrate | |
| JP2009099824A (en) | Thin-film transistor device, display device and method of manufacturing the same | |
| US7012302B2 (en) | Complementary thin film transistor circuit, electro-optical device, and electronic apparatus | |
| US7256457B2 (en) | Thin-film transistor device, utilizing different types of thin film transistors | |
| US7923725B2 (en) | Semiconductor device and a method of manufacturing the same | |
| US7381596B2 (en) | Method of manufacturing an AMOLED | |
| CN100459157C (en) | Thin film transistor structure for plane display device and its producing method | |
| US7459351B2 (en) | Method of manufacturing an AMOLED | |
| US7851282B2 (en) | Method for forming thin film devices for flat panel displays | |
| CN102222644A (en) | Method for manufacturing active matrix organic light-emitting diode (AMOLED) apparatus | |
| US8759166B2 (en) | Method for manufacturing thin film transistor device | |
| KR20070002771A (en) | Thin film transistor plate and method of fabricating the same | |
| KR101172015B1 (en) | Thin film transistor plate and method of fabricating the same | |
| CN109256429B (en) | Oxide semiconductor thin film transistor and manufacturing method thereof | |
| JP2005243938A (en) | Thin-film transistor and its manufacturing method | |
| KR101258080B1 (en) | Liquid crystal display device and method for fabricating thereof | |
| KR100719690B1 (en) | Manufacturing Method of Thin Film Transistor |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20090204 |