CN100454438C - DDR memory controller and matrix line access method for matrix transposition - Google Patents
DDR memory controller and matrix line access method for matrix transposition Download PDFInfo
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Abstract
The present invention discloses a DDR memory controller for matrix transposition, which is suitable for a DDR SDRAM memory. The present invention comprises a data channel, an address generation unit, a work mode configuration unit, a central control unit, a clock unit, a data reading bus, a data writing bus, an address bus, a configuration bus and a control bus, and also comprises an interface unit of storage granules A, and an interface unit of storage granules B. The present invention also provides a matrix row and array access method, and can completely hide the operation cost of DDR granules to realize uninterrupted data transmission. Besides, the present invention can fully utilize the characteristics of a double data rate of the DDR granules when the DDR memory controller completes matrix row access and matrix array access.
Description
Technical field
The present invention relates to the memory controller of DDR SDRAM, particularly be fit to the DDR memory controller and the row matrix column access method of matrix transpose.
Background technology
The storer that is made of Double Data Rate Synchronous Dynamic Random Access Memory (hereinafter to be referred as DDR SDRAM) particle has been applied in many array signal processing systems widely, the advantage of this class storer is that memory capacity is big, and can finish respectively at the rising edge of a clock period and negative edge and once read or write operation.
But the read-write of DDR SDRAM particle need be deferred to its specific operation: particle needs periodic refreshing; Read-write operation need at first be opened row; Only continuous reading or write operation can be in delegation, finished, the random read-write of any memory location can not be supported; Need to close the row of opening after read-write operation is finished, and it is carried out charging (percharge) operation.These expenses have caused DDR SDRAM storage system in data are used with the Array Signal Processing of matrix-style tissue, be difficult to take into account row access efficient and column access efficient, particularly in needs are finished the application of matrix transpose operation, can not bring into play DDR SDRAM and can in a clock period, finish and read for 2 times or the characteristic of write operation.
As shown in Figure 1, two-dimensional matrix has row element { A1, A2, A3 ..., { B1, B2, B3 ... Have column element { A1, B1, C1 ..., { A2, B2, C2 ... ...Matrix shown in Figure 1 there are two kinds of storage modes in existing DDR SDRAM storage system: store according to the row element storage with according to column element.Be stored in existing DDR SDARM storage system according to row element, storage space as shown in Figure 2; Be stored in existing DDR SDARM storage system according to column element, storage space as shown in Figure 3.Two kinds of storage modes all can not be taken into account row access efficient and column access efficient.Be stored as example with row element: because the storage of row element is continuous, so when pressing row access, the element of each row can be read and write fast; And column element storage is discontinuous, and this has just caused by the column access inefficiency, particularly can't utilize DDR SDRAM particle can finish continuous reading for 2 times or the characteristic of write operation in a clock period.
In the prior art, also do not have to give full play to DDR SDRAM particle 2 haplotype data rate characteristics, and hide the memory controller and the row matrix column access method of the support transpose process of visit expense.
Summary of the invention
The objective of the invention is to have the shortcoming that is difficult to take into account row matrix access efficiency and rectangular array access efficiency that exists in the DDR SDRAM storage system now, a kind of DDR SDRAM memory controller and the row matrix column access method that can finish the array signal matrix transpose operation efficiently is provided in order to overcome.
To achieve these goals, the invention provides a kind of DDR memory controller of suitable matrix transpose, be used for DDR SDRAM storer, comprise: data channel 3, scalar/vector 4, mode of operation dispensing unit 5, centralized control unit 6, clock unit 7, read data bus 8, write data bus 9, address bus 10, configuration bus 11 and control bus 12, also comprise storage particle A interface unit 1, storage particle B interface unit 2, described storage particle A interface unit 1, storage particle B interface unit 2 is connected with described write data bus 9 by described read data bus 8 with described data channel 3; Described storage particle A interface unit 1, storage particle B interface unit 2 are connected by address bus 10 with described scalar/vector 4; Described storage particle A interface unit 1, storage particle B interface unit 2 are connected by described configuration bus 11 with described mode of operation dispensing unit 5; Described centralized control unit 6 is connected with storage particle A interface unit 1, storage particle B interface unit 2, data channel 3, scalar/vector 4, mode of operation dispensing unit 5 by control bus 12; Described clock unit 7 provides the clock signal of need of work for whole memory controller.
In the technique scheme, described storage particle A interface unit 1 is two separate and function is identical storage particle interface units with storage particle B interface unit 2, they connect the DDR particle, produce the sequential that meets the DDR particle requirement, finish the various operations to the DDR particle; And the address that sends by address bus 10 receiver address generation units 4, by read data bus 8, write data bus 9 and data channel 3 transmission data, receive the configuration order that mode of operation dispensing units 5 send by configuration bus 11, the read write command that sends by control bus 12 receiving center control modules 6; When making storage operation, by described storage particle A interface unit 1 of centralized control unit 6 controls and unit 2 alternations of storage particle B interface, hide the operation overhead of DDR particle, guarantee that the data in the data channel 3 continue to flow.
A kind of row matrix column access method of utilizing the DDR memory controller comprises:
1), according to the size of the model of DDR SDRAM storer and the matrix that will store, matrix is divided into a plurality of, make 1 row size of the size of each piece and DDR SDRAM particle identical;
2), ready-portioned matrix-block is alternately left in the row of the DDR SDRAM particle of controlling in storage particle A interface unit 1 and storage particle B interface unit 2;
3), centralized control unit 6 receives the visit order to matrix, and produces control informations such as access type, visit length;
4), the control information that obtains according to step 3) of mode of operation dispensing unit 5, judge that the visit to matrix is row access or column access, if row access, execution in step 5), if column access, execution in step 6);
5), mode of operation dispensing unit 5 sends configuration orders to storage particle A interface unit 1 and storage particle B interface unit 2 by configuration bus 11, and DDR SDRAM particle is set in the interleaving access mode, execution in step 7 then);
6), mode of operation dispensing unit 5 to storage particle A interface unit 1 and storage particle B interface unit 2, is set in sequential access mode with DDR SDRAM particle by configuration bus 11 transmission configuration orders;
7), scalar/vector 4 receives the first address of accessing operation, and the control information by control bus 12 receiving center control modules 6, determine the length of row matrix operation, produce DDR particle row address and the DDR particle column address that to operate then successively, and above-mentioned row, column address is sent to storage particle A interface unit 1 and storage particle B interface unit 2;
8), storage particle A interface unit 1 and B interface unit 2 alternation under the control of centralized control unit 6 of storage particle, realize visit to element in the matrix.
In the technique scheme, when DDR SDRAM particle was set in the interleaving access mode, in described step 7), it was the DDR particle column address of " 01 " or " 10 " that scalar/vector 4 produces minimum 2.
In the technique scheme, when DDR SDRAM particle was set in sequential access mode, in described step 7), it was the DDR particle column address of " 01 " or " 11 " that scalar/vector 4 produces minimum 2.
Memory controller and row matrix column access method that the present invention proposes have made full use of the characteristic of DDR particle 2 haplotype data rates, and have hidden the visit expense fully, have realized continual data transmission.Memory controller of the present invention can realize having simple, flexible, convenient characteristics of transplanting in programming devices such as FPGA.
Description of drawings
Fig. 1 is the synoptic diagram of a two-dimensional matrix;
Element was at the arrangement mode of address space when Fig. 2 was a two-dimensional matrix shown in Figure 1 according to the row storage;
Element was at the arrangement mode of address space when Fig. 3 was a two-dimensional matrix shown in Figure 1 according to the row storage;
Fig. 4 is the structural drawing of memory controller of the present invention;
Fig. 5 is to be the sequential chart of 2 storages of example explanation particle interface unit alternation with working length 32;
Fig. 6 is the synoptic diagram of one 2 row 2 column matrix;
Fig. 7 is the location drawing when according to storage means of the present invention 2 row, 2 column matrix shown in Figure 6 being done storage;
Fig. 8 is Burst transmission length and the order of DDR particle under different working modes;
Fig. 9 is the memory controller block scheme of HY5DU12822AT as storage medium;
Figure 10 is that 64 row, 64 column matrix are divided into the storage synoptic diagram in storage system of the present invention behind 4 pieces;
Figure 11 a is that preceding 16 of 32 row, 32 row submatrixs are listed in the memory location synoptic diagram in the storage system DDR SDRAM particle of the present invention delegation;
Figure 11 b is that back 16 of 32 row, 32 row submatrixs are listed in the memory location synoptic diagram in the storage system DDR SDRAM particle of the present invention delegation;
The sequential chart of 2 storage particle interface units alternation when Figure 12 is row access;
The sequential chart of 2 storage particle interface units alternation when Figure 13 is column access;
Figure 14 is the process flow diagram of row matrix column access method of the present invention.
The drawing explanation
1 storage particle A interface unit, 2 storage particle B interface unit, 3 data channel
4 scalar/vectors, 5 mode of operation dispensing units, 6 centralized control units
7 clock lists, 8 read data bus, 9 write data buss
10 address buss, 11 configuration bus, 12 control buss
Embodiment
Below in conjunction with the drawings and specific embodiments, the invention will be further described.
As shown in Figure 4, memory controller of the present invention is made up of storage particle A interface unit 1, storage particle B interface unit 2, data channel 3, scalar/vector 4, mode of operation dispensing unit 5, centralized control unit 6 and clock unit 7.Storage particle A interface unit 1, storage particle B interface unit 2 are connected with write data bus 9 by read data bus 8 with data channel 3; Storage particle A interface unit 1, storage particle B interface unit 2 are connected by address bus 10 with scalar/vector 4; Storage particle A interface unit 1, storage particle B interface unit 2 are connected by configuration bus 11 with mode of operation dispensing unit 5; Centralized control unit 6 is connected with storage particle A interface unit 1, storage particle B interface unit 2, data channel 3, scalar/vector 4, mode of operation dispensing unit 5 by control bus 12.Clock unit 7 provides the clock signal of need of work for whole memory controller.Whole memory controller uses the realization of programming of VerilogHDL language in the FPGA of Xillinx company, the FPGA model is XC2V4000.
Described storage particle A interface unit 1 and storage particle B interface unit 2 are identical on function, and it mainly acts on and is: externally connect the DDR particle, produce the sequential that meets the DDR particle requirement, finish the various operations to the DDR particle; Internally pass through the address that address bus 10 receiver address generation units 4 send, by read data bus 8, write data bus 9 and data channel 3 transmission data, receive the configuration order that mode of operation dispensing units 5 send by configuration bus 11, the read write command that sends by control bus 12 receiving center control modules 6.
Described data channel 3 externally receives write data or sends read data; Internally transmit data to DDR storage particle by read data bus 8, write data bus 9 and 2 storage particle interface units.Data channel 3 is determined the streams data direction of current operation also by the control information of control bus 12 receiving center control modules 6.
Described scalar/vector 4 externally receives the first address of read-write operation, and the control information by control bus 12 receiving center control modules 6, determine the length of read-write operation, determine that simultaneously read-write operation is line operate or row operation, produce a series of read/write address then, give 2 storage particle interface units by address bus 10.
Described mode of operation dispensing unit 5 determines that by the control information of control bus 12 receiving center control modules 6 read-write operation is line operate or row operation, sends configuration order to 2 a storage particle interface unit by configuration bus 11 then.
Described centralized control unit 6 externally receives read write command, and the control information that produces whole memory controller need of work, these control informations comprise: read or the how alternation of length, line operate or the row operation of write operation, read-write operation, storage particle interface unit.Centralized control unit 6 is mutual by control bus 12 and other each unit.
Utilize above-mentioned DDR memory controller, can realize the visit to the matrix ranks, the access method of matrix ranks comprises:
Step 20, ready-portioned matrix-block alternately left in the row of DDR SDRAM particle of storage particle A interface unit 1 and unit 2 controls of storage particle B interface;
The visit order that step 30, centralized control unit 6 receive matrix, and produce control informations such as access type, visit length;
The control information that step 40, mode of operation dispensing unit 5 obtain according to step 30 judges that the visit to matrix is row access or column access, if row access, execution in step 50, if column access, execution in step 60;
Step 50, mode of operation dispensing unit 5 send configuration order to storage particle A interface unit 1 and storage particle B interface unit 2 by configuration bus 11, and DDR SDRAM particle is set in the interleaving access mode, and execution in step 70 then;
Step 60, mode of operation dispensing unit 5 send configuration order to storage particle A interface unit 1 and storage particle B interface unit 2 by configuration bus 11, and DDR SDRAM particle is set in sequential access mode;
Step 70, scalar/vector 4 receive the first address of accessing operation, and the control information by control bus 12 receiving center control modules 6, determine the length of row matrix operation, produce DDR particle row address and the DDR particle column address that to operate then successively, and above-mentioned row, column address is sent to storage particle A interface unit 1 and storage particle B interface unit 2;
Step 80, storage particle A interface unit 1 and B interface unit 2 alternation under the control of centralized control unit 6 of storage particle realize the visit to element in the matrix.
A core of memory controller of the present invention and row matrix column access method is: contain in the memory controller 2 independently but the identical storage particle interface unit of function, centralized control unit 6 control store particle A interface units 1 and unit 2 alternations of storage particle B interface, hidden the operation overhead of DDR particle, guaranteed that the data in the data channel 3 continue to flow.Describe principle of work below in detail.
The operation overhead of DDR particle comprise open the DDR particle capable, close capable, the periodic refreshing of DDR particle, the clock period of these 3 action needs is 3,3,8 (considering worst condition here) to the maximum, so the operation overhead of DDR particle is 14 clock period to the maximum.Only the length that needs centralized control unit 6 that each read-write operation is set is greater than or equal to 14 clock period, and control store particle B interface unit 2 starts working, stores particle A interface unit 1 and start working when storage particle B interface unit 2 executive overhead action requireds when storage particle A interface unit 1 executive overhead action required, just can hide its operation overhead fully.Fig. 5 is an example with read-write operation length 32, and the sequential of 2 storage particle interface units alternation has been described.In the moment 0, storage particle A interface unit 1 is started working; In the moment 32, starting working in storage particle B interface unit 2, stores particle A interface unit 1 simultaneously and enter overhead operations; In the moment 64, storage particle B interface unit 2 need enter overhead operations, has finished overhead operations and store particle A interface unit 1 this moment, can start working once more; In the moment 96,128,2 work that storage particle interface unit replaces constantly, guaranteed continual data transmission equally.
Another core of memory controller of the present invention and row matrix column access method is: realized that by mode of operation dispensing unit 5 and scalar/vector 4 interleaving access (Interleaved) mode is adopted in operation to row matrix, put DDR particle address low level and be " 01 " or " 10 "; And sequential access (Sequential) mode is adopted in operation to rectangular array, puts DDR particle address low level and is " 01 " or " 11 "; Overcome the row matrix visit of array signal and the shortcoming that the rectangular array visit can not utilize DDR particle 2 haplotype data rate characteristics simultaneously, the realization of maximum the transmission bandwidth of DDR particle.Row matrix visit and rectangular array visit with 2 row, 2 column matrix is example below, is described in detail.
Fig. 6 is one 2 row 2 column matrix, and its first row element is a1 and a2, and second row element is b1 and b2; Its first column element is a1 and b1, and the secondary series element is a2 and b2.When row matrix was visited, a1 and a2 can be once taken out in hope, perhaps once took out b1 and b2; Equally, when rectangular array was visited, a1 and b1 can be once taken out in hope, perhaps once took out a2 and b2.Among Fig. 7, provided the memory location figure that utilizes row matrix column access method of the present invention to realize.Leave a1 the position of the low address of DDR particle column address in for " 01 ", a2 leaves the position of the low address of DDR particle column address for " 00 " in, b1 leaves the position of the low address of DDR particle column address for " 10 " in, and b2 leaves the position of the low address of DDR particle column address for " 11 " in.
Fig. 8 has illustrated burst transfer (Burst) length and the order of DDR particle under different working modes.According to Fig. 8, when the needs row matrix is visited, adopt interleaving access (Interleaved) mode, can be " 01 " at the first address of the mid-DDR particle of a burst transfer (Burst) column address, the DDR particle will obtain a1 and a2 to the operation of " 01 " and " 00 " memory location; Can be " 10 " at the first address of the mid-DDR particle of a burst transfer (Burst) column address also, the DDR particle will obtain b1 and b2 to the operation of " 10 " and " 11 " memory location.
Equally according to Fig. 8, when the needs rectangular array is visited, adopt sequential access (Sequential) mode, can be " 01 " at the first address of the mid-DDR particle of a burst transfer (Burst) column address, the DDR particle will obtain a1 and b1 to the operation of " 01 " and " 10 " memory location; Can be " 11 " also at the first address of the mid-DDR particle of a burst transfer (Burst) column address, the DDR particle will be operated " 11 " and " 00 " memory location, obtain b2 and a2,, recover the order of a2 and b2 then by the data of switching clock rising edge and negative edge.
No matter utilize row matrix column access method recited above, be the row matrix visit, or the rectangular array visit, can obtain 2 data of row or row a clock period, made full use of the characteristic of DDR particle 2 haplotype data rates transmission.When matrix was listed as greater than 2 row 2, the submatrix that it can be decomposed into a plurality of 2 row, 2 row carried out same processing, so this method is applicable to the Array Signal Processing of different scales.
The DDR SDRAM particle HY5DU28822ET that adopts Hynix company adopts row matrix column access method of the present invention and memory controller as storage medium below, forms the DDRSDRAM storage system that is fit to the array signal transpose process, as shown in Figure 9.
HY5DU28822ET is organized as 4M * 8bit * 4banks; The row address of DDR particle is 12,4K; The column address of DDR particle is 10,1K.Therefore, HY5DU28822ET can be supported in the address realm of 1K and read continuously arbitrarily or write operation.Here the row address of HY5DU28822ET particle is designated as Ar[11:0], column address is designated as Ac[9:0].
With 64 row, the matrix of 64 row is that example illustrates row matrix column access method of the present invention.Matrix is divided into 4 pieces with it as shown in figure 10, and each piece is 32 row, the submatrix of 32 row, and its size is 1K, can leave in just in 1 row of HY5DU28822ET particle.
Wherein piece A, D leave in the particle of storage unit A interface unit 1 control, every 1 row that occupies the DDR particle of storage unit A interface unit 1 control; Piece B, C leave in the particle of storage unit B interface unit 2 controls, every 1 row that occupies the DDR particle of storage unit B interface unit 2 controls.
Be example with piece A below, the storage means of illustrated block in DDR SDRAM particle 1 row.As shown in figure 11, with the DDR particle column address Ac[9:0 in DDR SDRAM particle 1 row] be expressed as 16 system 0x000～0x3FF, the submatrix of 32 row, 32 row is divided into the fundamental block of 256 2 row 2 row again, each fundamental block leaves in 4 continuous in 1 row memory locations, fundamental block jump according to the row matrix direction is deposited, and deposits continuously according to the fundamental block of rectangular array direction.
Piece B, C, D in the DDR particle is capable storage means and the piece category-A seemingly, no longer be described in detail.
With the 5th behavior example of access matrix, illustrate how to realize row matrix accessing operation efficiently.The element of the 5th row has been divided among piece A and the piece B.During visit, centralized control unit 6 at first receives read write command, and produces: read or control informations such as the length (64) of write operation, read-write operation, row matrix operation.The row matrix control information operation of mode of operation dispensing unit 5 receiving center control modules 6 sends configuration order to 2 a storage particle interface unit by configuration bus 12 then, and configuration DDR SDRAM particle is operated in interleaving access (Interleaved) mode.Scalar/vector 4 receives the first address of read-write operation, and passes through the control information of control bus 12 receiving center control modules 6, determines the length (64) of row matrix operation etc., produces the DDR particle row address { 0x000} of operation then successively, DDR particle column address { 0x008,0x048,0x088,0x0C8,0x108,0x148,0x188,0x1C8,0x208,0x248,0x288,0x2C8,0x308,0x348,0x388,0x3C8} gives 2 storage particle interface units by address bus 10.
Storage particle A interface unit 1 is at first started working under the control of centralized control unit 6, reception DDR particle row address 0x000}, and carry out the visits that the 1st of the 5th row among the piece A are listed as 32 row.Finish the 5th row the 32nd column access at storage particle A interface unit 1, when beginning to enter overhead cycles, unit 2 beginnings of storage particle B interface are started working under the control of centralized control unit 6, same reception DDR particle row address 0x000}, and carry out the visits that the 33rd of the 5th row among the piece B are listed as 64 row.The time relationship of its work because made full use of the two characteristics along operation of DDR SDRAM clock, is finished so each stores operating in 16 clock period of particle interface unit as shown in figure 12.Data channel 3 alternately receives data from storage particle A interface unit 1 and storage particle B interface unit 2 under the control of centralized control unit 6, guaranteed the high-level efficiency of visit.
Classify example as with the 5th of access matrix below, illustrate how to realize column access operation efficiently.The element of the 5th row has been divided among piece A and the piece C.During visit, centralized control unit 6 at first receives read write command, and produces: read or control informations such as the length (64) of write operation, read-write operation, rectangular array operation.The rectangular array control information operation of mode of operation dispensing unit 5 receiving center control modules 6 sends configuration order to 2 a storage particle interface unit by configuration bus 12 then, and configuration DDR SDRAM particle is operated in sequential access (Sequential) mode.Scalar/vector 4 receives the first address of read-write operation, and the control information by control bus 12 receiving center control modules 6, determine the length (64) of rectangular array operation etc., produce operation DDR particle row address { 0x000 then successively, 0x001} (the DDR particle row address that sends when carrying out the rectangular array visit is not both because the rectangular array element has left the 2nd row of the DDR particle of the 1st row of DDR particle of storage particle A interface unit 1 control and unit 2 controls of storage particle B interface in), DDR particle column address { 0x081,0x085,0x089,0x08D, 0x091,0x095,0x099,0x09D, 0x0A1,0x0A5,0x0A9,0x0AD, 0x0B1,0x0B5,0x0B9,0x0BD} gives 2 storage particle interface units by address bus 10.
Storage particle A interface unit 1 is at first started working under the control of centralized control unit 6, reception DDR particle row address 0x000}, and carry out the 5th the 1st row that is listed as among the piece A to the visit of 32 row.Finish the 5th at storage particle A interface unit 1 and be listed as the 32nd row access, when beginning to enter overhead cycles, unit 2 beginnings of storage particle B interface are started working under the control of centralized control unit 6, reception DDR particle row address 0x001}, and carry out the 5th the 33rd row that is listed as among the piece C to the visits of 64 row.The time relationship of its work as shown in figure 13 and the row matrix access classes seemingly because made full use of the two characteristics along operation of DDR SDRAM clock, operating in 16 clock period of each storage particle interface unit finished.Data channel 3 alternately receives data from storage particle A interface unit 1 and storage particle B interface unit 2 under the control of centralized control unit 6.
Claims (4)
1, a kind of DDR memory controller of suitable matrix transpose, comprise: data channel (3), scalar/vector (4), mode of operation dispensing unit (5), centralized control unit (6), clock unit (7), read data bus (8), write data bus (9), address bus (10), configuration bus (11) and control bus (12), it is characterized in that, also comprise storage particle A interface unit (1), storage particle B interface unit (2), described storage particle A interface unit (1) is connected by described read data bus (8) with described data channel (3), described storage particle A interface unit (1) also is connected by described write data bus (9) with described data channel (3), described storage particle B interface unit (2) is connected by described read data bus (8) with described data channel (3), and described storage particle B interface unit (2) also is connected by described write data bus (9) with described data channel (3); Described storage particle A interface unit (1), storage particle B interface unit (2) are connected by address bus (10) with described scalar/vector (4); Described storage particle A interface unit (1), storage particle B interface unit (2) are connected by described configuration bus (11) with described mode of operation dispensing unit (5); Described centralized control unit (6) is connected with storage particle A interface unit (1), storage particle B interface unit (2), data channel (3), scalar/vector (4), mode of operation dispensing unit (5) by control bus (12); Described clock unit (7) provides the clock signal of need of work for whole memory controller;
Described storage particle A interface unit (1) is two storage particle interface units separate and function is identical with storage particle B interface unit (2), they are connected respectively to the DDR particle, generation meets the sequential of DDR particle requirement, finishes the various operations to the DDR particle; And the address that sends by address bus (10) receiver address generation unit (4), by read data bus (8), write data bus (9) and data channel (3) transmission data, receive the configuration order that mode of operation dispensing unit (5) sends by configuration bus (11), the read write command that sends by control bus (12) receiving center control module (6); When doing storage operation, by centralized control unit (6) control described storage particle A interface unit (1) and storage particle B interface unit (2) alternation, hide the operation overhead of DDR particle, guarantee that the data in the data channel (3) continue to flow.
2, a kind of row matrix column access method of utilizing the described DDR memory controller of claim 1 comprises:
1), according to the size of the model of DDR SDRAM storer and the matrix that will store, matrix is divided into a plurality of, make 1 row size of the size of each piece and DDR SDRAM particle identical;
2), ready-portioned matrix-block is alternately left in the row of the DDR SDRAM particle of controlling in storage particle A interface unit (1) and storage particle B interface unit (2);
3), centralized control unit (6) receives the visit order to matrix, and produces control informations such as access type, visit length;
4), the control information that obtains according to step 3) of mode of operation dispensing unit (5), judge that the visit to matrix is row access or column access, if row access, execution in step 5), if column access, execution in step 6);
5), mode of operation dispensing unit (5) sends configuration order to storage particle A interface unit (1) with store particle B interface unit (2) by configuration bus (11), and DDR SDRAM particle is set in the interleaving access mode, execution in step 7 then);
6), mode of operation dispensing unit (5) to storage particle A interface unit (1) and storage particle B interface unit (2), is set in sequential access mode with DDR SDRAM particle by configuration bus (11) transmission configuration order;
7), scalar/vector (4) receives the first address of accessing operation, and the control information by control bus (12) receiving center control module (6), determine the length of row matrix operation, produce DDR particle row address and the DDR particle column address that to operate then successively, and above-mentioned row, column address is sent to storage particle A interface unit (1) and storage particle B interface unit (2);
8), storage particle A interface unit (1) and storage particle B interface unit (2) alternation under the control of centralized control unit (6), realization is to the visit of element in the matrix.
3, row matrix column access method according to claim 2, it is characterized in that, when DDR SDRAM particle was set in the interleaving access mode, in described step 7), it was the DDR particle column address of " 01 " or " 10 " that scalar/vector (4) produces minimum 2.
4, row matrix column access method according to claim 3, it is characterized in that, when DDR SDRAM particle was set in sequential access mode, in described step 7), it was the DDR particle column address of " 01 " or " 11 " that scalar/vector (4) produces minimum 2.
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| CN101609715B (en) * | 2009-05-11 | 2012-09-05 | 中国人民解放军国防科学技术大学 | Matrix register file with separated row-column access ports |
| CN101706760B (en) * | 2009-10-20 | 2013-07-31 | 龙芯中科技术有限公司 | Matrix transposition automatic control circuit system and matrix transposition method |
| CN103237157B (en) * | 2013-05-13 | 2015-12-23 | 四川虹微技术有限公司 | A kind of real-time high-definition video image transpose device |
| CN103389967B (en) * | 2013-08-21 | 2016-06-01 | 中国人民解放军国防科学技术大学 | The device and method of a kind of matrix transposition based on SRAM |
| CN107241070B (en) * | 2016-03-29 | 2020-07-10 | 大唐移动通信设备有限公司 | Method for determining DPD coefficient, FPGA and DPD processing system |
| CN114661641A (en) * | 2020-12-24 | 2022-06-24 | 华为技术有限公司 | Memory module and memory bus signal processing method |
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| US20010048616A1 (en) * | 2000-05-26 | 2001-12-06 | Kazushige Ayukawa | Semiconductor device including multi-chip |
| US20050050375A1 (en) * | 2003-08-29 | 2005-03-03 | Mark Novak | Memory interface system and method |
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Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20010048616A1 (en) * | 2000-05-26 | 2001-12-06 | Kazushige Ayukawa | Semiconductor device including multi-chip |
| US20050050375A1 (en) * | 2003-08-29 | 2005-03-03 | Mark Novak | Memory interface system and method |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102339261A (en) * | 2011-09-16 | 2012-02-01 | 上海智翔信息科技股份有限公司 | DDR (Double Data Rate) 2 SDRAM (Synchronous Dynamic Random Access Memory) controller |
| CN102339261B (en) * | 2011-09-16 | 2015-09-30 | 上海智翔信息科技股份有限公司 | A kind of DDR2SDRAM controller |
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| CN1832035A (en) | 2006-09-13 |
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