CN100442296C - Optimizing integrated circuit placement method - Google Patents

Abstract

The invention relates to optimizing IC layout method. It doesn't need to increase wafer area, can increase wafer operating speed, save power consumption, improve wafer working performance, and advance technique application layer to realize the purpose of good, fast, small, and saving electricity.

Description

The method of optimizing integrated circuit placement

Technical field

The present invention is a kind of method of optimizing integrated circuit placement, sees through an integrated circuit application software to design optimizing integrated circuit placement, to reach the purpose that improves wafer running speed and save power consumption.

Background technology

All be the minimum coiling standard (Minimumrule) that adopts wafer factory (Foundry) at present on wafer is realized, that is to say that it all is to adopt the narrowest distance to wind the line that metal wire is followed between the metal wire, although it is so in same zone can around at most, but, can be maximum so this practice also can cause the stray capacitance between line and the line because electric capacity is inversely proportional to distance; Come again to be exactly coiling with coiling if when striding the different metal layer, the integrated circuit application software only can add a tie point (Via), more do not take up space although it is so, but there is a problem to produce, because greatly nearly 100 times of the resistance ratio metal wires of tie point, if in a coiling a lot of tie points are arranged, then the resistance of this coiling can become big relatively.

For when the layout winding operation, some patent has disclosed and has shortened the layout processing time and reduce the relevant technology of stray capacitance, as U.S. Pat 6,026, No. 225 " SIC (semiconductor integrated circuit) layout method (Method of layout of semiconductor integrated circuits) ", it is the method for winding that discloses a kind of SIC (semiconductor integrated circuit) as ASIC, in order to shorten the layout processing time, allow high density or dwindle SIC (semiconductor integrated circuit), please refer to the layout type process flow diagram of Fig. 1 for above-mentioned patent, this method is to comprise injecting a plurality of function nuclears (cell) (S100), artificial circuit operation (S102), whether checking obtains optimized result (S104), if, then determine in advance for the selected number of interconnections of huge signal transmission delay (S106), otherwise, then restart, make detailed injection (S 108), whether the checking interconnect location has critical path (critical path) (S110), in this way, then make detailed coiling critical path (S112), as denying, then make detailed coiling slack path (S114), emulation loads the circuit operation (S116) that calculates from the resistance of interconnection and the true interconnection of electric capacity, whether checking at last obtains optimization circuits (S118), in this way, then finishes this flow process, as not, then get back to and make detailed implantation step.

Again, as U.S. Pat 6,867,127B1 number " rhombus is filled metal and reached low parasitic coupling capacitance (Diamond metal-filled patterns achieving low parasitic couplingcapacitance) ", it is to disclose a kind of mode of formation filling metal on the argyle design of an integrated substrate that sees through to reach low coupling capacitor.

Summary of the invention

The objective of the invention is to obtain optimized coiling distance and only single tie point number, make it when integrated circuit layout, can not increase chip area and can improve wafer again to operate speed and save power consumption.

In order to reach above-mentioned purpose, the present invention proposes a kind of method of optimizing integrated circuit placement, see through an integrated circuit application software to design optimizing integrated circuit placement, this method is to comprise loading optimizing integrated circuit placement archives in this integrated circuit application software; Injecting a plurality of electronic packages examines on an ic substrate of this integrated circuit application software institute emulation; See through an optimization rule to carry out an optimized winding placement; Calculating is via a plurality of stray capacitances that produced after this optimized winding placement; Obtain an optimized winding department apart from the connection number that reaches on same tie point; And calculate the running time of this optimized winding placement and make a running time form.

Reach technology, means and the effect that set purpose is taked in order further to understand the present invention, see also following about detailed description of the present invention and accompanying drawing, believe purpose of the present invention, feature and characteristics, go deep into and concrete understanding when getting one thus, yet appended graphic reference and the explanation usefulness of only providing not is to be used for the present invention is limited.

Description of drawings

Fig. 1 is for being SIC (semiconductor integrated circuit) layout method process flow diagram;

Fig. 2 is the method flow diagram of optimizing integrated circuit placement of the present invention; And

Fig. 3 is the coiling stray capacitance synoptic diagram of integrated circuit.

Symbol description:

Metal level 10,12,14

Top plate 16

Lower plywood 18

Limit, top electric capacity 20

Vertical (flat board) electric capacity 22 in top

The marginal electric capacity 24 in bottom

Bottom (flat board) electric capacity 26

Coupling capacitance 28

Embodiment

Body circuit application software now can't be done at the design of high speed and low power consumption for entity realization (Physical implement) and consider; Therefore, at considering of this design, the present invention finds out a kind of method that neither can increase chip area and can improve wafer running speed again and save power consumption and solves above-mentioned problem, expectation can reach the more further lift technique application level of serviceability that not only increases wafer, with reach, the target of fast, little and power saving.

Please refer to the method flow diagram of Fig. 2 for optimizing integrated circuit placement of the present invention, see through an integrated circuit application software to design optimizing integrated circuit placement, this method is to comprise loading optimizing integrated circuit placement archives in this integrated circuit application software (S200), when desire uses the integrated circuit application software to come the design entity integrated circuit layout, usually all can load in advance the integrated circuit layout archives to this integrated circuit application software with configuration as basic layout, yet the present invention loads the optimizing integrated circuit placement archives that calculated; Injecting a plurality of electronic packages examines on an ic substrate of this integrated circuit application software institute emulation (S202); See through an optimization rule to carry out an optimized winding placement (S204), wherein this optimization rule is under the space of certain coiling, and its winding department is apart from being maximum.

Activate one in this integrated circuit application software and wind the line instrumental function to carry out optimized winding placement action (S206); Calculating is via a plurality of stray capacitances (S208) that produced after this optimized winding placement action, and wherein those stray capacitances are to see through C _Total=2 (C _c+ C _Fb+ C _Ft)+C _Ba+ C _TaCalculating that formula is derived, this C _cBe coupling capacitance, this C _FbBe limit, bottom electric capacity, this C _FtBe limit, top electric capacity, this C _BaBe bottom vertical (flat board) electric capacity, this C _TaBe vertical (flat board) electric capacity in top.

Calculating is via a plurality of resistance (S210) that produced after this optimized winding placement action; Obtain an optimized winding department apart from the connection number (S212) that reaches on same tie point, wherein in this optimized coiling spacing range, its stray capacitance can relatively reduce, but greater than this optimized coiling spacing range the time, its stray capacitance will relatively increase; Calculate the running time of this optimized winding placement and make a running time form (S214).

When the integrated circuit winding placement designs, can learn its power consumption, area and mutual situation of running time by following relevant formula.Electric current (I) on applying voltage (Vd) and this integrated circuit of flowing through is when the constant, and operate the time (T) also can and then reduce if parasitic capacitance value (C) reduces, as $T=\frac{(C\×V_d)}{I}$ Formula is represented, and applies voltage and running time when being constant, and this moment, the electric current on this integrated circuit of then flowing through can reduce, when electric current reduces then component size when parasitic capacitance value reduces Also can and then reduce, as $I=\mathrm{\μC}\frac{W}{2L}{(V_G-V_T)}^2$ Formula is represented, wherein this V _G-V _TFor grid voltage deducts cut-in voltage, W is effective grid width, and L is effective grid length, the power consumption calculation of this integrated circuit as $P=\frac{1}{2}C\×V_d\×f$ Formula is represented, and wherein this f is an operation frequency, and when applying voltage and operation frequency and be constant, the whole power consumption of integrated circuit will reduce to make stray capacitance reduce then.

Please refer to Fig. 3, Fig. 3 is the coiling stray capacitance synoptic diagram of integrated circuit, each metal level 10,12, can produce coupling capacitance 28 between 14, in addition, between top plate 16 and lower plywood 18 for each metal level 10,12,14 all can produce different stray capacitances, with metal level 12, comprise limit, at least one top electric capacity 20, vertical (flat board) electric capacity 22 at least one top, at least one bottom limit electric capacity 24 and at least one bottom (flat board) electric capacity 26 or the like, so it is the summation of above-mentioned every stray capacitance that this integrated circuit winding placement is understood the electric capacity summation that produces, can C _Total=2 (28+24+20)+26+22 formula are with expression, wherein for this integrated circuit layout have the greatest impact for coupling capacitance 28.

Say according to above-mentioned, because the running speed and the power consumption of wafer are relevant with the laod network that resistance capacitance is constituted, if not change chip area is prerequisite, reduce resistance capacitance with different coiling establishing method, that just can be realized not changing chip area and promote wafer running speed and the demand of saving power consumption.To put planning (FloorPlan), wafer utilization rate (Chip utilization) and winding department distance (Wire pitch) with wafer assemblies relevant yet general wafer can wind the line, these combine is exactly the resource that winds the line, so reduce the stray capacitance of coiling, can adopt the method for widening the coiling distance to reach.

Yet for the resistance value that winds the line and produced, can use the method that increases single tie point number to improve, but the coiling distance can not infinitely strengthen, meeting is elongated relatively because the minimizing of coiling resource can make the coiling distance, this moment, stray capacitance can become big on the contrary, also can not infinitely increase as for single tie point number, because can reduce the coiling resource like this, make coiling disorderly around and increase the diverse location tie point, the wire resistor value can be increased, if want to keep constant stray capacitance and the resistance value of reducing simultaneously of wafer size, its effective and efficient manner is winding department distance and increase the tie point number and obtain optimization between the resource with winding the line for a change.

Yet utilize method of the present invention to bring the connection number of optimization winding department distance and same tie point into, when being applied to the entity realization of a high speed design, can find to utilize size and put the same wafer and work as benchmark, utilize technique known to make comparisons simultaneously, the present invention can make wafer running speed accelerate really and reduce power consumption.

Above-mentioned disclosed graphic, explanation only be embodiments of the invention, allly is skillful in this skill person when can doing other all improvement according to above-mentioned explanation, and these change and still belong in the claim that invention spirit of the present invention defines below reaching.

Claims (6)

1. the method for an optimizing integrated circuit placement sees through an integrated circuit application software to design optimizing integrated circuit placement, it is characterized in that, comprises the following steps:

Load optimizing integrated circuit placement archives in this integrated circuit application software;

Injecting a plurality of electronic packages examines on an ic substrate of this integrated circuit application software institute emulation;

See through an optimization rule to carry out an optimized winding placement, wherein this optimization rule is under the space of certain coiling, and its winding department is apart from being maximum;

Calculating is via a plurality of stray capacitances that produced after this optimized winding placement;

Obtain an optimized winding department apart from the connection number that reaches on same tie point; And

Calculate the running time of this optimized winding placement and make a running time form.

2. the method for optimizing integrated circuit placement as claimed in claim 1 is characterized in that, wherein should see through the step of an optimization rule, comprises that further a coiling instrumental function that activates in this integrated circuit application software is to carry out optimized winding placement.

3. the method for optimizing integrated circuit placement as claimed in claim 1 is characterized in that, wherein should calculate the step via this optimized winding placement action, comprises that also calculating is via a plurality of resistance that produced after this optimized winding placement.

4. the method for optimizing integrated circuit placement as claimed in claim 1 is characterized in that, wherein said a plurality of stray capacitances are to see through calculating that following formula is derived:

C _total＝2(C _c+C _fb+C _ft)+C _ba+C _ta

This C _cBe coupling capacitance, this C _FbBe limit, bottom electric capacity, this C _FtBe limit, top electric capacity, this C _BaBe bottom vertical electric capacity, this C _TaBe the top vertical capacitor.

5. the method for optimizing integrated circuit placement as claimed in claim 1, it is characterized in that wherein in this optimized coiling spacing range, its stray capacitance can relatively reduce, but greater than this optimized coiling spacing range the time, its stray capacitance will relatively increase.

6. the method for optimizing integrated circuit placement as claimed in claim 2 is characterized in that, wherein should calculate the step via this optimized winding placement action, comprises that more calculating is via a plurality of resistance that produced after this optimized winding placement.

Images