CN100440535C - Phase-change memory unit combined by reversible phase-change resistance and transistor and preparing method thereof - Google Patents
Phase-change memory unit combined by reversible phase-change resistance and transistor and preparing method thereof Download PDFInfo
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- CN100440535C CN100440535C CNB2005100265412A CN200510026541A CN100440535C CN 100440535 C CN100440535 C CN 100440535C CN B2005100265412 A CNB2005100265412 A CN B2005100265412A CN 200510026541 A CN200510026541 A CN 200510026541A CN 100440535 C CN100440535 C CN 100440535C
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- 238000000034 method Methods 0.000 title claims abstract description 38
- 230000002441 reversible effect Effects 0.000 title claims abstract description 22
- 230000005669 field effect Effects 0.000 claims abstract description 13
- 239000012782 phase change material Substances 0.000 claims abstract description 13
- 230000007704 transition Effects 0.000 claims description 26
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- 239000000463 material Substances 0.000 claims description 20
- 229910052710 silicon Inorganic materials 0.000 claims description 19
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- 239000010703 silicon Substances 0.000 claims description 18
- 238000002360 preparation method Methods 0.000 claims description 17
- 229910052751 metal Inorganic materials 0.000 claims description 14
- 239000002184 metal Substances 0.000 claims description 14
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- 238000006243 chemical reaction Methods 0.000 claims description 9
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- 238000001755 magnetron sputter deposition Methods 0.000 claims description 8
- 229920002120 photoresistant polymer Polymers 0.000 claims description 8
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 7
- 229920005591 polysilicon Polymers 0.000 claims description 7
- 230000008569 process Effects 0.000 claims description 7
- 239000010409 thin film Substances 0.000 claims description 7
- 230000009466 transformation Effects 0.000 claims description 7
- 229910004298 SiO 2 Inorganic materials 0.000 claims description 6
- PZZOEXPDTYIBPI-UHFFFAOYSA-N 2-[[2-(4-hydroxyphenyl)ethylamino]methyl]-3,4-dihydro-2H-naphthalen-1-one Chemical compound C1=CC(O)=CC=C1CCNCC1C(=O)C2=CC=CC=C2CC1 PZZOEXPDTYIBPI-UHFFFAOYSA-N 0.000 claims description 5
- 239000003292 glue Substances 0.000 claims description 5
- 238000009413 insulation Methods 0.000 claims description 5
- 238000010884 ion-beam technique Methods 0.000 claims description 5
- WABPQHHGFIMREM-UHFFFAOYSA-N lead(0) Chemical compound [Pb] WABPQHHGFIMREM-UHFFFAOYSA-N 0.000 claims description 5
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 4
- 238000004026 adhesive bonding Methods 0.000 claims description 4
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- 238000000151 deposition Methods 0.000 claims description 3
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- 229910052697 platinum Inorganic materials 0.000 claims description 3
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 claims description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 claims description 2
- 210000001367 artery Anatomy 0.000 claims description 2
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 2
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Abstract
The present invention provides a phase change memory unit which combines a reversible phase change resistor and a transistor into a whole, and a preparing method thereof. Small-sized field effect transistors of micrometer levels to nano levels are prepared by using the N type and P type characteristics of reversible phase change material with relative stability and easy micro-manufacturing technology through using the semiconductive characteristic of phase change material. Extraction electrodes of 10 to 100 nm are prepared on a source electrode and a drain electrode of a transistor by using nano processing technology, the structural integration and the functional integration of 1R1T (one reversible phase change resistor and one field effect transistor) for constructing a phase change memory unit can be realized, and the integration level of a phase change memory can be effectively improved.
Description
Technical field
The present invention relates to a kind of phase-changing memory unit and preparation method.Specifically, relate to P type and N type phase-change material, the N type is prepared phase-changing memory unit, device to P type or P type to ion injection transition and a kind of employing Micrometer-Nanometer Processing Technology of N type.The invention belongs to microelectronics technology.
Background technology
Phase transition storage (C-RAM) is based on that the reversible variation of phase-change material makes the large and small reversible variation of resistance value and the memory technology that realizes information.Compare with main flow semiconductor memory technologies in the market, that C-RAM has is non-volatile, have extended cycle life, component size is little, low in energy consumption, can multistagely store, read at a high speed, advantage such as anti-irradiation (ability of resistant to total dose is greater than 1Mrad), high-low temperature resistant (55～125 ℃), anti-vibration, anti-electronic jamming and manufacturing process are simple, not only can be used widely at civilian microelectronics such as mobile phone, digital camera, MP3 player, mobile memory cards, and in military domain such as Aero-Space or guided missile system, important application prospects be arranged.Therefore, the major company of semicon industries such as international Ovonyx, Intel, Samsung, STMicw Electronics and Hitachi and the research and development that The Air Force Research Laboratory all is devoted to C-RAM, and in nearest 5 years, obtained the breakthrough of a series of great technology, allowed industry see the dawn of its practicability.For this reason, the international semiconductor TIA in 2 years of 2003-04 comes C-RAM first of the novel memory technology that might realize industrialization, is considered to most possibly replace the device that present flash memory (FLASH), dynamic random access memory (DRAM) becomes following memory main product and become commercial product at first.
At present C-RAM is carrying out that technology is improved and the R﹠D work of manufacturability aspect.Intel company prepares the model machine of 4MB in calendar year 2001; Samsung has then prepared the test sample of 64MB at the beginning of 2004.
Though the research and development impetus of C-RAM is very gratifying, but also have many manufacturabilities and basic problem not to obtain fine solution, aspect basic, the research and development of novel phase-change material, as the characteristic of semiconductor of phase-change material when the amorphous, electrical conduction mechanism research, the research of P/N type, the P type makes the transition the research of P/N type thermal stability and resistance stability to N type or N type to the P type.Aspect device, reduce the new device structural research that device cell improves device density, phase-change material and good electrode material are in the processing technology of nanoscale and Research of Ohmic Contact etc., and these researchs will be followed the whole process of C-RAM industrialization and propelling.The characteristic of semiconductor that how to effectively utilize phase-change material is realized the switching characteristic of field-effect transistor, the 1R1T that the storage characteristics that how to effectively utilize the reversible transition material realizes phase-change memory cell integrated on integrated and function in shape is starting point of the present invention, the most important be under the prerequisite of the not switching characteristic of damage field effect transistor realization to the memory function of information.
Summary of the invention
The object of the present invention is to provide a kind of phase-changing memory unit and preparation method.The phase-changing memory unit that provides is by integrated on integrated on a reversible transition resistance and the field-effect transistor structure and the function.Integrated on the structure have in following two kinds of structures any one:
(1) on P type twin polishing silicon substrate, leakage and source are N type Ge
2Sb
2Te
5Film, the reversible transition resistance material in grid region then be by element doping by the material of N type to P type conversion;
(2) on N type twin polishing silicon substrate, leakage and source are P type Ge
2Sb
2Te
5Film, the reversible transition resistance material in grid region then be by element doping by the material of P type to N type conversion.
Described grid region is 20-150nm to conversion of P type or P type to the reversible transition resistance material thickness of N type conversion by the N type; The aperture of described source and leakage is 10-100nm.
Concrete preparation technology comprises:
1, the preparation of phase-change material
Si and amorphous chalcogenide compound all belong to semi-conducting material, Si is the semi-conducting material of ripe main flow of preparation semiconductor device, but can not realize memory function from material itself, utilize chalcogenide compound reversible transition process can realize the memory function of information, but this kind material material is soft, multicomponent, bad with interface mechanical characteristics such as silicon materials, metal materials, is not a kind of good semi-conducting material therefore.Adopt the magnetron sputtering means, compound by Si and amorphous chalcogenide compound, optimize component and realize that plural layers adhesive force is good, easily micro-nano processing, and can be at the composite material of nanosecond order generation reversible transition.Inject by ion, realize material by the N type to the conversion of P type or P type to N type chalcogenide compound.
2, the preparation of device cell
Adopt N type and P type chalcogenide compound composite material, mix by exposure, etching or ion implantation modification and realize the transistor arrangement of NPN or PNP, optimize the switch performance that technology realizes low-voltage, utilize nanoprocessing technology at SiO
2Adiabatic and passivation layer is realized the source, is leaked drawing of nano-electrode and drawing of gate electrode.
3, from the above mentioned, technical process provided by the invention is:
(a) on P type or N type silicon substrate, adopt magnetron sputtering method to prepare N type or P type Ge
2Sb
2Te
5Phase-change thin film;
(b) N type or the P type Ge for preparing in step (a)
2Sb
2Te
5Adopt gluing, exposure and developing method to leave the phase-change material window of transition on the film, ion injects Ge
2Sb
2Te
5Film makes it to be P type or N type;
(c) deposit spathic silicon grid are at N type or the P type Ge as source and leakage
2Sb
2Te
5Resist coating protection on the film;
(d) remove photoresist, and peel off polysilicon unnecessary on the glue;
(e) deposition SiO
2Heat insulation layer;
(f) expose source, leakage and grid with focused ion beam method and lithographic method respectively;
(g) evaporated metal electrode and carve metal lead wire.
The N type or the P type Ge that adopt magnetically controlled sputter method to prepare on the described silicon substrate material
2Sb
2Te
5The thickness of film is 5-200nm.
Described ion injects and makes Ge
2Sb
2Te
5Transoid, the injection ion that uses is any one of silicon, phosphorus, boron, oxygen and nitrogen.
Described metal electrode lead-in wire is W, Pt, Al, RuO or LaNiO
3In a kind of, the preparation method is a kind of in magnetron sputtering, high vacuum electron beam evaporation, plasma enhanced chemical vapor deposition or the vapour deposition of metal organic molecular chemistry.
Addressing and switching characteristic by the phase-change memory cell of method provided by the invention preparation realize by the phase transformation field-effect transistor, the writing, wipe under the situation that operation is and pulsewidth high by effective control voltage or current pulse signal arteries and veins of storing process, under the situation of not destroying phase transformation switch with field-effect transistors characteristic, realize phase transformation field-effect transistor source, leak the reversible transition process in the local nanometer range, sense data by measurement source, leakage the resistance size and in addition logic compare.
Description of drawings
Fig. 1 deposits N type Ge on P type silicon chip
2Sb
2Te
5Film
Fig. 2 ion injects and makes Ge
2Sb
2Te
5Film is P type (former N type Ge
2Sb
2Te
5Film blocks with photoresist)
Fig. 3 deposit polysilicon gate
Fig. 4 removes photoresist, and peels off polysilicon unnecessary on the glue
Fig. 5 deposit SiO
2Heat insulation layer
Fig. 6 exposes the source with the method for focused ion beam method and etching respectively and leaks and grid
Fig. 7 evaporated metal electrode
Fig. 8 carves metal lead wire, finishes the making of whole phase transition storage
Embodiment
Embodiment 1
On P type silicon substrate material, adopt magnetron sputtering method to prepare N type Ge
2Sb
2Te
5Phase-change thin film (Fig. 1), technological parameter is: background air pressure is 3 * 10
-4Pa, Ar gas air pressure is 0.15Pa during sputter, and sputtering power is 200W, and underlayer temperature is 25 ℃, and film thickness is 200nm.Again at Ge
2Sb
2Te
5Adopt gluing, exposure and developing method to leave the phase-change material window of transition on the phase-change thin film, ion injects N makes Ge
2Sb
2Te
5Be P type (Fig. 2), technological parameter is: the injection energy is 65keV, and implantation dosage is 4.51 * 10
16/ cm
2Deposit polysilicon gate (Fig. 3).Remove photoresist, and peel off polysilicon unnecessary on the glue (Fig. 4).Deposit SiO
2Heat insulation layer (Fig. 5).Expose source, leakage and grid (Fig. 6) with the method for focused ion beam method and etching respectively.Adopt magnetron sputtering method to prepare metal electrode W (Fig. 7), technological parameter is: background air pressure is 5 * 10
-4Pa, Ar gas air pressure is 0.08Pa during sputter, and sputtering power is 300W, and underlayer temperature is 25 ℃, and film thickness is 100nm.Carve metal lead wire, finish the making (Fig. 8) of whole phase transition storage.The NPN phase transformation transistor arrangement for preparing under above-mentioned technology can be realized switch performance and storage characteristics.
Embodiment 2
P type silicon substrate material among the embodiment 1 is changed into N type silicon substrate material, and other is identical with embodiment 1.
Embodiment 3
The Ge in embodiment 1 and 2
2Sb
2Te
5Phase-change thin film changes into by Si and Ge
2Sb
2Te
5Compound phase-change thin film, other is identical with embodiment 1 and 2.
Embodiment 4
Injection ion N in embodiment 1 and 2 is changed into B, and technological parameter is: the injection energy is 60keV, and implantation dosage is 3.86 * 10
16/ cm
2, other is identical with embodiment 1 and 2.
Embodiment 5
Extraction electrode W among embodiment 1, embodiment 2, embodiment 3 and the embodiment 4 is changed into Pt, or Al, or RuO, or LaNiO
3, other is identical with embodiment 1,2,3 and 4.
Embodiment 6
The phase-change memory cell among embodiment 1, embodiment 2, embodiment 3, embodiment 4 and the embodiment 5, by aluminium or the interconnected realization array of copper, because integrated on the integrated and function structurally improved the integrated level of phase transition storage effectively.
Claims (8)
1, the phase-changing memory unit that unites two into one of a kind of reversible transition resistance and transistor is characterized in that on reversible transition resistance and the field-effect transistor structure integrated on the integrated and function; Integrated on described reversible transition resistance and the field-effect transistor structure, be in following two kinds of structures any one:
A is on P type twin polishing silicon substrate, and leakage and source are N type Ge
2Sb
2Te
5Film, the reversible transition resistance material in grid region then are by the material of N type to the conversion of P type by the element doping method;
B is on N type twin polishing silicon substrate, and leakage and source are P type Ge
2Sb
2Te
5Film, the reversible transition resistance material in grid region then are by the material of P type to the conversion of N type by the element doping method.
2,, it is characterized in that described grid region is 20-150nm to conversion of P type or P type to the reversible transition resistance material thickness of N type conversion by the N type by the described phase-changing memory unit of claim 1.
3, the method for preparation phase-changing memory unit as claimed in claim 1 is characterized in that the step of preparation process of structure A is:
A on P type silicon substrate, adopts magnetron sputtering method or PECVD method to prepare N type Ge earlier
2Sb
2Te
5Phase-change thin film;
The N type Ge that b prepares at step a then
2Sb
2Te
5Adopt gluing, exposure and developing method to leave the phase-change material window of transition on the film, ion injects Ge
2Sb
2Te
5Film makes it to be the P type;
C deposit spathic silicon grid are at the N type Ge as source and leakage
2Sb
2Te
5Scribble the photoresist protection on the film;
D removes photoresist, and peels off polysilicon unnecessary on the glue;
E deposits SiO
2Heat insulation layer;
F exposes source, leakage and grid with focused ion beam method and lithographic method respectively;
G evaporated metal electrode also carves metal lead wire.
4, the method for preparation phase-changing memory unit as claimed in claim 1 is characterized in that the step of preparation process of structure B is:
A adopts magnetron sputtering method or PECVD method to prepare P type Ge on N type silicon substrate
2Sb
2Te
5Phase-change thin film;
The P type Ge that b prepares at step a then
2Sb
2Te
5Adopt gluing, exposure and developing method to leave the phase-change material window of transition on the film, make P type Ge by the ion injection
2Sb
2Te
5Film is the N type;
C deposit spathic silicon grid are at the P type Ge as source and leakage
2Sb
2Te
5Scribble the photoresist protection on the film;
D removes photoresist, and peels off polysilicon unnecessary on the glue;
E deposits SiO
2Heat insulation layer;
F exposes source, leakage and grid with focused ion beam method and lithographic method respectively;
G evaporated metal electrode also carves metal lead wire.
5,, it is characterized in that the N type or the P type Ge that adopt magnetically controlled sputter method to prepare on the silicon substrate material as the preparation method of claim 3 or 4 described phase-changing memory units
2Sb
2Te
5The thickness of film is 5-200nm.
6, the preparation method of phase-changing memory unit as claimed in claim 3 is characterized in that the ion injection makes N type Ge
2Sb
2Te
5Transoid becomes the P type, and the injection ion that uses is any one of silicon, phosphorus, boron, oxygen and nitrogen.
7,, it is characterized in that the metal electrode lead-in wire is W, Pt, Al, RuO or LaNiO as the preparation method of claim 3 or 4 described phase-changing memory units
3In a kind of, the preparation method is a kind of in magnetron sputtering, high vacuum electron beam evaporation, plasma enhanced chemical vapor deposition or the vapour deposition of metal organic molecular chemistry.
8, the phase-changing memory unit for preparing by claim 3 or 4 described methods, it is characterized in that addressing and switching characteristic realize by the phase transformation field-effect transistor, the writing, wipe under the situation that operation is and pulsewidth high by effective control voltage or current pulse signal arteries and veins of storing process, under the situation of not destroying phase transformation switch with field-effect transistors characteristic, realize phase transformation field-effect transistor source, leak the reversible transition process in the local nanometer range, sense data by measurement source, leakage the resistance size and in addition logic compare.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2005100265412A CN100440535C (en) | 2005-06-08 | 2005-06-08 | Phase-change memory unit combined by reversible phase-change resistance and transistor and preparing method thereof |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2005100265412A CN100440535C (en) | 2005-06-08 | 2005-06-08 | Phase-change memory unit combined by reversible phase-change resistance and transistor and preparing method thereof |
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| Publication Number | Publication Date |
|---|---|
| CN1722462A CN1722462A (en) | 2006-01-18 |
| CN100440535C true CN100440535C (en) | 2008-12-03 |
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| US7883931B2 (en) | 2008-02-06 | 2011-02-08 | Micron Technology, Inc. | Methods of forming memory cells, and methods of forming programmed memory cells |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0563248A (en) * | 1991-09-02 | 1993-03-12 | Japan Aviation Electron Ind Ltd | Superconducting phase-change type fet |
| JPH09260670A (en) * | 1996-03-21 | 1997-10-03 | Sharp Corp | Semiconductor device, thin film transistor, manufacture thereof, liquid crystal display device and manufacture thereof |
| CN1455461A (en) * | 2003-05-29 | 2003-11-12 | 北京大学 | Back-gate MOS transistor, and manufacturing method thereof and static RAM |
| US20040166604A1 (en) * | 2003-02-25 | 2004-08-26 | Samsung Electronics Co. Ltd. | Phase changeable memory cells and methods of fabricating the same |
| US20040195604A1 (en) * | 2003-04-02 | 2004-10-07 | Young-Nam Hwang | Phase-change memory devices and methods for forming the same |
| US20050037574A1 (en) * | 2002-03-27 | 2005-02-17 | Fujitsu Limited | Semiconductor memory device and manufacturing method thereof |
-
2005
- 2005-06-08 CN CNB2005100265412A patent/CN100440535C/en not_active Expired - Fee Related
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0563248A (en) * | 1991-09-02 | 1993-03-12 | Japan Aviation Electron Ind Ltd | Superconducting phase-change type fet |
| JPH09260670A (en) * | 1996-03-21 | 1997-10-03 | Sharp Corp | Semiconductor device, thin film transistor, manufacture thereof, liquid crystal display device and manufacture thereof |
| US20050037574A1 (en) * | 2002-03-27 | 2005-02-17 | Fujitsu Limited | Semiconductor memory device and manufacturing method thereof |
| US20040166604A1 (en) * | 2003-02-25 | 2004-08-26 | Samsung Electronics Co. Ltd. | Phase changeable memory cells and methods of fabricating the same |
| US20040195604A1 (en) * | 2003-04-02 | 2004-10-07 | Young-Nam Hwang | Phase-change memory devices and methods for forming the same |
| CN1455461A (en) * | 2003-05-29 | 2003-11-12 | 北京大学 | Back-gate MOS transistor, and manufacturing method thereof and static RAM |
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