CN100444012C - Pixel structure of liquid crystal display of thin film transistor, and fabricating method - Google Patents
Pixel structure of liquid crystal display of thin film transistor, and fabricating method Download PDFInfo
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- CN100444012C CN100444012C CNB2006101451136A CN200610145113A CN100444012C CN 100444012 C CN100444012 C CN 100444012C CN B2006101451136 A CNB2006101451136 A CN B2006101451136A CN 200610145113 A CN200610145113 A CN 200610145113A CN 100444012 C CN100444012 C CN 100444012C
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- 238000000034 method Methods 0.000 title claims abstract description 29
- 239000010409 thin film Substances 0.000 title claims description 21
- 239000004973 liquid crystal related substance Substances 0.000 title claims description 9
- 238000009413 insulation Methods 0.000 claims abstract description 51
- 238000002161 passivation Methods 0.000 claims abstract description 17
- 239000011521 glass Substances 0.000 claims abstract description 8
- 229920002120 photoresistant polymer Polymers 0.000 claims description 119
- 238000005530 etching Methods 0.000 claims description 58
- 239000002184 metal Substances 0.000 claims description 35
- 229910052751 metal Inorganic materials 0.000 claims description 35
- 239000000758 substrate Substances 0.000 claims description 17
- 238000004519 manufacturing process Methods 0.000 claims description 11
- 238000003384 imaging method Methods 0.000 claims description 10
- 239000002131 composite material Substances 0.000 claims description 9
- 239000012528 membrane Substances 0.000 claims description 9
- 229910004205 SiNX Inorganic materials 0.000 claims description 8
- 229910052802 copper Inorganic materials 0.000 claims description 8
- 238000000151 deposition Methods 0.000 claims description 8
- 230000008021 deposition Effects 0.000 claims description 8
- 229910052782 aluminium Inorganic materials 0.000 claims description 7
- 229910052750 molybdenum Inorganic materials 0.000 claims description 7
- 229910020286 SiOxNy Inorganic materials 0.000 claims description 6
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 6
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 6
- 230000015572 biosynthetic process Effects 0.000 claims description 4
- 238000004140 cleaning Methods 0.000 claims description 4
- 230000005611 electricity Effects 0.000 claims description 3
- 239000010408 film Substances 0.000 claims description 3
- 238000001259 photo etching Methods 0.000 description 21
- 229910016048 MoW Inorganic materials 0.000 description 8
- 239000004065 semiconductor Substances 0.000 description 5
- 238000004380 ashing Methods 0.000 description 3
- 238000005192 partition Methods 0.000 description 3
- 229910021417 amorphous silicon Inorganic materials 0.000 description 1
- 230000002950 deficient Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 239000004615 ingredient Substances 0.000 description 1
- 239000000463 material Substances 0.000 description 1
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Abstract
A pixel structure of film transistor LCD is featured as setting the first grate insulation layer, active layer and doped layer on grid and grate line; arranging cut-off groove on grate line to cut off active layer from doped layer; covering the second insulation layer on glass base plate; setting pixel electrode and drain electrode to be an integral unit being set above the second insulation layer and being lap-jointed with doped layer and covering passivation layer on external part of pixel electrode. Its preparing method is also disclosed.
Description
Technical field
The present invention relates to Thin Film Transistor-LCD and manufacture method thereof, pixel structure for thin film transistor liquid crystal display and manufacture method thereof that particularly a kind of third photo etching technology is made.
Background technology
At present in the method that conventional thin film transistor LCD device is made, array processes is used the method for five lay photoetching mask plates, a part adopts the method for four lay photoetching mask plates, and wherein four lay photoetching mask plates mainly adopt the technology of gray tone (Gray Tone) mask that metal electrode is leaked in the source of the channel part of thin film transistor (TFT) and active layer partly carries out etching.
The process sequence at conventional four lay photoetching mask plates of this structure comprises:
At first, utilize conventional grid technique to form the grid layer, deposit gate insulation layer then.
Then, metal level is leaked in deposited semiconductor active layer, doped layer and source.Utilize Gray Tone mask to form the island of thin film transistor (TFT), carry out cineration technics, expose channel part, the metal level of etching channel part, the doped layer of etching channel part, active layer.Because need be to active layer, metal level also has the etching of doped layer in this step process, thus in photoetching process, need the control of the photoresist of Gray Tone channel part quite strict, in addition the selection of etching than and homogeneity very high requirement is all arranged.So the tolerance for technology requires very high.
Summary of the invention
The objective of the invention is the defective at prior art, propose the way that a kind of thin-film transistor liquid crystal display array structure and third photo etching technology thereof are made this structure, it can reduce the design to the requirement of process allowance and simplification thin film transistor (TFT).
In order to realize above-mentioned technical purpose, the invention provides a kind of pixel structure for thin film transistor liquid crystal display, comprise: glass substrate, grid line, gate electrode, first grid insulation course, active layer, doped layer, second insulation course, data line, source electrode, drain electrode, pixel electrode and passivation layer wherein are followed successively by first grid insulation course, active layer and doped layer on gate electrode and the grid line; One interrupts grooves is arranged on the grid line, and it blocks doped layer and active layer on the grid line; Second insulation course covers on the outer glass substrate of interrupts grooves and grid line and gate electrode; Pixel electrode and drain electrode are one and are positioned at second insulation course top, and at position that forms drain electrode and the overlap joint of the doped layer on the gate electrode; Passivation layer covers the part outside the pixel electrode.
In the such scheme, described grid line and gate electrode are the monofilm of AlNd, Al, Cu, Mo, MoW or Cr, perhaps are one of AlNd, Al, Cu, Mo, MoW or Cr or composite membrane that combination in any constituted.The described first grid insulation course or second insulation course are the monofilm of SiNx, SiOx or SiOxNy, perhaps are one of SiNx, SiOx or SiOxNy or composite membrane that combination in any constituted.The monofilm of described source electrode, data line or leak electricity very Mo, MoW or Cr perhaps is one of Mo, MoW or Cr or composite membrane that combination in any constituted.
In order to realize above-mentioned technical purpose, the present invention provides a kind of manufacture method of pixel structure for thin film transistor liquid crystal display simultaneously, comprising:
Step 1 deposits the grid metal level, first grid insulation course successively on the substrate of cleaning, active layer, doped layer adopts first mask, this mask is the gray mask version, through obtaining not having photoresist zone, reserve part photoresist zone behind the exposure imaging and keeping whole photoresists zone; Etching does not have the photoresist zone and forms grid line and grid island figure; After finishing etching, photoresist is carried out cineration technics, all remove the photoresist in reserve part photoresist zone, remove the photoresist in the whole photoresists of the reservation zone of a part of thickness, expose the part doped layer on the grid line, then doped layer and active layer are carried out etching, obtain the interrupts grooves on the grid line, interrupts grooves is blocked doped layer and the active layer on the grid line; Then deposit second insulation course, adopt the liftoff stripping technology of photoresist, peel off second insulation course of grid line and grid island top;
Step 2, sedimentary origin leaks metal level on completing steps 1 substrate, adopts second mask, and this mask is the gray mask version, obtains not having the photoresist zone through behind the exposure imaging, reserve part photoresist zone and the whole photoresists of reservation zone; Etching does not have the photoresist zone and forms thin film transistor channel, and obtains the drain electrode figure of pixel electrode and one thereof and the source electrode pattern of data line and one thereof; After finishing etching, photoresist is carried out cineration technics, all remove the photoresist in reserve part photoresist zone, remove the photoresist in the whole photoresists of the reservation zone of a part of thickness, metal level is leaked in the source of exposing the source electrode zone of data line and one thereof; Deposit passivation layer adopts the liftoff stripping technology of photoresist, peels off the photoresist and the passivation layer of pixel electrode and drain electrode zone top; Metal level is leaked in the etching source, exposes second insulation course of pixel electrode area below and the doped layer of below, drain electrode zone;
Step 3, pixel deposition electrode film on completing steps 2 substrates adopts the 3rd mask to carry out mask, expose and carry out etching, obtains pixel electrode.
In the such scheme, described first mask is the zone beyond formation grid line and the grid island through the zone of no photoresist behind the exposure imaging; Reserve part photoresist zone is for forming the interrupts grooves zone on the grid line.Etching does not have the photoresist zone and comprises doped layer etching, active layer etching, first grid insulation course etching and grid metal level etching in the described step 1.Described second mask comprises the drain electrode zone that forms pixel electrode area and one thereof through the zone that keeps whole photoresists behind the exposure imaging; Reserve part photoresist zone comprises the source electrode that forms data line and one thereof; Other parts are no photoresist zone.Etching does not have the photoresist zone and obtains thin film transistor channel and comprise that partly the source leaks the etching of metal level etching and doped layer in the described step 2.
The present invention is with respect to prior art, owing to utilize the gray mask version and formed interrupts grooves on grid line and gate electrode, active layer, doped layer, second insulation course and the grid line in conjunction with liftoff stripping technology; And the present invention utilizes the gray mask version to form raceway groove simultaneously, metal level and pixel electrode are leaked in the source.Therefore, the present invention has saved the cost of array processes and has accounted for the machine time, has improved production capacity.
Simultaneously, the present invention is owing to adopt second insulation course to realize the planarization of technology in first gray mask version, for the technology of back has increased process allowance.
Moreover the present invention adopts the drain electrode of transparent metal electrode as thin film transistor (TFT), has avoided the problem of contact resistance.
Below in conjunction with the drawings and specific embodiments the present invention is further illustrated in more detail.
Description of drawings
Fig. 1 a is that the present invention adopts the figure that obtains after the photoetching of first gray tone (Gray-Tone) mask;
Fig. 1 b is that the present invention adopts the expose cross section figure at A-A ' position among Fig. 1 a of back of first gray mask version;
Fig. 1 c is that the present invention adopts the expose cross section figure at B-B ' position among Fig. 1 a of back of first gray mask version;
Fig. 1 d is the cross section figure at A-A ' position among Fig. 1 a after the present invention adopts first gray mask version to no photoresist district etching;
Fig. 1 e is that the present invention adopts first gray mask version that photoresist is carried out behind the cineration technics cross section figure at A-A ' position among Fig. 1 a;
Fig. 1 f is that the present invention adopts first gray mask version that photoresist is carried out behind the cineration technics cross section figure at B-B ' position among Fig. 1 a;
Fig. 1 g is the cross section figure at B-B ' position among Fig. 1 a after the present invention adopts first gray mask version to the active layer etching;
Fig. 1 h is the cross section figure at A-A ' position among Fig. 1 a behind the present invention's second insulating layer deposition;
Fig. 1 i is that the present invention carries out after liftoff peeling off (Lift-Off) technology cross section figure at A-A ' position among Fig. 1 a;
Fig. 1 j is the cross section figure that the present invention carries out B-B ' position among Fig. 1 a of liftoff peeling off (Lift-Off) back;
Fig. 1 k is a complete pixel planes pictorial diagram after the present invention adopts the first whole technology of mask to finish;
Fig. 2 a is the figure after second gray tone of the present invention (Gray Tone) mask photoetching;
Fig. 2 b is the cross section figure at C-C ' position among Fig. 2 a behind second gray tone of the present invention (Gray Tone) mask exposure;
Fig. 2 c is the cross section figure at C-C ' position among Fig. 2 a after second gray tone of the present invention (Gray Tone) mask does not have photoresist zone etching and finishes;
Fig. 2 d is the cross section figure at C-C ' position among Fig. 2 a behind second gray tone of the present invention (Gray Tone) mask photoresist ashing;
Fig. 2 e is the cross section figure at C-C ' position among Fig. 2 a after second gray tone of the present invention (Gray Tone) mask passivation layer deposition;
Fig. 2 f is the cross section figure at C-C ' position among Fig. 2 a after second gray tone of the present invention (Gray Tone) mask photoresist lift off;
Fig. 2 g is that the cross section figure at C-C ' position among Fig. 2 a is leaked after the metal level etching in second gray tone of the present invention (Gray Tone) mask source;
Fig. 3 a is the 3rd conventional mask photoetching back plane figure of the present invention;
Fig. 3 b is the cross section figure at D-D ' position among Fig. 3 a behind the 3rd conventional mask exposure of the present invention;
Fig. 3 c is the cross section figure at D-D ' position among the 3rd conventional mask pixel electrode etching Fig. 3 a of the present invention;
Fig. 3 d is the cross section figure at D-D ' position among Fig. 3 a after the 3rd conventional mask photoresist lift off of the present invention.
Mark among the figure: 20, glass substrate; 21, gate electrode; 22, first grid insulation course; 23, semiconductor active layer; 24, semiconductor doping layer; 25, the photoresist (Gray Tone) of the photoresist of photoetching for the first time part reserve area; 25 ', the photoresist (Full Tone) of the complete reserve area of the photoetching photoresist first time; 26, second insulation course; 27, metal electrode layer is leaked in the source; 28, the photoresist ((Gray Tone) of the photoresist of photoetching for the second time part reserve area; 28 ', the photoresist (Full Tone) of the complete reserve area of the photoetching photoresist second time; 29, pixel electrode; 30, photoetching for the third time forms photoresist; 31, passivation layer.
Embodiment
The invention provides a kind of pixel structure for thin film transistor liquid crystal display, comprise parts such as substrate, grid line, gate electrode, first insulation course, active layer, doped layer, second insulation course, source electrode, drain electrode, pixel electrode and passivation layer, these ingredients and prior art do not have difference, and other is characterised in that itself and dot structure phase region of the prior art: be followed successively by first grid insulation course, active layer and doped layer on gate electrode and the grid line; One interrupts grooves is arranged on the grid line, and expose first grid insulation course at the interrupts grooves position; Second insulation course covers on the outer glass substrate of interrupts grooves and grid line and gate electrode; Pixel electrode and drain electrode are one and are positioned at second insulation course top, and at position that forms drain electrode and the overlap joint of the doped layer on the gate electrode; Passivation layer covers the part outside the pixel electrode.
Grid line of the present invention and gate electrode can be the monofilm of AlNd, Al, Cu, Mo, MoW or Cr, perhaps are one of AlNd, Al, Cu, Mo, MoW or Cr or composite membrane that combination in any constituted.
The present invention's first insulation course or second insulation course can be the monofilm of SiNx, SiOx or SiOxNy, perhaps are one of SiNx, SiOx or SiOxNy or composite membrane that combination in any constituted.
The monofilm of source of the present invention electrode, data line or leak electricity very Mo, MoW or Cr perhaps is one of Mo, MoW or Cr or composite membrane that combination in any constituted.
The present invention provides this one pixel structure process method simultaneously, comprising:
Step 1 deposits the grid metal level, first grid insulation course successively on the substrate of cleaning, active layer, doped layer adopts first mask, this mask is the gray mask version, obtains not having the photoresist zone through behind the exposure imaging, reserve part photoresist zone and the whole photoresists of reservation zone; The zone of wherein not having photoresist is for forming grid line and grid island zone in addition; Reserve part photoresist zone is for forming interrupts grooves zone on the grid line.Etching does not have the photoresist zone and forms grid line and grid island figure, and the etching in this step comprises etching doped layer, active layer, first grid insulation course and grid metal level.After finishing etching, photoresist is carried out cineration technics, all remove the photoresist in reserve part photoresist zone, remove the photoresist in the whole photoresists of the reservation zone of a part of thickness, expose the part doped layer on the grid line, then doped layer is carried out etching, obtain the interrupts grooves on the grid line.At last, then deposit second insulation course, adopt the liftoff stripping technology of photoresist, peel off second insulation course of grid line and grid island top;
Step 2, sedimentary origin leaks metal level on completing steps 1 substrate, adopts second mask, and this mask is the gray mask version, obtains not having the photoresist zone through behind the exposure imaging, reserve part photoresist zone and the whole photoresists of reservation zone; The zone that wherein keeps whole photoresists comprises the drain electrode zone that forms pixel electrode and one thereof; Reserve part photoresist zone comprises the source electrode zone that forms data line and one thereof; Other parts are no photoresist zone.Etching does not have photoresist zone and forms thin film transistor channel and obtain pixel electrode and the drain electrode figure of one, and the source electrode pattern of data line and one; This step etching comprises the etching of source leakage metal level etching and doped layer.After finishing etching, photoresist is carried out cineration technics, all remove the photoresist in reserve part photoresist zone, remove the photoresist in the whole photoresists of the reservation zone of a part of thickness, metal level is leaked in the source of exposing the source electrode zone of data line and one thereof, at this moment the drain electrode of pixel electrode and one thereof top remainder photoresist.Deposit one deck passivation layer then, and adopt the liftoff stripping technology of photoresist, peel off the passivation layer and the photoresist of the drain electrode top of pixel electrode and one thereof, and the source leakage metal level of following pixel electrode and drain electrode zone carries out etching.
Step 3, pixel deposition electrode film on completing steps 2 substrates adopts the 3rd mask to carry out mask, expose and carry out etching, exposes the pixel electrode part figure.
Below in conjunction with accompanying drawing one pixel structure process method of the present invention is described in detail, shown in Fig. 1 a to Fig. 3 d.
At first, on the glass substrate 20 of cleaning, deposit grid metal 21 (Mo earlier, Al/Nd, Cu etc.), on the grid metal, deposit ground floor insulation course 22 (SiNx) again, deposited semiconductor active layer 23 on the ground floor insulation course (a-Si, p-Si etc.), and then deposited semiconductor doped layer 24 (doping B, P etc.).Adopt first gray mask version (Gray Tone) to carry out obtaining grid island figure behind the mask exposure, as shown in Figure 1a, Fig. 1 b is the cross section figure at A-A ' position, Fig. 1 c is the cross section figure at B-B ' position, other outer zones of grid line and gate electrode do not have photoresist as seen from the figure, forming the partition grooves position on the grid line is the photoresist 25 of the photoresist of photoetching for the first time part reserve area, and other zones and gate electrode partly are the photoresist 25 ' of the complete reserve area of the photoetching photoresist first time on the grid line.Carry out etching then, the zone of not protected by photoresist is etched away, the cross section figure at A-A ' position is shown in Fig. 1 d among Fig. 1 a.Carry out photoresist ashing technology then, the cross section figure at A-A ' position is shown in Fig. 1 e among Fig. 1 a, the cross section figure at B-B ' position is shown in Fig. 1 f among Fig. 1 b, by Fig. 1 f as seen, the locational doped layer of partition grooves exposes on the grid line, then this doped layer is carried out etching, obtain the partition grooves on the grid line, shown in Fig. 1 g.Deposit second insulation course gate electrode is protected, shown in Fig. 1 h, back exposure doped layer is peeled off at A-A ' position among Fig. 1 a, shown in Fig. 1 i; The active layer at B-B ' position is covered by second insulation course 26 among Fig. 1 b, shown in Fig. 1 j.
Then, metal electrode layer 27 (Mo, Al, Cu etc.) is leaked in deposition and source successively, adopts second gray tone (Gray Tone) mask, and the exposure back forms the photoresist of data line and pixel electrode shape, shown in Fig. 2 a.Photoresist ((Gray Tone) 28 at source electrode and data line one side formation photoetching for the second time photoresist part reserve area, form the photoresist (Full Tone) 28 ' of the complete reserve area of photoetching photoresist for the second time in drain electrode and pixel electrode area, shown in Fig. 2 b.Etching (etching of metal electrode layer and doped layer is leaked in the source) is carried out in the zone of not protected by photoresist, shown in Fig. 2 c.Then carry out photoresist ashing technology, shown in Fig. 2 d, metal electrode layer is leaked in the source of source electrode and linear position data come out, drain electrode and pixel electrode area top remainder photoresist.Carry out passivation layer 31 depositions then, shown in Fig. 2 e.And then in conjunction with the liftoff stripping technology of photoresist, will drain and pixel electrode area top remainder photoresist and passivation layer peel off together, expose the source leakage metal level 27 of drain electrode and pixel electrode area, shown in Fig. 2 f.At last, metal level 27 is leaked in the source of drain electrode and pixel electrode area carry out etching, expose second insulation course of channel part doped layer and pixel region, shown in Fig. 2 g.2b to 2g is the sectional view of C-C ' position among Fig. 2 a (raceway groove position) among the figure.
At last, pixel deposition electrode layer (SiNx etc.), and obtain the formation of photoetching for the third time photoresist 30 after utilizing conventional for the third time lay photoetching mask plate exposure, shown in Fig. 3 a, the sectional view at D-D ' position is shown in Fig. 3 b among Fig. 3 a.Then, carry out the pixel electrode layer etching, shown in Fig. 3 c.At last, carry out photoresist stripping process, finish the making of pixel electrode 29, and form final figure, shown in Fig. 3 d.
In the present embodiment owing to utilize first gray mask version and liftoff stripping technology to form interrupts grooves on grid line and gate electrode, active layer, doped layer, second insulation course and the grid line; Utilize second gray mask version to form raceway groove, source simultaneously and leak metal level, therefore saved the cost of array processes and account for the machine time, improved production capacity.In addition, because present embodiment adopts second insulation course to realize the planarization of technology in first gray mask version, for the technology of back has increased process allowance.Moreover, owing to adopt of the drain electrode of transparent metal electrode in the present embodiment, avoided the problem of contact resistance as thin film transistor (TFT).
It should be noted that at last, above embodiment is only unrestricted in order to technical scheme of the present invention to be described, although the present invention is had been described in detail with reference to preferred embodiment, those of ordinary skill in the art should can use different materials and equipment to realize it as required, promptly can make amendment or be equal to replacement, and not break away from the spirit and scope of technical solution of the present invention technical scheme of the present invention.
Claims (9)
1, a kind of pixel structure for thin film transistor liquid crystal display, comprise: glass substrate, grid line, gate electrode, first grid insulation course, active layer, doped layer, second insulation course, data line, source electrode, drain electrode, pixel electrode and passivation layer is characterized in that: be followed successively by first grid insulation course, active layer and doped layer on gate electrode and the grid line; One interrupts grooves is arranged on the grid line, and it blocks doped layer and active layer on the grid line; Second insulation course covers on the outer glass substrate of interrupts grooves and grid line and gate electrode; Pixel electrode and drain electrode are one and are positioned at second insulation course top, and at position that forms drain electrode and the overlap joint of the doped layer on the gate electrode; Passivation layer covers the part outside the pixel electrode.
2, dot structure according to claim 1 is characterized in that: described grid line and gate electrode are the monofilm of AlNd, Al, Cu, Mo, MoW or Cr, perhaps are one of AlNd, Al, Cu, Mo, MoW or Cr or composite membrane that combination in any constituted.
3, dot structure according to claim 1 is characterized in that: the described first grid insulation course or second insulation course are the monofilm of SiNx, SiOx or SiOxNy, perhaps are one of SiNx, SiOx or SiOxNy or composite membrane that combination in any constituted.
4, dot structure according to claim 1 is characterized in that: the monofilm of described source electrode, data line or leak electricity very Mo, MoW or Cr perhaps is one of Mo, MoW or Cr or composite membrane that combination in any constituted.
5, a kind of manufacture method of pixel structure for thin film transistor liquid crystal display is characterized in that, comprising:
Step 1 deposits the grid metal level, first grid insulation course successively on the substrate of cleaning, active layer, doped layer adopts first mask, this mask is the gray mask version, through obtaining not having photoresist zone, reserve part photoresist zone behind the exposure imaging and keeping whole photoresists zone; Etching does not have the photoresist zone and forms grid line and grid island figure; After finishing etching, photoresist is carried out cineration technics, all remove the photoresist in reserve part photoresist zone, remove the photoresist in the whole photoresists of the reservation zone of a part of thickness, expose the part doped layer on the grid line, then doped layer and active layer are carried out etching, obtain the interrupts grooves on the grid line, interrupts grooves is blocked doped layer and the active layer on the grid line; Then deposit second insulation course, adopt the liftoff stripping technology of photoresist, peel off second insulation course of grid line and grid island top;
Step 2, sedimentary origin leaks metal level on completing steps 1 substrate, adopts second mask, and this mask is the gray mask version, obtains not having the photoresist zone through behind the exposure imaging, reserve part photoresist zone and the whole photoresists of reservation zone; Etching does not have the photoresist zone and forms thin film transistor channel, and obtains the drain electrode figure of pixel electrode and one thereof and the source electrode pattern of data line and one thereof; After finishing etching, photoresist is carried out cineration technics, all remove the photoresist in reserve part photoresist zone, remove the photoresist in the whole photoresists of the reservation zone of a part of thickness, metal level is leaked in the source of exposing the source electrode zone of data line and one thereof; Deposit passivation layer adopts the liftoff stripping technology of photoresist, peels off the photoresist and the passivation layer of pixel electrode and drain electrode zone top; Metal level is leaked in the etching source, exposes second insulation course of pixel electrode area below and the doped layer of below, drain electrode zone;
Step 3, pixel deposition electrode film on completing steps 2 substrates adopts the 3rd mask to carry out mask, expose and carry out etching, obtains pixel electrode.
6, manufacture method according to claim 5 is characterized in that: described first mask is the zone beyond formation grid line and the grid island through the zone of no photoresist behind the exposure imaging; Reserve part photoresist zone is for forming the interrupts grooves zone on the grid line.
7, according to claim 5 or 6 described manufacture methods, it is characterized in that: etching does not have the photoresist zone and comprises doped layer etching, active layer etching, first grid insulation course etching and grid metal level etching in the described step 1.
8, manufacture method according to claim 5 is characterized in that: described second mask comprises the drain electrode zone that forms pixel electrode area and one thereof through the zone that keeps whole photoresists behind the exposure imaging; Reserve part photoresist zone comprises the source electrode that forms data line and one thereof; Other parts are no photoresist zone.
9, according to claim 5 or 8 described manufacture methods, it is characterized in that: etching does not have the photoresist zone and obtains thin film transistor channel and comprise that partly the source leaks the etching of metal level etching and doped layer in the described step 2.
Priority Applications (5)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2006101451136A CN100444012C (en) | 2006-11-10 | 2006-11-10 | Pixel structure of liquid crystal display of thin film transistor, and fabricating method |
| KR1020070114476A KR100917654B1 (en) | 2006-11-10 | 2007-11-09 | TFT-LCD pixel unit and method for manufacturing the same |
| US11/938,416 US7892897B2 (en) | 2006-11-10 | 2007-11-12 | TFT-LCD pixel unit and method for manufacturing the same |
| JP2007293686A JP4837649B2 (en) | 2006-11-10 | 2007-11-12 | Thin film transistor liquid crystal display pixel structure and manufacturing method thereof |
| US13/007,884 US8134158B2 (en) | 2006-11-10 | 2011-01-17 | TFT-LCD pixel unit and method for manufacturing the same |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2006101451136A CN100444012C (en) | 2006-11-10 | 2006-11-10 | Pixel structure of liquid crystal display of thin film transistor, and fabricating method |
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| CN1959510A CN1959510A (en) | 2007-05-09 |
| CN100444012C true CN100444012C (en) | 2008-12-17 |
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| CN101364016B (en) * | 2007-08-10 | 2010-04-21 | 北京京东方光电科技有限公司 | Thin-film transistor LCD pixel structure and its making method |
| CN102637636A (en) | 2011-08-24 | 2012-08-15 | 京东方科技集团股份有限公司 | Organic thin-film transistor array substrate, method for manufacturing same and display device |
| CN103489918A (en) * | 2012-06-08 | 2014-01-01 | 京东方科技集团股份有限公司 | Thin-film transistor, array substrate and manufacturing method thereof |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2005283691A (en) * | 2004-03-29 | 2005-10-13 | Quanta Display Japan Inc | Liquid crystal display |
| CN1707338A (en) * | 2004-06-05 | 2005-12-14 | Lg.菲利浦Lcd株式会社 | Liquid crystal display device and fabricating method thereof |
| CN1244891C (en) * | 1992-08-27 | 2006-03-08 | 株式会社半导体能源研究所 | Active matrix display |
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1244891C (en) * | 1992-08-27 | 2006-03-08 | 株式会社半导体能源研究所 | Active matrix display |
| JP2005283691A (en) * | 2004-03-29 | 2005-10-13 | Quanta Display Japan Inc | Liquid crystal display |
| CN1707338A (en) * | 2004-06-05 | 2005-12-14 | Lg.菲利浦Lcd株式会社 | Liquid crystal display device and fabricating method thereof |
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