CN100386812C - Code modulation method and device, demodulation method and device - Google Patents
Code modulation method and device, demodulation method and device Download PDFInfo
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Abstract
The present invention relates to a code modulation method and a device thereof, and a code demodulation method and a device thereof which belong to the field of CD data processing technology. The code modulation method with two third of code rate the same as that of 8 modulation to 12 modulation and a device thereof of the present invention are used in the way that a data bit sequence is firstly converted into a channel bit sequence, and partial code types are permuted according to a connection rule so as to obtain a code type without the run length of 1 for more than continuous 6 times in the channel bit sequence. A dk control bit and a DSV control bit exist in the channel bit sequence, and the number of a bit '0' between adjacent bits '1' in the channel bit sequence at least is 1, and at most is k by controlling the value of the dk control bit. The amplitude of the frequency component obtained after modulation of the channel bit sequence in the frequency below 1/10000 in channel clocking frequency is more than 20dB as high as that of the maximum value of the frequency component. Simultaneously, the present invention also discloses the demodulation method for the coded channel bit sequence and the device thereof.
Description
Technical field
The present invention relates to code modulating method and modulating device, demodulation method and the demodulating equipment of use when enterprising line number digital data record of CD or regeneration, belong to the data of optical disk processing technology field.
Background technology
In optical storage system, to before data recording is to the CD, modulate usually the data sequence in order to be fit to recording medium.Conventional optical disk system all adopts the limited code modulating method of run length (being called for short the brigade commander), i.e. RLL (Run Length Limited, run length) coding.RLL is meant that the channels bits sequence that CD is stored meets the following conditions: in the channels bits sequence, between the phase ortho position ' 1 ' the rarest d position ' 0 ', and k position ' 0 ' arranged at most.These two parameter separate provision of d and k may appear at minimum and maximum run in the sequence.Parameter d is being controlled high-transmission frequency, the intersymbol interference in the time of therefore may influencing sequence and transmit by bandwidth efficient channel.In the binary data transmission, wish that usually the signal that receives is can be self synchronous.Usually utilize a phaselocked loop to reproduce synchronously.Phaselocked loop is adjusted according to the saltus step of the waveform that receives and is detected phase place constantly.Maximum run parameter k guarantees that suitable jump frequency is to satisfy the needs that read clock synchronization.In optical storage system, parameter d gets 1 or 2 usually, and the k value is got about 10, and the more little recovery that helps clock more of parameter k.
When recording medium is carried out data recording and data reproduction, if comprise flip-flop in this record regenerating signal, then can make the signal that uses in the servocontrol of optical disc apparatus become and be easy to generate change, perhaps become and fluctuate easily.Therefore, in optical storage system, in order to prevent or to reduce interacting between the low-frequency component of read output signal and tracking servo signal, also require modulating-coding can suppress to encode back channels bits sequence, promptly have the characteristic of dc balance at the component of low-frequency range.Adopt the dc balance sign indicating number also to help to eliminate the influence of low-frequency disturbance that fingerprint etc. causes to read output signal.Run length limited code with dc balance characteristic is called as the run length limited code of dc balance.
For example, adopted d=2 in DVD (Digital Versatile Disc), the run length limited code of the dc balance of k=10 also claims EFMPlus modulation.This coding can convert the data source word that 8 data bit constitute to the channel code word that 16 channels bits constitute, and in the channels bits sequence after modulation, has 2 between phase ortho position " 1 " at least 10 positions " 0 " are arranged at the most.At RLL (2,10) in the rule, the minimum number (being called minimum run length) of the position " 0 " that comprises between " d=2 " the expression phase ortho position " 1 " is 2, on the other hand, the maximum number (being called maximum run length) continuously of the position " 0 " that comprises between " k=10 " the expression phase ortho position " 1 " is 10.In addition, the EFMPlus modulation has by the selective channel code word suppresses the function of flip-flop from a plurality of tables according to DSV (Digital Sum Value).DSV is the head of the channels bits sequence after the NRZI conversion, when the position is " 1 ", get+1, get-1 when " 0 ", the summation after the addition is the desired value substantially of the flip-flop size of channels bits sequence successively.The EFMPlus modulation can suppress the flip-flop change of channels bits sequence by select to make the channel code word of DSV minimum from pre-prepd a plurality of tables.
As described above, EFMPlus modulation is the modulator approach that data bit sequence is divided into 8 data source word and is transformed to 16 channel code word, and the code check that can obtain its coding according to the ratio of data bit sequence and channels bits sequence is 1/2.When the code check of coding means per 1 that detects the channels bits sequence greatly the utilizable time elongated, therefore, wish that for high-density memory system the code check of encoding is the bigger the better.In recent years, along with data of optical disk reads and the raising of signal processing technology, PRML (PRML) technology is applied in the optical storage system.Therefore, being suitable for high density " d=1 " modulating-coding storage, that have higher encoder bit rate has obtained using widely.
Especially, for the regenerated signal of high-density optical disk, because the signal amplitude of the short sign indicating number type (pattern) of mark lengths and space length diminishes, so the judgement of its channels bits sequence comparison difficulty that becomes.Because signal amplitude reduces, use when utilizing peak-value detection method that regenerated signal is carried out binary conversion treatment, take place easily because the erroneous judgement situation that noise causes.Recur the problem that causes by minimum run length, disclosed spy opened in the flat 11-346154 communique and is pointed out on Dec 14th, 1999.
By adopting RPML (PRML) technology can under the situation that only the shortest mark lengths and space length shorten, remedy the influence that amplitude reduces.PRML detects, and compares by channels bits sequence and reproduction waveform to a plurality of candidates, selects near the candidate channel bit sequence of the reproduction waveform result as detection.Therefore, compare traditional peak-value detection method, PRML detects can further reduce the detection error.
But detect for PRML, also have a kind of situation that detects error that causes easily: run length is " 1 " continuously in the channels bits sequence, and NRZI is equivalent to the shortest mark when writing down and the shortest space 2T sign indicating number type recurs, and T is a channel bit length.Though can distinguish the reproduction waveform of 2T sign indicating number type and the reproduction waveform of more than the 3T yard type by using PRML to detect, but for continuous 2T sign indicating number type, only be difficult to determine the phase place of channels bits sequence according to the reproduction waveform of this part, if have noise to sneak into reproduction waveform this moment again, then be easy to cause the error-detecting result of the continuous all 1T offsets of 2T sign indicating number type.In this case, the scope that departs from detection directly has influence on all errors, causes the detection error that relates to a plurality of bytes easily.Therefore, for fear of the propagation of this type detection error, need limit the number of times that 2T sign indicating number type occurs continuously by modulating-coding.
In addition, be 1 the pairing regenerated signal of 2T sign indicating number type for continuous minimum run length, because therefore less the and continued presence of its regenerated signal amplitude exists the problem that is difficult to extract out channel clock from regenerated signal.Aspect the stability of guaranteeing the channel clock extraction, also need the number of times that 2T sign indicating number type occurs is continuously limited.
Disclosed patent US2004/0207545 announced and had than the higher 8-12 modulation technique of EFMPlus modulation code check on October 21st, 2004.The 8-12 modulation technique can be converted to 8 data source word 12 channel code word, the number of position " 0 " is at least 1 between phase ortho position " 1 " in the channels bits sequence, be at most 10, continuous run length more than 5 times do not occur simultaneously and be 1 sign indicating number type " 1010101010101 ".But the 8-12 modulation needs 2 owing to convert 8 bit data source words to 12 bit channel code words
8=256 or more kinds of transformation model, conversion table becomes very huge as a result, and modulating/demodulating is handled (conversion process) and become very complicated.
On September 23rd, 2004, disclosed patent US2004/0183704 announced the modulation technique that 4 bit data source words is converted to 6 bit channel code words, only needed 2
4=16 kinds of translative mode are just enough, so conversion table is small-sized.But, therefore can not satisfy the requirement of storage system owing to can not effectively limit the number of times that 2T sign indicating number type occurs continuously.
In addition, the spy opens flat 11-346154 communique and discloses and use the map table with conversion fraction, with being limited in below the stipulated number continuously of minimum run length.But the spy opens flat 11-346154 communique and utilizes Variable Length Code, does not consider the code check of coding, and the modulating/demodulating of variable length code is handled more complicated simultaneously.
Summary of the invention
In order to solve the too complicated or easy problem that causes regenerated signal detection error codes type of appearance of coding modulation technique that has now, the invention provides a kind of simple more code modulating method and device, demodulation method and device, it has and 8-12 modulation same code rate, guarantee in the channels bits sequence, not occur causing easily the modulating-coding that regenerated signal detects the sign indicating number type of error simultaneously, the flip-flop that obtains signal after channels bits sequence after guaranteeing in addition to modulate is changed through NRZI is lower, to be fit to the requirement of high-density recording recording system.
Technical scheme of the present invention is as follows:
A kind of code modulating method, the data bit sequence that the 2n position is constituted is transformed to the channels bits sequence of 3n position, and n is an integer, it is characterized in that, and described modulator approach comprises the steps:
Utilize modulation circuit, the 2n bit data cut apart by per 4 obtain the data source word, according to coding schedule each data source word is converted to 6 bit channel code words, channel code word process that obtains and string conversion and order are exported, obtain the 3n bit data, wherein said coding schedule has two subcode tables that comprise 16 6 bit channel code words, 16 6 bit channel code words of one of them subcode table start with position " 1 " or " 0000 ", and 16 6 bit channel code words of another subcode table are with " 01 ", " 001 " or " 0001 " beginning, having the tail sign indicating number of a code word in addition in each subcode table at least is dk control bit or DSV control bit;
Channel code word and subsequent channel code word are united definite concatenate rule to modulation circuit in advance according to using, after the sign indicating number type that meets concatenate rule in the 3n bit data replaced, obtain new 3n bit data, wherein said concatenate rule comprises all makes the code word that occurs " 101010101010101 " in the channels bits sequence connect situation, and the code word after the displacement connects and connected and composed by the code word that can not obtain according to the coding rule in the described coding schedule;
By being position ' 0 ', position ' 1 ' or DSV control bit ' # ' according to dk control law assignment to the dk control bit in the new 3n bit data, obtain comprising the 3n bit data of DSV control bit, guarantee no matter DSV control bit value is " 0 " or " 1 ", the number of the position " 0 " between the phase ortho position " 1 " in the channels bits sequence that finally obtains is 1 to be k at the most at least, and wherein k is the integer more than or equal to 9;
Afterwards, be position " 0 " or position " 1 " by select the DSV control bit according to DSV, obtain finally definite 3n bit channel bit sequence, and it is carried out the NRZI conversion.
The present invention also provides the coded modulation that realizes code modulating method of the present invention device, it is characterized in that, described coded modulation device comprises:
The memory encoding table, and by described coding schedule of reference and status information, the data source word is converted to the coding schedule change-over circuit of channel code word, the coding schedule of described coding schedule change-over circuit storage comprises: with the corresponding channel code word that constitutes by position " 0 ", position " 1 ", dk control bit or DSV control bit of 4 bit data source words, and the status information of subcode table that should reference during the next data source word of expression conversion;
When the channel code word is connected to each other, the channel code word that satisfies concatenate rule is replaced the coupled circuit that obtains the channels bits sequence; Described concatenate rule is to use that in advance channel code word and subsequent channel code word are united definite;
According to the dk limiter that determines the value of dk control bit before the dk control bit with information following closely; And
DSV controller according to the value of the previous DSV control bit of the DSV decision of the channels bits sequence that calculates.
The method that the present invention also provides a kind of channels bits sequence that above-mentioned coded modulation is obtained to carry out demodulation is characterized in that described demodulation method comprises the steps:
Utilizing demodulator circuit, extract synchronous code-type from the channels bits sequence that obtains, is basic point with the synchronous code-type of extracting out, determines the border of per 6 bit channel code words;
Boundary information according to the channel code word that obtains, from the channels bits sequence, detect the sign indicating number type of being replaced according to concatenate rule, and cut apart rule according to the displacement that obtains by described concatenate rule and realize the displacement of continuous channel code word is cut apart, wherein said concatenate rule is by channel code word and subsequent channel code word are united definite in advance;
According to current code word to be decoded following closely 6 bit channel code words or the information of synchronous code-type, select to need use with the corresponding subsolution mileometer adjustment of coding schedule;
According to current code word to be decoded and selected subsolution mileometer adjustment, obtain 4 bit data source words.
The present invention also provides a kind of demodulating equipment of realizing above-mentioned demodulation method, it is characterized in that, described demodulating equipment comprises:
From the channels bits sequence, detect the synchronous code-type testing circuit of the synchronous code-type of insertion;
Cut apart permutation circuit, the described permutation circuit of cutting apart is used for detecting according to the channel code word concatenate rule of the consecutive hours sign indicating number type of being replaced each other, cuts apart rule according to displacement and is replaced into sign indicating number type before connecting, and be divided into 6 bit channel code words;
According to the 6 follow-up bit channel code words or the information of synchronous code-type, circuit is selected in the subsolution mileometer adjustment that the subsolution mileometer adjustment that is used for current 6 bit channel codeword decodings is selected; And
Store the demodulation table change-over circuit of demodulation table, described demodulation table change-over circuit is converted to 4 bit data source words according to the subsolution mileometer adjustment of selecting with 6 bit channel code words.
Code modulating method of the present invention and device have and 8-12 modulation phase encoder bit rate together, the flip-flop that the channels bits sequence that obtains after utilizing described code modulating method and device to the data bit sequence modulation that generates is at random carried out the signal that obtains after the NRZI conversion is very little, do not occur in the channels bits sequence simultaneously making easily that the sign indicating number type of error appears detecting in regenerated signal, satisfied the requirement of high-density recording recording system.In the present invention, owing to can realize modulation and demodulation by less coding schedule and demodulation table, so coded modulation device and demodulating equipment are more prone to realization.
Particularly, it is 4/6 that the present invention can obtain encoder bit rate, the minimum value of run length is 1, maximal value is k, wherein k is the integer more than or equal to 9, and the number of times that run length 1 occurs continuously is limited in 6 times and following channels bits sequence, considers the border of channel code word, is avoided the effect that influence involves 3 bytes.In addition, it is very little to obtain low-frequency component, and the channels bits sequence of suitable high density recording, and in the frequency of 10,000 of channel clock frequency/following, oscillator intensity is compared more than the little 20dB with maximal value.On the other hand, separating timing, can be that unit handles with 6 channel code word, and because only with reference to current channel code word and 6 bit channel code word or synchronous code-types following closely, so its circuit structure has the very difficult characteristics of propagating of demodulating error.In addition, even under the high situation of recording density, also easily channel clock is stably extracted out, and be difficult to take place to detect error.
Description of drawings
Fig. 1 is the structural drawing of modulation circuit of the present invention;
Fig. 2 is the process flow diagram of expression modulator approach of the present invention;
Fig. 3 is the figure of the frequency characteristic of presentation code;
Fig. 4 is the DSV characteristic evaluation result who is used to illustrate the channels bits sequence after data transfer device and device are changed according to an embodiment of the invention;
Fig. 5 is the process flow diagram of expression demodulation method of the present invention;
Fig. 6 is the structural drawing of demodulator circuit of the present invention.
Embodiment
For clear and definite above-mentioned and other purpose, feature and advantage of the present invention, be elaborated with reference to the embodiment of accompanying drawing to a preferred embodiment of the present invention.
In an embodiment, utilize modulation circuit, at first the 2n bit data is cut apart by per 4 and obtained the data source word, each data source word is converted to 6 bit channel code words according to coding schedule, channel code word process that obtains and string conversion and order are exported, and obtain the 3n bit data.Table 1 illustrates a coding schedule that can be used for code modulating method of the present invention, wherein said coding schedule has two subcode tables that comprise 16 6 bit channel code words, 16 6 bit channel code words of one of them subcode table are with position " 1 " or " 0000 " beginning, and 16 6 bit channel code words of another subcode table are with " 01 ", " 001 " or " 0001 " beginning.
In the coding schedule shown in the table 1, in the 6 bit channel code words except position ' 0 ' and position ' 1 ", also used position ' * ' and ' # '.Position ' * ' (* ∈ 0,1, #}, wherein # ∈ 0,1}) represent that it is a dk control bit, its value is determined by the dk limiter shown in Fig. 1 106, or is determined jointly by dk limiter 106 shown in Fig. 1 and DSV controller 107.Particularly, the dk control bit is according to one value after the described dk control bit, and in the channels bits sequence before described dk control bit and the number that follows the continuous position " 0 " after the described dk control bit closely determine it is position " 0 ", " 1 " or DSV control bit.Position ' # ' represents that this position is a DSV control bit, and its value is determined by the DSV controller shown in Fig. 1 107.In addition, having the tail sign indicating number of a code word in the described coding schedule in each subcode table at least is dk control bit or DSV control bit.Respectively corresponding two states of two sub-code tables of described coding schedule, state 0 and state 1, and include 4 data source word and 6 channel code word, and expression should reference when the next data source word of conversion the status information of subcode table, this status information is used to specify next data source word when changing used subcode table.
Table 1: the coding schedule that uses in the modulator approach of the present invention
In the coding schedule shown in the table 1,4 bit data source words are corresponding mutually with NextState information, and wherein 4 bit data source words are represented with its corresponding sexadecimal number 0 to F.In the coding schedule shown in the table 1, each source word all has one " NextState " corresponding with it in two sub-code tables, and the value of " NextState " has defined the state that the coding schedule change-over circuit should enter after converting this data source word.The coding schedule change-over circuit selects the subcode table corresponding with this state to carry out coded modulation according to the present located state, promptly after finishing current data source word code conversion, can enter next state automatically and select the subcode table corresponding to be used for the coding of next data source word, repeat said process until end-of-encode with it.With coded modulation of the present invention, carry out 4 data source word is converted to 6 channel code word, the code check R=4/6 of its coding.
The NextState information of representing in two sub-code tables according to table 1 expression is come the chooser code table, when the channel code word that obtains is connected to each other, no matter the final value of dk control bit and DSV control bit how, all discontinuous appearance position " 1 " in the channels bits sequence that finally obtains, and the number that occurs position " 0 " continuously always is not more than k, and wherein k is the integer more than or equal to 9.Because discontinuous appearance " 1 " in the channels bits sequence, the channels bits sequence is carried out the NRZI conversion and when writing down, all more than 2T, T is a channel bit length for the mark of generation and space length.That is, can obtain minimum run length according to the coding schedule of table 1 expression is 1, maximum run length be k RLL (1, k) coding, wherein k is the integer more than or equal to 9.Use this coding can not produce mark and the space shorter, therefore can avoid occurring the difficulty that writes down and detect than 2T.
In addition, when the channel code word is connected to each other, channel code word and subsequent channel code word are united definite concatenate rule to modulation circuit in advance according to using shown in the table 2, after the sign indicating number type that meets concatenate rule in the 3n bit data replaced, obtain new 3n bit data, wherein said concatenate rule comprises all makes the code word that occurs " 101010101010101 " in the channels bits sequence connect situation, and the code word after the displacement connects and connected and composed by the code word that can not obtain according to the coding rule in the described coding schedule.By replacing, can be that 1 sign indicating number type " 101010101010101 " is got rid of from the channels bits sequence with continuous run length more than 6 times according to the concatenate rule shown in the table 2.Run length is the mark and the space of 1 sign indicating number type the shortest 2T length when becoming record after through the NRZI conversion.Because the run length 1 that occurs is no more than 6 times continuously, therefore can avoids the less situation of regenerated signal amplitude to continue to occur, thereby can not bring difficulty the regeneration of clock.Concatenate rule in the table 2 is to close definite by four continuous channel code couplets, to connect consistent channel code word linker substitution with code word before the displacement in the table 2 and become by the code word that can not obtain to connect according to the coding rule in the described coding schedule, for example " 001,001 000,010 101 "Because the NextState of code word " 001001 " only is 1 in the coding schedule shown in the table 1, therefore can not obtain the code word connection of " 001,001 000010 " according to coding schedule shown in the table 1, therefore " 001,001 000,010 101 " be that the code word that can not obtain according to the coding rule in the described coding schedule connects.In addition, in the table 2 displacement before the sign indicating number type in represent "? " represent that this position can be any one among " 0 ", " # ", " * ", after displacement, "? " the position keep value before the displacement.In the channels bits sequence according to the concatenate rule displacement, comprise that all make that run length 1 may continuous sign indicating number type more than 6 times when the channel code word was connected to each other.In addition, because concatenate rule is replaced into this channels bits sequence according to the unavailable code word connection of table 1 coding schedule, is therefore separating the sign indicating number type that timing detects the process displacement easily, and it is being recovered to the preceding sign indicating number type of displacement.
Table 2 is tables of the concatenate rule that uses in the modulator approach of the present invention of expression;
If use the coding schedule of table 1 and the concatenate rule of table 2, can obtain encoder bit rate and be 4/6, the minimum value of run length is 1, maximal value is k, wherein k is the integer more than or equal to 9, and run length 1 continuous number of times is limited in 6 times and following channels bits sequence.If this channels bits sequence is carried out the NRZI conversion and is used for data recording, satisfy mark lengths and space length at (k+1) more than the 2T below the T, and the mark of 2T and the only continuous 6 times condition of space maximum.The zone that the mark of 2T and space are continuous because the amplitude of regenerated signal is insufficient, causes the detection error of data easily.Because the number of times that 2T sign indicating number type is occurred continuously is limited in 6 times and below, can suppress easily to cause the appearance of the sign indicating number type of error.
In addition, even under the continuous situation of 2T sign indicating number type, if 2T sign indicating number type read-around ratio is limited in below 6 times, its length becomes below the 12T so.Under the situation of using PRML to detect, the whole detection error that 1T amount deviation takes place easily of continuous 2T sign indicating number type, and if read-around ratio below 6 times, can be suppressed at 14 to the scope of the influence of deviation expansion below the channel bit.Through after the demodulation, can will detect error control in 2 bytes.
In addition, when the channels bits sequence is long, sometimes owing to the demodulating error that takes place synchronously that departs from channel clock, for fear of this situation, usually, the coded modulation device comprises that also synchronous code-type inserts circuit, and described synchronous code-type inserts circuitry stores that to comprise run length be the above synchronous code-type of k, and wherein k is the integer more than or equal to 9.In the process of utilizing described modulation circuit to data conversions, described synchronous code-type inserts circuit, and will to comprise run length be that the above synchronous code-type of k inserts in the channels bits sequence cycle according to the rules, and wherein k is the integer more than or equal to 9.Therefore, if when regeneration, deviation took place synchronously, so in the moment that detects next synchronous code-type, can detect deviation synchronously, thereby avoid error continuous afterwards.
For storage system, in order to guarantee clock recovery, parameter k should be not excessive, selects parameter k=10 usually, so do not occur the above sign indicating number type of run length k=10 in the channels bits sequence.Therefore adopt to comprise the synchronous code-type that run length is 12 condition code type " 10000000000001 ", can be different from the sign indicating number type that the concatenate rule of the modulometer of use table 1 and table 2 obtains.Table 3 shows the synchronous code-type that code modulating method of the present invention uses, and it is identical with the synchronous code-type that patent US2004/0207545 is adopted, but the status number difference.As shown in table 3, SY0 has identical condition code type to four kinds of synchronous code-types of SY3, and adheres to two states separately, after guaranteeing to insert synchronous code-type in the channels bits sequence, minimum run length is that 1 constraint is not destroyed, and do not occur continuous more than 6 times run length be 1 sign indicating number type.The status information that synchronous code-type among Fig. 1 inserts circuit 104 to be provided according to status register 103 selects to insert synchronous code-type, behind each insertion synchronous code-type, the status information of status register 103 becomes state 1, continues coding this moment and the situation that continuous position " 1 " occurs can not occur.In addition, owing to get k=10, the sign indicating number type that does not have run length 11 in the channels bits sequence equally, synchronous code-type can also be to be feature with the sign indicating number type that comprises run length 11, and the sign indicating number type of sign indicating number type " 1000000000001 " that is about to comprise run length 11 is as synchronous code-type.In addition, when using synchronous code-type, for fear of the continuous appearance more than 6 times of the sign indicating number type of run length 1, channel code word and synchronous code-type also should be replaced with reference to the concatenate rule shown in the table 2 when being connected.
Table 3 is tables of the synchronous code-type that uses in the modulator approach of the present invention of expression;
| Synchronous code- | State | 0 | |
| SY0 | 1000#0?010000?000000?001001 | 0100#0?010000?000000?001001 | |
| SY1 | 10100#010000?000000?001001 | 00100#?010000?000000?001001 | |
| SY2 | 10010#010000?000000?001001 | 00010#?010000?000000?001001 | |
| SY3 | 00000#010000?000000?001001 | 00#010?010000?000000?001001 |
All comprise 1 DSV control bit that can be chosen as position " 0 " or position " 1 " in each synchronous code-type according to DSV (Digital Sum Value).Owing to still have the local channel code word not comprise dk control bit or DSV control bit in table 1 coding schedule, therefore in the channels bits sequence of modulation back after through dk limiter 106, may have the situation that does not occur the DSV control bit in the channels bits sequence, still can utilize the DSV control bit in the synchronous code-type that the DC component of the channels bits sequence between the synchronous code-type is controlled this moment.According to code modulating method of the present invention, the value of DSV control bit can not be determined before next DSV control bit occurs.
Four kinds of sign indicating number type SY0 to SY3 as synchronous code-type is provided with can select arbitrarily, and by well-regulated selection, can be according to detected synchronous code-type, general definite its position in the allocated channel bit sequence.If do not need assigned address, can select to use SY0 to SY3 at random, also can only use one kind of SY0.In addition, synchronous code-type is not limited to the sign indicating number type of expression here, can select length arbitrarily.According to the deciding means of synchronous code-type, can comprise and change the status information that the subcode table that uses behind the synchronous code-type is inserted in expression.
Fig. 1 illustrates the circuit block diagram of the coded modulation device (being modulation circuit) that proposes according to the present invention, this modulation circuit can utilize complex programmable logic device (CPLD), realizations such as field-programmables array FPGA or special chip belong to the known technology in the Design of Digital Circuit field.Modulation circuit as shown in the figure has coding schedule change-over circuit 101, status register 103, synchronous code-type insertion circuit 104 and multiplexer 109.Coding schedule change-over circuit 101 stores the described coding schedule of table 1 expression, the status information of subcode table that should reference when it comprises with the next data source word of the corresponding channel code word that is made of position " 0 ", position " 1 ", dk control bit or DSV control bit of 4 bit data source words and expression conversion.Arbitrarily the status information S (t) that is divided into 4 one group data source word B (t) and provides with status register 103 of user data at random enters coding schedule change-over circuit 101.Coding schedule change-over circuit 101 converts the data source word B (t) that imports to 6 bit channel code word X (t) by described coding schedule and status information S (t) with reference to table 1 expression; On the other hand, the described coding schedule according to table 1 expression outputs to multiplexer 109 to NextState information S (t+1).Multiplexer 109 also Secondary Synchronization Code type insertion circuit 104 obtains NextState information, multiplexer 109 is selected it, and the NextState information S (t+1) of expression NextState outputed to status register 103, the status information S (t+1) that status register 103 will be corresponding with next data source word B (t+1) outputs to coding schedule change-over circuit 101 and synchronous code-type insertion circuit 104.In the modulation circuit as shown in the figure, coupled circuit 105, dk limiter 106, DSV controller 107 and NRZI converter 108 sequentially are connected the outgoing side of coding schedule change-over circuit 101 and synchronous code-type insertion circuit 104, export the sequence that is used to write down from NRZI converter 108.
Synchronous code-type inserts circuit 104 and stores synchronous code-type, and the status information S (t) that keeps according to status register 103, and the cycle is according to the rules inserted the channels bits sequence to modulate with synchronous code-type, exports NextState information S (t+1) simultaneously.As described above, from the status information of coding schedule change-over circuit 101 outputs and the status information of synchronous code-type insertion circuit 104 outputs, offer status register 103 via multiplexer 109.Status register 103 is brought in constant renewal in and is kept next status information S (t+1), and from coding schedule change-over circuit 101 delivery channel code words, perhaps each Secondary Synchronization Code type inserts circuit 104 output synchronous code-type services at every turn.
The synchronous code-type that coupled circuit 105 will insert circuit 104 outputs from the channel code word and the Secondary Synchronization Code type of coding schedule change-over circuit 101 outputs is coupled and exports.When the channel code word is connected to each other, unite definite concatenate rule by go ahead of the rest according to use channel code word and subsequent channel code word, in coupled circuit, 4 continuous channel code words are connected with code word before the displacement shown in the table 2 and compare, the channel code word that satisfies concatenate rule is replaced, export as the serial data of expression channels bits sequence then.
The channels bits sequence that forms behind coupled circuit 105 enters dk limiter 106 subsequently.Dk limiter 106 is according to the value that determines the dk control bit before the dk control bit with information following closely, and concrete dk control law is as follows:
Step 1: if dk control bit ' * ' code word afterwards starts with ' 1 ', then order position ' * ' is ' 0 ', otherwise enters step 2;
Step 2: can make in the channels bits sequence that the number of position ' 0 ' is greater than k continuously if dk control bit ' * ' is made as ' 0 ', wherein k is the integer more than or equal to 9, make then that dk control bit ' * ' is ' 1 ', dk control bit ' * ' is a DSV control bit ' # ' otherwise make.
Except comprising position ' 0 ' and ' 1 ', also comprise DSV control bit ' # ' in the channels bits sequence of process dk limiter 106.But DSV control bit value ' 0 ' or ' 1 ', its final value is by 107 decisions of the DSV controller among Fig. 1.Regardless of the final value of DSV control bit, can not destroy the distance of swimming constraint of d=1 and k, wherein k is the integer more than or equal to 9.In addition, value by k in the rule shown in change dk limiter 106 steps 2, can also obtain different k parameters RLL (1, k) sign indicating number, wherein k is more than or equal to 9 integer, because crossing conference, k make clock recovery become difficult, therefore in real system, get k=9,10,11 usually, 12, in this preferred embodiment, select k=10.
The sequence that comprises the DSV control bit for 106 outputs of dk limiter, the DC component that DSV controller 107 comes the control channel bit sequence by the value of selecting DSV control bit ' # ', it is according to the value of the previous DSV control bit of the DSV decision of the channels bits sequence that calculates.Here define channels bits sequence { x
iCorresponding NRZ sequence { y
iAnd DSV sequence { z
iBe:
y
i＝2[(y
i-1+x
i)mod2-1]， (1)
Y wherein
0=0, z
0=0.Can be by the value of selecting the DSV control bit so that sequence { x
iCorresponding DSV sequence { z
iValue satisfy:
N
1≤z
i≤N
2， (3)
N wherein
1(≤0) and N
2(〉=0) is two (limited) constants.DSV controller 107 comes the DSV sequence { z of control channel bit sequence correspondence by the value of selecting DSV control bit ' # '
iValue, and then the control channel bit sequence is at the component of low-frequency range.
For the channels bits sequence { x after the process dk limiter 106
i, suppose that its m position is an i DSV control bit, its n position is an i+1 DSV control bit, i.e. x
m=x
n=#.Because x
mBe DSV control bit ' # ' that its value can be ' 0 ' or ' 1 '.At x
mEvery kind of value, DSV controller 107 calculates the channels bits sequence respectively at next DSV control bit x
nDistance of swimming numeral and z before occurring
N-1, select to make z then
N-1The x of absolute value minimum
mValue is as DSV control bit x
mFinal value.Repeat above operation and in all sequence of symhols, no longer comprise the DC control code element.
When getting k=10, by using the modulation circuit of this structure, the minimum value that can easily obtain run length is 1, and maximal value is 10, run length 1 not occurring is sign indicating number type continuous more than 6 times, and the channels bits sequence of the very little suitable high density recording of low-frequency component.
In addition, above explanation is based on that the concatenate rule of the coding schedule of table 1 and table 2 carries out, and when using the table of corresponding relation between change data source word and the channel code word, also can obtain same effect.For example, in state 1 pairing subcode table, channel code word and NextState that data source word " A " is corresponding with data source word " F " exchange, and obtain new coding schedule.In addition, though distributed DSV control bit position in the table 1, be not limited to the example that the coding schedule of table 1 provides.For example, the coded word that will comprise 1 DSV control bit, be divided into these two kinds of the channel code words that the DSV control bit becomes the channel code word of " 0 " and becomes " 1 ", by will wherein a kind ofly synthesizing with other channel code word, perhaps that other channel code word is synthetic, can change DSV control bit position easily or have the channel code word of DSV control bit.The code word " 10000# " that for example will contain the DSV control bit is divided into two channel code words " 100000 " and " 100001 ", its NextState is " state 1 ", correspond respectively to data source word " 2 " and data source word " B ", simultaneously that NextState is identical and be the channel code word " 101000 " of " state 1 " and " 101001 " and merge and obtain new channel code word " 10100# ", and with it corresponding to data source word " 1 ".Owing to the frequency of occurrences of DSV control bit in the coding schedule that obtains by this operation is constant, can expect has the characteristic same with the coding schedule of use table 1.
Fig. 2 illustrates the process flow diagram of above-mentioned code modulating method.At first, coding is initialized as state 0 or state 1 with the status register 103 of modulation circuit at first, simultaneously y0 and z0 is initialized as 0.User data is pressed the Frame that some bytes (for example, 91 bytes) separately obtain arbitrarily, in the beginning of each Frame, inserts synchronous code-type according to the order of SY0, SY1, SY2, SY3, and the original state of synchronous code-type is chosen as state 1.Comprise the DSV control bit in the first synchronous code-type, and, therefore do not carry out the judgement of DSV control bit value here, but wait until that next DSV control bit begins when occurring in DSV control bit not appearance as yet before this.After this, data bit sequence is cut apart by per 4, obtained per 4 one group data source word, the current modulation circuit status information of utilizing coding schedule of the present invention and status register 103 to be stored, be transformed to 6 bit channel code words, insert next synchronous code-type up to needs; While is according to the status information of coding schedule update mode register 103 storages of table 1 expression.Coupled circuit 105 is replaced the back connection according to concatenate rule shown in the table 2 each other to the channel code word then, and exports dk limiter 106 to.It is position ' 0 ', position ' 1 ' or DSV control bit ' # ' according to dk control law assignment that dk limiter 106 passes through the dk control bit, obtain comprising the channels bits sequence of DSV control bit, guarantee no matter DSV control bit value is " 0 " or " 1 ", the number of the position " 0 " between the phase ortho position " 1 " in the channels bits sequence that finally obtains is 1 to be k at the most at least, wherein k is the integer more than or equal to 9, k=10 here.
Comprise code element ' 0 ', ' 1 ' and DSV control bit ' # ' through the channels bits sequence of dk limiter 106.This sequence enters DSV controller 107 shown in Figure 1, DSV controller 107 is from the DSV of the first beginning of the sequence sequence of calculation, and the i (i=1 in detecting sequence, 2,3...) behind the individual DSV control bit, begin to calculate the DSV of this DSV control bit under its different value condition, till i+1 DSV control bit occurring, selecting i DSV control bit according to DSV then is position " 0 " or position " 1 ", then begin to calculate the DSV of i+1 DSV control bit sequence under its different value condition afterwards, till i+2 DSV control bit occurring, and determine the value of i+1 DSV control bit, by that analogy according to result of calculation.
As above-mentioned, Yi Bian carry out coded modulation on one side periodically insert synchronous code-type.Usually, the value of DSV control bit is uncertain before next DSV control bit occurs, yet for last the DSV control bit in the channels bits sequence, the DSV of its value when calculating channels bits sequence end determines.If inserting the cycle of synchronous code-type is the cycle according to 100 bytes (or higher), then can reduce the influence of the efficient reduction that causes by the insertion synchronous code-type.In addition, in the coding schedule, the part of the DSV control bit that synchronous code-type is represented can be converted to the polarity of controlling recording data.By changing predetermined locational DSV control bit, can limit the sign indicating number type that is recorded on the dish.
Fig. 3 is illustrated in the frequency characteristic example of the signal after the NRZI conversion that obtains under the above-mentioned code modulation mode.Transverse axis represents to utilize the frequency after the channel clock frequency is done normalization, and the longitudinal axis is represented the pairing oscillator intensity of different frequency composition, and unit is dB.After using modulator approach of the present invention that scale-of-two user data is at random modulated, as shown in Figure 3, compare with the maximal value of the amplitude composition of channels bits sequence after the NRZI conversion, in the oscillator intensity of the low-frequency range below 1/10000 of channel clock frequency than maximal value more than the little 20dB.Because in the frequency band below 1/10000 of channel clock frequency, the servosignal that has the control optical head position, and compare more than the little 20dB with maximal value in the oscillator intensity of this low-frequency range through the channels bits sequence after the coded modulation of the present invention, therefore can effectively reduce its baneful influence, help guaranteeing servo-controlled precision the servo-drive system control signal.
Table 4 shows the assessment result form of the frequency of occurrences of various T in the channels bits sequence after code modulating method and device are changed according to an embodiment of the invention.As can be seen from the table, owing to there is not the sign indicating number type of 1T and 11T above (except the 13T that synchronous code-type comprised) in the channels bits sequence, therefore satisfy the distance of swimming constraint of d=1 and k=10 fully.In addition, as shown in table 4, the 3T frequency of occurrences (22.213%) is the highest, the frequency (21.949%) that 2T occurs secondly, these are different with the highest situation of the common 2T frequency of occurrences.Adopted the concatenate rule shown in the table 2 relevant in this frequency of occurrences distribution situation shown in the table 4 and the coded modulation, because the concatenate rule shown in the table 2 replaces with other situation with the continuous situation of a large amount of 2T, the frequency of occurrences that 2T therefore occurred is lower than the situation of the 3T frequency of occurrences.Because the frequency that 2T occurs decreases, therefore the error that adopts PRML to detect also can reduce, and helps improving the performance of system.
Table 4 is the assessment result forms that are used for illustrating the frequency of occurrences of the various T of channels bits sequence after data transfer device and device are changed according to an embodiment of the invention;
| Run length nT | Occurrence number | Occupancy volume | The frequency of occurrences | Occupy |
| 1 | 0 | 0 | 0.0％ | 0.0％ |
| 2 | 101901 | 203802 | 37.899％ | 21.949％ |
| 3 | 68751 | 206253 | 25.57％ | 22.213％ |
| 4 | 42576 | 170304 | 15.835％ | 18.342％ |
| 5 | 23026 | 115130 | 8.5639％ | 12.399％ |
| 6 | 15640 | 93840 | 5.8169％ | 10.107％ |
| 7 | 7590 | 53130 | 2.8229％ | 5.7221％ |
| 8 | 4409 | 35272 | 1.6398％ | 3.7988％ |
| 9 | 2196 | 19764 | 0.81675％ | 2.1286％ |
| 10 | 1261 | 12610 | 0.469％ | 1.3581％ |
| 11 | 690 | 7590 | 0.25663％ | 0.81744％ |
| 12 | 0 | 0 | 0.0％ | 0.0％ |
| 13 | 832 | 10816 | 0.30944％ | 1.1649％ |
| 14 | 0 | 0 | 0.0％ | 0.0％ |
| Amount to | 268872 | 928511 | 100.0％ | 100.0％ |
Form shown in the table 5 is the assessment result of the occurrence number of continuous 2T sign indicating number type in the channels bits sequence after code modulating method and device are changed according to an embodiment of the invention.Obviously see from table 5, when the concatenate rule shown in the execution list 2, the situation that 6 above 2T sign indicating number types occur continuously no longer occurs, 6 continuous frequencies that occur of 2T sign indicating number type are also very low simultaneously, have only 0.83611%.In addition, the probability of single 2T sign indicating number type and continuous two 2T sign indicating number types appearance is then suitable.The distribution situation of the continuous 2T sign indicating number type shown in the table 5 helps reducing the mistake that PRML detects.
Table 5 is the assessment result forms that are used for illustrating the multiplicity of the continuous 2T of channels bits sequence after data transfer device and device are changed according to an embodiment of the invention;
| 2T sign indicating number type multiplicity | Occurrence number | Occupancy volume | The frequency of occurrences | Occupy |
| 1 | 39161 | 39161 | 61.309％ | 38.43％ |
| 2 | 15480 | 30960 | 24.235％ | 30.382％ |
| 3 | 6066 | 18198 | 9.4967％ | 17.859％ |
| 4 | 2400 | 9600 | 3.7573％ | 9.4209％ |
| 5 | 626 | 3130 | 0.98004％ | 3.0716％ |
| 6 | 142 | 852 | 0.22231％ | 0.83611％ |
| 7 | 0 | 0 | 0.0％ | 0.0％ |
| 8 | 0 | 0 | 0.0％ | 0.0％ |
| Amount to | 63875 | 101901 | 100.0％ | 100.0％ |
Fig. 4 is the distribution results of the pairing DSV of channels bits sequence after code modulating method is changed with device according to an embodiment of the invention.From Fig. 4, obviously find out, very little by the dispersion of the DSV value behind the DSV controller, and concentrate on about 0, therefore the DC component of the channels bits sequence that obtains after the modulation is very low.
The demodulation method of the channels bits sequence that code modulating method according to the present invention and modulation circuit are obtained describes below.Fig. 5 illustrates the process flow diagram of demodulation method.At first, regenerated signal being detected, utilize demodulator circuit, extract synchronous code-type from the channels bits sequence that obtains, is basic point with the synchronous code-type of extracting out, determines the border of per 6 bit channel code words; Then, the boundary information of the channel code word that obtains according to expression, from the channels bits sequence, detect the sign indicating number type of being replaced according to concatenate rule, and cut apart rule according to the displacement that obtains by concatenate rule and realize the displacement of continuous channel code word is cut apart, unite definite in advance by channel code word and subsequent channel code word according to using for wherein said concatenate rule; And then, according to current code word to be decoded following closely 6 bit channel code words or the information of synchronous code-type, select to need use with the corresponding subsolution mileometer adjustment of coding schedule, at last according to current code word to be decoded and selected subsolution mileometer adjustment, the 4 bit data source words that obtain.
Wherein, table 6 shows a kind of concrete implementation that rule is cut apart in the displacement of using in the demodulation method of the present invention.Because when coded modulation, make the code word that occurs " 101010101010101 " in the channels bits sequence connect situation all according to concatenate rule, be replaced into by the code word connection that can not obtain, as in an embodiment " 101,010 101010 " being replaced into " 001,001 000010 " according to the coding rule in the coding schedule.Therefore in order to realize correct demodulation, will to use displacement to cut apart rule be that original code word connects to those code word linker substitutions that can not obtain according to the coding rule in the described coding schedule separating timing, as in an embodiment " 001,001 000010 " being replaced into original " 101010101010 " again.Table 6 has stipulated that the displacement that the code word that may occur in all channels bits sequences, can not obtain according to the coding rule in the described coding schedule connects cuts apart rule.
Table 6 is that regular table is cut apart in the displacement of using in the expression demodulation method of the present invention;
Table 7 illustrates and is used for the demodulation table that 6 channel code word is converted to 4 bit data source words of the present invention.Demodulation table shown in the table 7 is divided into 2 sub-demodulation tables, respectively corresponding two states of demodulator circuit.In each subsolution mileometer adjustment, it is corresponding one by one with 21 channel code words all to exist 21 data source words of being represented by sexadecimal number 0～F.Separate timing, demodulating equipment shown in Figure 6 can select corresponding subsolution mileometer adjustment to be used for the demodulation of current code word X (t) according to the code word X following closely (t+1) of current code word X (t) or the information of synchronous code-type.If current channel code word X (t) channel code word X (t+1) afterwards is with ' 1 ' or ' 0000 ' beginning, perhaps, when next synchronous code-type was the SY0～SY3 of state 0,1 couple of current code word X of chooser demodulation table (t) carried out demodulation; If current code word X (t) code word X (t+1) afterwards is with ' 01 ', ' 001 ' or ' 0001 ' beginning, perhaps, when next synchronous code-type was the SY0～SY3 of state 1,2 couples of current code word X of chooser demodulation table (t) carried out demodulation.In addition, the 6 bit code types that in demodulation table, do not occur and in demodulation table in the corresponding data source word hurdle with the sign indicating number type of " Z " expression, all be utilize code modulating method of the present invention the sign indicating number type that can not take place.When detecting these yards type, this yard type is transferred to handle as not separating, and export data source word arbitrarily during the information of same of output demodulation mistake.But owing to use PRML to detect during the judgement of regenerated signal, the sign indicating number type that is determined as not having the channels bits sequence of expression in the demodulation table almost can not got rid of at the PRML detection-phase.Therefore, can reduce judge with demodulation in error.In addition, demodulation table owing to be to make 6 the channel code word form corresponding with 4 data source word, opened the map table of variable length block code in the flat 11-346154 communique and is compared with the spy, has the advantage of the propagation that is difficult for making a mistake.
Table 7 is the demodulation tables that use in the expression demodulation method of the present invention
The structure of demodulating equipment of the present invention (being demodulator circuit) is described below in conjunction with Fig. 6.This demodulator circuit can utilize complex programmable logic device (CPLD), and realizations such as field-programmables array FPGA or special chip belong to the known technology in the Design of Digital Circuit field.At first, the channels bits sequence is imported into synchronous code-type testing circuit 601.Synchronous code-type testing circuit 601 detects the synchronous code-type of insertion from the channels bits sequence, and with the position of detected synchronous code-type as basic point, the information of expression channel code word boundary position is appended to channels bits sequence and output.Before the channels bits sequence is cut apart by per 6 bit channel code words, cutting apart permutation circuit 602 detects according to the channel code word concatenate rule of the consecutive hours sign indicating number type of being replaced each other, cut apart rule according to the described displacement shown in the table 6 and be replaced into the preceding sign indicating number type of connection, and be divided into the output of 6 bit channel code words; Then, current channel code word X (t) is admitted to demodulation table change-over circuit 604 and waits demodulation, meanwhile code word X following closely (t+1) or synchronous code-type then are admitted to the subsolution mileometer adjustment and select circuit 603, be used for selecting to current code word X (t) decoding the subsolution mileometer adjustment that should adopt; Afterwards, the subsolution mileometer adjustment selects circuit 603 according to the 6 follow-up bit channel code words or the information of synchronous code-type, will select to be used for the subsolution mileometer adjustment of current 6 bit channel codeword decodings according to aforementioned rule, and selection result is sent into demodulation table change-over circuit 604; Demodulation table change-over circuit 604 stores demodulation table, and the subsolution mileometer adjustment according to selecting converts current 6 bit channel code word X (t) to 4 bit data source word B (t), and as the output of demodulation table change-over circuit 604.In addition, do not have the sign indicating number type of appearance in the described demodulation table of demodulation table change-over circuit 604 for table 7 expression, output can not demodulated information.In decode procedure, be that unit handles with 6 channel code words, and, owing to only can realize demodulation, can realize that demodulating error is difficult for the circuit structure of propagating with reference to current code word X (t) and following closely a code word X (t+1) or synchronous code-type.
In addition, the present invention is not limited to the various embodiments described above, in the scope of spirit of the present invention and claim, can suit to change to each embodiment.For example, code modulating method of the present invention and device, demodulation method and device are not only applicable to the reading and writing in the optical recording media, go for other recording medium yet.
Claims (8)
1. code modulating method, the data bit sequence that the 2n position is constituted is transformed to the channels bits sequence of 3n position, and n is an integer, it is characterized in that, and described modulator approach comprises the steps:
Utilize modulation circuit, the 2n bit data cut apart by per 4 obtain the data source word, according to coding schedule each data source word is converted to 6 bit channel code words, channel code word process that obtains and string conversion and order are exported, obtain the 3n bit data, wherein said coding schedule has two subcode tables that comprise 16 6 bit channel code words, 16 6 bit channel code words of one of them subcode table start with position " 1 " or " 0000 ", and 16 6 bit channel code words of another subcode table are with " 01 ", " 001 " or " 0001 " beginning, having the tail sign indicating number of a code word in addition in each subcode table at least is dk control bit or DSV control bit;
Channel code word and subsequent channel code word are united definite concatenate rule to modulation circuit in advance according to using, after the sign indicating number type that meets concatenate rule in the 3n bit data replaced, obtain new 3n bit data, wherein said concatenate rule comprises all makes the code word that occurs " 101010101010101 " in the channels bits sequence connect situation, and the code word after the displacement connects and connected and composed by the code word that can not obtain according to the coding rule in the described coding schedule;
By being position ' 0 ', position ' 1 ' or DSV control bit ' # ' according to dk control law assignment to the dk control bit in the new 3n bit data, obtain comprising the 3n bit data of DSV control bit, guarantee no matter DSV control bit value is " 0 " or " 1 ", the number of the position " 0 " between the phase ortho position " 1 " in the channels bits sequence that finally obtains is 1 to be k at the most at least, and wherein k is the integer more than or equal to 9; Wherein, the obtaining value method of the dk control bit in the channels bits sequence is as follows: according to one value after the described dk control bit, and in the channels bits sequence before described dk control bit and the number that follows the continuous position " 0 " after the described dk control bit closely determine it is position " 0 ", " 1 " or DSV control bit;
Afterwards, be position " 0 " or position " 1 " by select the DSV control bit according to DSV, obtain finally definite 3n bit channel bit sequence, and it is carried out the NRZI conversion.
2. code modulating method according to claim 1 is characterized in that:
Respectively corresponding two states of two sub-code tables of described coding schedule, include 4 bit data source words and 6 bit channel code words, and expression should reference when the next data source word of conversion the status information of subcode table, this status information is used to specify next data source word when changing used subcode table; Described 4 bit data source words are corresponding with NextState information, and use 16 systems to represent;
Data bit sequence is cut apart by per 4, obtained per 4 one group data source word, utilize described coding schedule and current modulation circuit status information, be transformed to 6 bit channel code words.
3. code modulating method according to claim 1 and 2, it is characterized in that: utilize in the process of described modulation circuit to the conversion of 2n bit data, to comprise run length be that the above synchronous code-type of k inserts in the channels bits sequence cycle according to the rules, and wherein k is the integer more than or equal to 9.
4. code modulating method according to claim 3, it is characterized in that: described synchronous code-type has identical condition code type, and adhere to two states separately, after assurance is inserted synchronous code-type in the channels bits sequence, minimum run length is that 1 constraint is not destroyed, and do not occur continuous more than 6 times run length be 1 sign indicating number type.
5. a coded modulation device of realizing the described code modulating method of claim 1 is characterized in that, described coded modulation device comprises:
The memory encoding table, and by described coding schedule of reference and status information, the data source word is converted to the coding schedule change-over circuit of channel code word, the coding schedule of described coding schedule change-over circuit storage comprises: with the corresponding channel code word that constitutes by position " 0 ", position " 1 ", dk control bit or DSV control bit of 4 bit data source words, and the status information of subcode table that should reference during the next data source word of expression conversion;
When the channel code word is connected to each other, the channel code word that satisfies concatenate rule is replaced the coupled circuit that obtains the channels bits sequence; Described concatenate rule is to use that in advance channel code word and subsequent channel code word are united definite;
According to the dk limiter that determines the value of dk control bit before the dk control bit with information following closely; And
DSV controller according to the value of the previous DSV control bit of the DSV decision of the channels bits sequence that calculates.
6. coded modulation device according to claim 5, it is characterized in that, described coded modulation device comprises that also synchronous code-type inserts circuit, described synchronous code-type inserts circuitry stores synchronous code-type, it inserts the channels bits sequence to modulate according to the status information cycle according to the rules with synchronous code-type, the length of described synchronous code-type is fixed, and comprising run length is the above sign indicating number type of k, and comprises the DSV control bit that can be chosen as position " 0 " or position " 1 " according to DSV.
7. the method that the channels bits sequence is carried out demodulation is characterized in that, described demodulation method comprises the steps:
Utilizing demodulator circuit, extract synchronous code-type from the channels bits sequence that obtains, is basic point with the synchronous code-type of extracting out, determines the border of per 6 bit channel code words;
Boundary information according to the channel code word that obtains, from the channels bits sequence, detect the sign indicating number type of being replaced according to concatenate rule, and cut apart rule according to the displacement that obtains by described concatenate rule and realize the displacement of continuous channel code word is cut apart, wherein said concatenate rule is by channel code word and subsequent channel code word are united definite in advance;
According to current code word to be decoded following closely 6 bit channel code words or the information of synchronous code-type, select to need use with the corresponding subsolution mileometer adjustment of coding schedule;
According to current code word to be decoded and selected subsolution mileometer adjustment, obtain 4 bit data source words.
8. a demodulating equipment of realizing the described demodulation method of claim 7 is characterized in that, described demodulating equipment comprises:
From the channels bits sequence, detect the synchronous code-type testing circuit of the synchronous code-type of insertion;
Cut apart permutation circuit, the described permutation circuit of cutting apart is used for detecting according to the channel code word concatenate rule of the consecutive hours sign indicating number type of being replaced each other, cuts apart rule according to displacement and is replaced into sign indicating number type before connecting, and be divided into 6 bit channel code words;
According to the 6 follow-up bit channel code words or the information of synchronous code-type, circuit is selected in the subsolution mileometer adjustment that the subsolution mileometer adjustment that is used for current 6 bit channel codeword decodings is selected; And
Store the demodulation table change-over circuit of demodulation table, described demodulation table change-over circuit is converted to 4 bit data source words according to the subsolution mileometer adjustment of selecting with 6 bit channel code words.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2005101321301A CN100386812C (en) | 2005-12-16 | 2005-12-16 | Code modulation method and device, demodulation method and device |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2005101321301A CN100386812C (en) | 2005-12-16 | 2005-12-16 | Code modulation method and device, demodulation method and device |
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| CN1822181A CN1822181A (en) | 2006-08-23 |
| CN100386812C true CN100386812C (en) | 2008-05-07 |
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| CN104702552B (en) * | 2013-12-05 | 2018-08-14 | 上海华虹集成电路有限责任公司 | BPSK subcarrier correlation demodulation bit boundaries determine circuit and method |
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH11346154A (en) * | 1998-05-29 | 1999-12-14 | Sony Corp | Device and method for modulation, device and method for demodulation and providing medium |
| US20040183704A1 (en) * | 2002-12-27 | 2004-09-23 | Chosaku Noda | Data conversion apparatus and data conversion method |
| US20040207545A1 (en) * | 2002-12-18 | 2004-10-21 | Nec Corporation | Code modulating method and code modulating apparatus, demodulating method and demodulating apparatus, and information recording medium |
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH11346154A (en) * | 1998-05-29 | 1999-12-14 | Sony Corp | Device and method for modulation, device and method for demodulation and providing medium |
| US20040207545A1 (en) * | 2002-12-18 | 2004-10-21 | Nec Corporation | Code modulating method and code modulating apparatus, demodulating method and demodulating apparatus, and information recording medium |
| US20040183704A1 (en) * | 2002-12-27 | 2004-09-23 | Chosaku Noda | Data conversion apparatus and data conversion method |
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| CN1822181A (en) | 2006-08-23 |
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