CN100373812C - Calibrating apparatus and method for automatic gain control circuit of array receiver - Google Patents

Abstract

The present invention relates to a calibration device for an automatic gain control circuit of an array receiver and a method, which divides signals received by an aerial array into two paths after processed by a passage circuit, wherein one path of the signals reaches a gain calibration device through AGC circuits and a demodulation circuit; the gain calibration device uses calibration weight value sent from a calculation unit to calibrate each passage signal; the other path of the signals is sent to a received signal intensity detection device; signal field intensity signals output by the received signal intensity detection device are sent to the calculation unit through A/D conversion; the gain calibration weight value of each AGC circuit is calculated by the calculation unit and sent to the gain calibration device. The present invention can calibrate the inconsistency of gain of each passage in real time and does not affect the normal work of a system, and the inconsistency is caused by each AGC circuit in an array passage. The detection of signal power when AGC circuits of each passage are calibrated, the calculation of calibration weight value and the calibration of signals of each passage are realized by using a software, and the calibration accuracy is high. The method provided by the present invention can calibrate the consistency of gain of the whole receiving chain of the array.

Description

The calibrating installation and the method that are used for the array acceptor automatic gain control circuit

Technical field

The present invention relates to a kind of the realization array acceptor automatic gain is controlled the device and method that (AGC) circuit is calibrated.In particular for adaptive array antenna, smart antenna, phased array radar, the calibrating installation and the calibration steps of systems array receiver agc circuits such as phase array sonar.Array acceptor of the present invention comprises the agc circuit in two and plural wireless signal receiving circuit and each the passage receiving circuit.

Background technology

In order to improve the communication performance of communication system, the capacity of raising system, and in order to satisfy at a high speed, the requirement of mass data transmission, a lot of companies, also have some R﹠D institutions to smart antenna, the adaptive antenna technology is carried out application study, yet these technical research and application can claim to the amplitude-phase consistency of the receiving circuit (abbreviation array channel) of each passage of array acceptor mostly.Phased array radar in addition, systems such as phase array sonar also require the amplitude-phase consistency of array channel.

When array acceptor designed, simply a plurality of single channel receiving circuits being combined obviously was the requirement that can not satisfy array channel amplitude phase equalization.In order to enlarge the dynamic range of received signal, the method that adopts is to use agc circuit in receiving link usually, the strong and weak gain of regulating the signal that is received automatically of signal that the agc circuit in each receiver receives according to this receiver.Because the signal power difference that the device property that the agc circuit in each receiver uses is different and each receiver receives, additional gain is inconsistent to each agc circuit to signal so, and changes than very fast.Except agc circuit, owing to the device property difference that each passage receiving circuit uses, also can cause the gain disparity error of array channel, in case device is selected, this fractionated gain error is general only to be changed with environmental change.

The inconsistent gain that the agc circuit of each receiver causes for Array Signal Processing, be equivalent to array signal has been carried out undesirable amplitude weighting, can reduce the performance of Array Signal Processing algorithm, so the inconsistent real time calibration that needs of amplitude of the array channel gain that causes of agc circuit.We know that agc circuit can adjust gain automatically according to the watt level of received signal, the dynamic range of compressed signal, so receiver can receive the bigger wireless signal of dynamic range, and obtain reasonable demodulation effect.If the gain of our calibrating signal before the signal demodulation can be lost the treatment effect of agc circuit.

At smart antenna, adaptive antenna, the amplitude-phase characteristic disparity error of array channel is to need calibration in the systems such as phased array radar, but change with the signal variable power because the array channel that the agc circuit of each passage causes is inconsistent, it is inconsistent to use the array channel calibration algorithm can't calibrate the array channel that agc circuit causes, and the amplitude that agc circuit causes in the array channel is inconsistent may cause array channel calibration failure.Therefore the array channel amplitude that needs the calibration agc circuit to cause is inconsistent.

Summary of the invention

Technical problem to be solved by this invention is: a kind of calibrating installation and method that is used for the array acceptor agc circuit is provided, can be used for smart antenna, adaptive antenna, phased array radar, the inconsistent calibration of the caused array channel gain of systems array receiver agc circuits such as phase array sonar, thus the consistency of array channel is met the demands.

The present invention is achieved in that

The calibrating installation of array acceptor automatic gain control circuit comprises: gain correction device 10, received signal intensity detecting device 20, computing unit 30.Also comprise corresponding channel circuit, agc circuit, demodulator circuit.

The signal that receives from aerial array is through the amplification of channel circuit, and filtering is divided into two paths of signals after the Frequency mixing processing.Wherein one road signal is admitted to agc circuit, send into gain correction device 10 after the demodulation of process demodulator circuit again through the signal after the processing of agc circuit automatic gain, the calibration weights that gain correction device 10 uses computing unit 30 to send are calibrated each channel signal.Other one road signal is admitted to received signal intensity detecting device 20, and its signal strength received signals intensity detecting device 20 detects; Send into computing unit 30 after received signals intensity detecting device 20 detected field intensity signals (RSSI) the process A/D conversion; Calculate each agc circuit gain calibration weights at computing unit 30, and these weights are sent into gain correction device 10.

Adopt the method for automatic gain control circuit calibrating installation of described array acceptor as follows:

1 signal power detects

Signal power detects and comprises following several steps:

(1) measures the variation relation of received signal field intensity indication (RSSI) with received signal power;

(2) according to the storage bit number of fixed-point data, the measurement result that re-quantization is above-mentioned, and be stored in the data storage, be used for the use of tabling look-up when signal power detects;

(3) the RSSI voltage of field intensity checkout gear 20 outputs to received signal carries out mould/number conversion;

(4) determine the signal power that each passage receives in the array by tabling look-up.

The calculating of 2 calibration weights

The calculating of automatic gain control circuit calibration weights comprises following several steps:

(1) from the signal power value of each definite passage of (4) step that signal power detects, chooses maximum performance number as reference power.Correspondingly determine reference calibrations weights according to the storage bit number of calibration weights and the gain-adjusted scope of agc circuit;

(2) calculate the poor of signal power that reference power and each passage receive;

(3) calculate the calibration weights of the automatic gain control circuit of each passage according to above-mentioned difference power.Computing formula is:

20×log ₁₀(W _ref)-20×log ₁₀(W _n)＝P _ref-P _n n＝1，2，…

W _n＝W _n/G _nn＝1，2，…

Determining of 3 cut position positions

When gain correction device 10 adopts fixed point device or logical device to realize, need carry out dynamic unified cut position to the signal behind each calibrate handles, purpose is to guarantee that the power proportions characteristic of each channel signal behind the cut position is constant, and guarantees that distorted signals that cut position causes within the range of permission.Definite step of cut position position is as follows:

(1) according to the maximum signal power P that allows to receive _MAX, and the figure place of the A/D figure place of signal and formed filter coefficient determines that an initial cut position position and data keep figure place, each passage is all identical;

(2) calculate maximum signal power P then _MAXThe difference of the signal power that receives with each passage;

(3) calculate the figure place that initial cut position position moves right, computing formula is: RMOV _n=mod ((P _Max-P _n), 6) n=1,2 ..., initial cut position position is exactly the cut position position of actual use after moving right according to result of calculation, and data reservation figure place remains unchanged in the cut position position moves to right process.

4 calibrations are carried out

Gain correction device 10 receives calibration weights and the cut position position that computing unit 30 is sent, and carries out channel signal calibration and data cutout function.The specific implementation step is as follows:

(1) design interface module receives calibration weights and cut position positional information that computing unit 30 is sent, the amplitude G of the signal of each passage _nN=1,2 ... send to computing unit 30;

(2) design time-delay buffer module, purpose is to make the calibration weights, cut position information and each channel signal are synchronous;

(3) at first calculate the amplitude G of the signal of each passage _nN=1,2 ..., and preserve, then each channel signal is calibrated;

(4) signal after the calibration is carried out cut position and handle, the signal after calibrating from gain correction device 10 outputs at last.

The present invention adopts the gain of calibrating signal after the signal demodulation, calibrating installation and the method that is used for the automatic gain control circuit of array acceptor of the present invention, can carry out real time calibration to each channel gain that each agc circuit in the array channel causes is inconsistent, and not influence system's operate as normal.Signal power during each passage agc circuit calibration detects, and calibrating the calculating of weights and each channel signal is calibrated all is to realize with software, and calibration accuracy is very high.Calibration accuracy is as described in the example of the present invention, adopting 8 bit correction weights and input harvester output voltage under the situation of 8 quantifications, the inconsistency of channel gain can be reduced to ± 0.5db in, and the inconsistent adjusting dynamic range that is decided by each agc circuit of each channel gain of array that does not adopt calibrating mode of the present invention, and become when being.If the quantization digit of the A/D of raising input harvester output voltage and the figure place of calibration weights can further improve calibration accuracy.Method provided by the invention can be calibrated the gain consistency of the whole reception link of array.

Description of drawings

Fig. 1 is the structural representation of the automatic gain control circuit calibrating installation of array acceptor;

Fig. 2 is the realization schematic diagram of array channel gain correction device;

Fig. 3 is the realization schematic diagram of received signal intensity detecting device;

Fig. 4 is the realization schematic diagram of computing unit;

Fig. 5 is the automatic measurement schematic diagram of RSS I with the received signal power variation relation.

Embodiment

Describe the specific embodiment of the present invention in detail below in conjunction with accompanying drawing:

One, signal power detects

At first as shown in Figure 3, design received signal intensity detecting device 20, and received signal intensity detecting device 20 and each passage are installed together.Received signal intensity detecting device 20 comprises several like this parts: power splitter, signal demodulator, amplifier, rssi measurement interface 21.Each functions of components is: an effect of power splitter is channel signal to be told be used for the signal that field intensity detects, and signal demodulator is that the signal after merit is divided carries out the field intensity detection; Amplifier is used for the output signal of amplification detector; Rssi measurement interface 21 provides the interface of a measure R SSI voltage, but the output voltage of measuring amplifier.

As shown in Figure 5, provide the automatic measurement method of RSSI with the received signal power variation relation.At first produce the signal of known power with computer 43 control signal sources 44, by control switch 45 this signal from the base station 40 antenna opening, 46 input 1# passages, can adjust the power output of signal source length by length according to incremental manner (or the mode of successively decreasing) then, and note down each signal power value.Signal power of computer 43 every adjustings, control switch 41 is just the signal input power meter 42 of rssi measurement interface 21 outputs of 1# passage, power meter 42 is measured received signal field intensity indication (RSSI) output voltage of this passage, the measurement result of computer 43 readout power meters 42 is so just made the form of the RSSI output voltage of 1# passage with the received signal power variation then; In like manner can make the form of the RSSI output voltage of n# passage with the received signal power variation.After we finish the form of all passage correspondences, according to the reference voltage of A/D chip and the quantization digit of A/D chip, measurement result to the RSSI of each passage is carried out quantification treatment, and the form stores after quantizing in the ROM of computing unit 30, the use of tabling look-up after being provided with.

When automatic gain control calibration, A/D chip in the computing unit 30 carries out mould/transformation of variables to the RSSI output voltage of each passage, CPU reads the digital quantity behind the RSSI voltage A/D of each passage successively, and preserves the data of a time period in memory, calculates the mean value of the RSSI voltage in this time period then, and table look-up according to this mean value and to determine the signal power that each passage receives in the array, use P1, P2 ..., Pn represents, the dBm of unit.

Two, the calculating of calibration weights

At first the designing and calculating unit 30, and as shown in Figure 4, this device comprises such several sections: A/D conversion, and CPU is (as single-chip microcomputer, DSP or other microprocessors), data storage, program storage, logical device, the software download debugging interface, communication interface, FPGA download interface.And computing unit 30, received signal intensity detecting device 20 and channel gain calibrating installation 10 link.The function of computing unit 30 is to calculate the automatic gain calibration weights and calculate the cut position position.

The function of computing unit 30 each building block: A/D conversion is converted to digital quantity to the RSSI voltage analog; CPU carries out the calculating of calibration weights and cut position position, and table lookup function; Data storage is preserved data such as RSSI data and calibration weights; Program storage is preserved executable program and data form; Logical device is carried out the logic control of CPU and external devices; The software download debugging interface provides computer and computing unit to carry out the interface that information is transmitted, such as debugging AGC calibration software, functions such as download of AGC calibration software and communication.

Calculate reference power P then _RefWith reference calibrations weights W _RefReference power P _RefComputational methods are P _Ref=max{P ₁P ₂P _n.Reference calibrations weights W _RefChoosing method be such, if we use is fixed-point processor, the calibration weights are with 8 no symbolic representations, because reference power is a maximum in each channel receiving signal power, so reference calibrations weights W _RefCan equal 255.In fact the reference calibrations weights chooses as long as satisfy

20×log ₁₀(W _max)-20×log ₁₀(W _min)＝P _max-P _min

W _max＝W _ref＝max{W ₁W ₂…W _n}

W _min＝min{W ₁W ₂…W _n}

P _max＝P _ref＝max{P ₁P ₂…P _n}

P _Min=min{P ₁P ₂P _nRequirement just passable, be not to equal 255, just enumerated an example here.When calibrating weights with 8 no symbolic representations, the dynamic range of signals that can satisfy is 48dB, if dynamic range of signals (P _Max-P _Min) 48dB, we will suitably improve the figure place of calibration weights so, if dynamic range of signals (P _Max-P _Min)＜48dB, we will suitably reduce the figure place of calibration weights so.

Calculate the automatic gain calibration weights W of each passage at last according to following these expression formulas ₁, W ₂..., W _n

20×log ₁₀(W _ref)-20×log ₁₀(W ₁)＝P _ref-P ₁

20×log ₁₀(W _ref)-20×log ₁₀(W ₂)＝P _ref-P ₂

20×log ₁₀(W _ref)-20×log ₁₀(W _n)＝P _ref-P _n

If the CPU in the computing unit 30 selects fixed-point processor for use, the calibration weights that calculate each passage with top formula are comparison difficulties so, therefore can adopt the method for tabling look-up to determine the calibration weights of each passage, this method ratio is easier to realize, is an instantiation determining the calibration weights of each passage with look-up table below.

At first design a calibration weights form, satisfy such requirement between the adjacent calibration weights:

20×log ₁₀(Wm)-20×log ₁₀(W _m-1)＝0.5dB (m>1)

If reference calibrations weights W _RefEqual 255, so according to expression formula

20×log ₁₀(W _ref)-20×log ₁₀(W _m)＝m×0.5dB (m≥0)

Can calculate the form of calibration weights, referring to table 1.This form is applicable to calibration weights W _RefEqual 255, gain between the adjacent calibration weights differs and equals 0.5dB, and the maximal regulated gain is the special case of 20dB, and the technician can be according to step provided by the invention and method, set up a form that is applicable to the another one special case, but do not break away from essence of the present invention.

The form of table 1 calibration weights referring to

m	Gain inequality	Weights W m	m	Gain inequality	Weights W m	m	Gain inequality	Weights W m	m	Gain inequality	Weights W m
												0	0	255	11	5.5	135	22	11	72	33	16.5	38
1	0.5	241	12	6	128	23	11.5	68	34	17	36
												2	1.0	227	13	6.5	121	24	12	64	35	17.5	34
3	1.5	215	14	7	114	25	12.5	60	36	18	32
												4	2.0	203	15	7.5	108	26	13	57	37	18.5	30
5	2.5	191	16	8	102	27	13.5	54	38	19	29
												6	3.0	181	17	8.5	96	28	14	51	39	19.5	27
7	3.5	170	18	9	90	29	14.5	48	40	20	25
												8	4.0	161	19	9.5	85	30	15	45
9	4.5	152	20	10	81	31	15.5	43

10

5

143

21

10.5

76

32

16

40

Calculate the poor of each passage received power and reference power: ERR then ₁=P _Ref-P ₁, ERR ₂=P _Ref-P ₂..., ERR _n=P _Ref-P _n, ERR _nGain inequality in the correspondence table 1 is tabled look-up, and can obtain the automatic gain calibration weights of each passage like this.

The calibration weights that calculate above only are that the gain of agc circuit is calibrated, in order to calibrate the whole consistency of accepting the gain of link of array, so above-mentioned calibration weights also carry out following processing: the range value G of each channel signal of calculating of fetch channel gain correction device 10 at first _nCalculate then: W _n=W _n/ G _nN=1,2 ...

Three, the cut position position determines

Therefore channel gain calibrating installation 10 general available fixed point microprocessors or realize with FPGA relate to each channel data cut position problem of calibration back.The calculating of cut position position is finished in computing unit 30.The cut position method is such, at first sets an initial cut position position and data reservation figure place in channel gain calibrating installation 10, and each passage is all identical.Initial cut position position and reservation figure place are to determine that according to the figure place of signal and the figure place of formed filter coefficient corresponding this initial cut position method is set a maximum power value P in software _MAX, can be set at more high-power that receiver can tolerate; Perhaps P _MAX=P _RefAccording to the result of calculation of following expression, the initial cut position position that moves right, the figure place that data keep is constant.

RMOV ₁＝mod((P _max-P ₁)，6)

RMOV ₂＝mod((P _max-P ₂)，6)

RMOV _n＝mod((P _max-P _n)，6)

Mod ((P in the formula _Max-P _n), 6) expression (P _Max-P _n) difference round again divided by 6 merchant.

At last the gain calibration weights of each passage that obtains with look-up table (or directly calculate) and the cut position position that moves to right is sent to channel gain calibrating installation 10 and calibrates, and each channel data after the calibration is carried out processing such as cut position.

Four, calibration is carried out

At first the designed channel gain correction device 10, can realize that this device is made up of several like this parts in the inner realization of FPGA or with microprocessor: interface module, channel gain calibration module, cut position module, time-delay buffer module.The function of each part: interface module is the data-interface of channel gain calibrating installation 10 and computing unit 30; The channel gain calibration module is carried out the calibrate weights and channel data multiplies each other; The cut position module is the data after the calibration to be carried out cut position handle; The effect of time-delay buffer module is the data of each passage of buffer memory in time period, makes calibration weights and cut position information and channel data synchronous.

The process that calibration is carried out:

(1) channel gain calibrating installation 10 receives the data of each channel formation filter output, and puts into buffer module;

(2) calculate the mean value of signal amplitude in each buffer module, and preserve, call for interface module.Supposed to store in the buffer module data of N sampling, the mean value of the signal amplitude of each passage is so: $G_n=\frac{1}{N}\underset{i=1}{\overset{N}{\mathrm{\Σ}}}\sqrt{I^2\left(i\right)+Q^2\left(i\right)}n=\mathrm{1,2}\·\·\·;$

(3) read the calibration weights and the cut position positional information of each passage, then calibration weights and corresponding channel signal are multiplied each other.

(4) according to the cut position positional information signal after calibrating is carried out cut position and handle, the signal after calibrating from gain correction device 10 outputs at last.

Claims (7)

1. a calibrating installation that is used for the array acceptor automatic gain control circuit comprises at least two channel circuits, at least two agc circuits, at least two demodulator circuits, and it is characterized in that: described device also comprises:

The received signal intensity detecting device, gain correction device, computing unit,

The signal that receives from aerial array through the amplification of channel circuit, filtering, Frequency mixing processing after, be divided into two paths of signals, one the tunnel is admitted to agc circuit, through the signal after the processing of agc circuit automatic gain, after passing through the demodulator circuit demodulation again, send into gain correction device, the calibration weights that gain correction device uses computing unit to send, each channel signal is calibrated

Other one the tunnel sends into the received signal intensity detecting device, and its signal strength received signals intensity detecting device detects; After the detected field intensity signal RSSI process of the received signals intensity detecting device A/D conversion, send into computing unit; Calculate each agc circuit gain calibration weights at computing unit, and these weights are sent into gain correction device.

2. be used for the calibrating installation of array acceptor automatic gain control circuit according to claim 1, it is characterized in that: described received signal intensity detecting device comprises:

At least two power splitters are divided into two-way with channel signal, and one the tunnel is used for field intensity detects, and one the tunnel is used for down-conversion, demodulation process;

At least two sound detectors, signal demodulator are that the signal after merit is divided carries out the field intensity detection;

At least two amplifiers, amplifier are used for the output signal of amplification detector;

At least two rssi measurement interfaces provide measure R SSI the interface of voltage, but the output voltage of measuring amplifier.

3. be used for the calibrating installation of array acceptor automatic gain control circuit according to claim 1, it is characterized in that: described gain correction device can realize that described gain correction device comprises by FPGA or microprocessor:

An interface module is used for the data-interface of channel gain calibrating installation and computing unit;

At least two channel gain calibration modules are used to carry out calibrate weights and channel data and multiply each other;

At least two cut position modules, the cut position position that is used for each channel data of calculating according to described computing unit data after to calibration are carried out cut position and are handled;

At least two time-delay buffer modules are used for the data of each passage of buffer memory in time period, make the cut position position and the channel data of calibration weights and each channel data synchronous.

4. be used for the calibrating installation of array acceptor automatic gain control circuit according to claim 1, it is characterized in that: the described computing unit that is used to calculate the automatic gain calibration weights and calculate the cut position position of each channel data comprises:

At least two A/D converters are used for the RSSI voltage analog is converted to digital quantity;

A CPU adopts single-chip microcomputer or DSP or fixed point microprocessor, is used to carry out the calculating of the cut position position of calibrating weights and each channel data, and the data form of looking into the reference calibrations weights;

A data memory is used to preserve RSSI data and calibration weights data;

A program storage is used to preserve executable program and described data form;

A logical device is used to carry out the logic control of CPU and external devices;

Software download debugging interface comprises software download debugging and communication interface, FPGA download interface, provides computer and computing unit to carry out the interface that information is transmitted, and is used to debug the AGC calibration software, and the AGC calibration software is downloaded and communication.

5. a calibration steps that is used for the array acceptor automatic gain control circuit comprises the steps:

One, signal power detects, and further comprises the steps:

(1) measures the variation relation of received signal field intensity indication RSSI with received signal power;

(2) according to the storage bit number of fixed-point data, the measurement result that re-quantization is above-mentioned, and be stored in the data storage, be used for looking into when signal power detects output voltage and use with the form that received signal power changes;

(3) the RSSI voltage of field intensity checkout gear output to received signal carries out mould/number conversion;

(4) determine the signal power that each passage receives in the array by looking into output voltage with the form that received signal power changes;

Two, the calculating of calibration weights further comprises the steps:

(1) chooses maximum performance number as reference power each channel signal performance number that the 4th step that detects from signal power is determined, correspondingly determine reference calibrations weights according to the storage bit number of calibration weights and the gain-adjusted scope of agc circuit;

(2) calculate the poor of signal power that reference power and each passage receive;

(3) calculate the calibration weights of the automatic gain control circuit of each passage according to above-mentioned difference power, computing formula is:

20×log ₁₀(W _ref)-20×log ₁₀(W _n)＝P _ref-P _n n＝1，2，…；

Wherein, calibration weights W _n, reference calibrations weights W _Ref, reference power P _Ref, the signal power Pn that passage receives;

When three, determining of cut position position, gain correction device adopt fixed point device or logical device to realize, need carry out dynamic unified cut position to the signal behind each calibrate and handle, further comprise the steps:

(1) according to the maximum signal power P that allows to receive _MAX, and the figure place of the A/D figure place of signal and formed filter coefficient determines that an initial cut position position and data keep figure place, each passage is all identical;

(2) calculate maximum signal power P then _MAXThe difference of the signal power that receives with each passage;

(3) calculate the figure place that initial cut position position moves right, computing formula is:

RMOV _n=mod ((P _Max-P _n), 6) n=1,2 ..., initial cut position position is exactly the cut position position of actual use after moving right according to result of calculation, and data reservation figure place remains unchanged in the cut position position moves to right process;

Four, calibration is carried out, and gain correction device receives calibration weights and the cut position position that computing unit is sent, and carries out channel signal calibration and data cutout, further comprises the steps:

(1) by interface module, the cut position positional information of determining in calibration weights that calculate in the step 2 that the reception computing unit is sent and the step 3;

(2) by the time-delay buffer module, make the calibration weights, cut position information and each channel signal are synchronous;

(3) at first calculate the range value G of each channel signal _nN=1,2 ..., then each channel signal is calibrated W _n=W _n/ G _nN=1,2,

(4) signal after the calibration is carried out cut position and handle, the signal after calibrating from gain correction device output at last.

6. as being used for the calibration steps of array acceptor automatic gain control circuit as described in the claim 5, it is characterized in that: (1) step during described signal power detects further comprises:

The signal source of at first computerizeing control produces the signal of known power, by control switch this signal is imported a paths from the antenna opening of base station;

Then according to incremental manner, or the mode of successively decreasing, adjust the power output of signal source, and write down each signal power value;

The signal input power meter that signal power of the every adjusting of computer, control switch are just exported the rssi measurement interface of this passage, power meter are measured the received signal field intensity indication RSSI output voltage of this passage;

The measurement result of computer readout power meter is so just made the form of the RSSI output voltage of this passage with the received signal power variation then;

Repeat the form of the RSSI output voltage of the above-mentioned n of a can be made into passage with the received signal power variation.

7. as being used for the calibration steps of array acceptor automatic gain control circuit as described in the claim 5, it is characterized in that: (2) step during described signal power detects further comprises:

After the form that the output voltage of all passage correspondences changes with received signal power is finished, according to the reference voltage of A/D chip and the quantization digit of A/D chip, measurement result to the RSSI of each passage is carried out quantification treatment, and the form stores after quantizing in the ROM of computing unit, the use of tabling look-up after being provided with.

Images