CN100372343C - Controlling device for digital pulse formed filter output gain - Google Patents
Controlling device for digital pulse formed filter output gain Download PDFInfo
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- CN100372343C CN100372343C CNB2004100704082A CN200410070408A CN100372343C CN 100372343 C CN100372343 C CN 100372343C CN B2004100704082 A CNB2004100704082 A CN B2004100704082A CN 200410070408 A CN200410070408 A CN 200410070408A CN 100372343 C CN100372343 C CN 100372343C
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Abstract
The present invention relates to a wireless communication system, particularly to a device for controlling the output gain of an RRC(root rise cosine) digital wave filter in a TD-SCDMA system (mobile communication system time division synchronous code division multiple-access). The gain control device of the present invention comprises an output gain device which selects an effective bit required by self-adaptive regulation. Automatic gain control is arranged on the basis of a wireless frame, the power or a time slot of the next frame is predicted by calculating the power or an amplitude of a time slot of the existing or the previous frame, and then, gain is set for the next frame. The present invention can effectively reduces a calculation scale and reduce storage space.
Description
Technical Field
The present invention relates to a wireless communication system, and more particularly, to a device for controlling the output gain of an RRC (root-rising-remaining-rotation) digital filter in a TD-SCDMA system (time division synchronous code division multiple access).
Background
With the development and popularization of wireless communication services, the number of mobile communication users has been increasing manyfold, and especially, the number of mobile users in china has been increasing at a rate of more than 150% for years. Users are also increasingly demanding on the speed and quality of communications.
In a wireless communication system, a fast fading wireless transmission channel is very serious to the signal degradation, and for a digital receiver, AGC (automatic gain control) can suppress fading and make a received baseband signal relatively stable, but in a digital receiver, especially in a second generation (2G) and a third generation (3G) mobile communication system, the variation of a received signal caused by adjacent channels, that is, signals of a plurality of adjacent carrier frequencies is also very serious: according to the standard requirement, the adjacent channel interference is about 40dB greater than that when the carrier frequency signal is worst. For TD-SCDMA, there is also a strong FDD out-of-band signal. Generally, for a zero-if rf receiver or a super-heterodyne rf receiver, which is widely used in 3G base station and handset reception, a baseband at the digital receiver end filters most of the adjacent channel interference through a pulse shaping matched filter RRC (root-rising residual filter).
However, the measurement of AGC in the prior art is before RRC. The main purpose of this arrangement is to ensure that the signal of the local carrier frequency does not overflow due to saturation, because the local carrier frequency and the adjacent frequency signal are not separated yet. The length of quantization bit has a large dynamic range allocated to adjacent carrier frequency channel, and the fixed point implementation design of the digital RRC filter is designed according to the amplitude of the sampling signal at this time, which needs to ensure that the accumulator does not overflow and saturate in the filtering process. Since the fixed-point operation does not take the filter characteristic into consideration, it is considered only from mathematical operations such as multiplication and addition. From the operation point of view, it is equivalent to the word length reservation of the all-pass filter.
Therefore, the gain control in the prior art has the defect of large chip area due to the need of using a large memory space to store the intermediate data and the operation result.
In addition, noise filtering is performed in addition to the adjacent channel interference, but since the noise is weak compared with the signal, the noise is not mainly considered in the analysis, but the effect of the noise can still be merged into the adjacent channel interference. In the following, the superposition of the interference signal and the noise of the adjacent channel is generally referred to as an interference signal.
Disclosure of Invention
The invention aims to improve the representation precision of fixed point data after an RRC filter to the carrier frequency and avoid the transmission of invalid bits. The performance of the receiver is improved, and the digital word length and the storage space of hardware implementation are reduced, so that the chip area is reduced.
In order to solve the above technical problem, the present invention provides an output gain control device for a digital pulse shaping filter: an output gain control device selects a valid bit required for adaptive adjustment, and calculates a shift value using a power estimation value before an RRC filter and a power estimation value after the RRC filter, the output gain control device including: RRC filter, RRC pre-signal power estimator, RSSI estimator, multiplication control RRC filter output device, wherein,
the pre-RRC signal power estimator is used for estimating the signal power before the RRC filter and receiving a signal from the analog-digital converter; after estimating the total power of the signals of the specific time slot of the frame, the pre-RRC signal power estimator outputs the signals to a multiplication control RRC filtering output device, and the multiplication control RRC filtering output device controls fixed-point numbers output by the RRC filtering;
an RSSI estimator for estimating the power of the received useful signal is arranged between the rear-end receiving digital processing device and the multiplication control RRC filtering output device;
the RSSI estimator outputs the estimated useful signal power of the specific time slot of the frame to the multiplication control RRC filtering output device, and the shift control RRC filtering output is carried out;
the multiplication control RRC filter outputter receives data transmitted from the RRC filter, and outputs a shift bit truncation to be controlled.
It can be seen from the above description that the output gain control device of the digital pulse shaping filter according to the present invention can improve the performance of the receiver and reduce the digital word length and the storage space implemented by hardware by avoiding the transmission of invalid bits, thereby reducing the chip area.
Drawings
FIG. 1 is a block diagram of a radio frequency front end and AGC and adaptive valid bit adjustment system of the present invention;
FIG. 2 is an exploded view of the gain control RRC filtered output;
FIG. 3 is a diagram of a TD-SCDMA sub-frame structure;
fig. 4 is a schematic diagram of an RRC filter;
fig. 5 is a simplified implementation block diagram of an exploded view of the shift control RRC filtering output.
Detailed Description
In order to reduce the chip area, the analysis is first performed from two points:
on the other hand, in a certain functional operation module, the following operations are provided
Where X is the data from the output of the RRC and Y is a variable of the functional block, for simplicity of description, a sign bit is represented by the fixed-point data of Q +1 bits if X ∈ [ -1, 1). As shown in table 1, is an output description of the RRC filter.
TABLE 1
| Sign bit | Invalid bit | Invalid bit | Significant bit | Significant bit | Significant bit | Significant bit | … |
| Sign bit | Invalid bit | Invalid bit | Invalid bit | Invalid bit | Significant bit | Significant bit | … |
The representation bit of Y of the mathematical representation of the fixed point operation without loss of precision is 2Q +1. Thus, if the fixed-point representation of X has 2 invalid bits after the sign bit (the invalid bit is "0" for positive numbers and "1" for negative numbers), the output of Y has 4 invalid bits, which results in waste of the fixed-point representation, and if there is further calculation for Y, the operation scale of hardware is enlarged in order to use the valid bit data of Y. For example, to use the 4-bit valid bits of Y, 8-bit data bits are used for the calculation.
But if the data of Y is a valid bit after the sign bit, only 4 bits are used for calculation. Thus, the effective bit is increased, and the operation scale can be reduced. The above example takes square as an example, but in the system design of the receiver, the operations of addition, multiplication, etc. are completely the same in terms of the reservation of the significant bits.
On the other hand, the output of many functional modules is used as the input of another functional module, and before the output, if buffer storage of data exists, the storage space can be greatly reduced. Still taking the example of the above model, if the result of our operation is to store 700 x 8 bit-specific bits, and if there are 4 bits invalid, our memory space is 700 x 12 bits, which enlarges the memory space. Resource waste is caused, and the cost is increased.
From the above analysis, to effectively reduce the operation scale and the storage space, the efficiency of fixed-point data representation needs to be improved, and the output of the RRC is the source of all subsequent calculations, so to achieve the purpose of the present invention, the effective bit of the output is mainly improved for the RRC.
The invention relates to self-adaptive effective bit regulation, which is composed of a gain multiplier (variable bit shift controller) and used for reselecting a required effective bit through calculation. As mentioned above, it is controlled by the strength of the adjacent channel and the interfering signal. If the interference signal is strong, it is practical for ADC (analog to digital conversion) to compress the useful signal to ensure that the useful signal plus the interference signal do not overflow during sampling and that the signal does not operate in the non-linear range of the radio frequency. For example, an interfering signal 12dB stronger than the desired signal will occupy the quantization space of up to 2 bits. After the RRC filter, most of the interference signals (out-of-band signals) are filtered out, so that the output can be raised by two significant bits. If there is no interference, the output data will remain unchanged.
Another consideration is that when the system with more strict delay requirement is applied, the calculation is based on prediction.
The device of the invention can be used for the base station and the terminal receiving in all wireless digital communication systems with pulse beam forming, in particular in third generation wireless communication systems. The application in the terminal can improve the receiving performance of the system and reduce the scale of the terminal demodulation chip.
One embodiment of the present invention is shown in fig. 1, and is implemented in an rf front end and AGC and adaptive active bit adjust system. The system comprises typical components of a wireless communication system, in particular a receiver system of 3G, such as a radio frequency end analog signal amplifier 1, an automatic gain controller 3, an analog-to-digital converter 2, a rear end receiving digital processing 8 and the like, and further comprises an output gain device consisting of an RRC front signal power estimator 4, an RRC filter 6, an RSSI estimator 5 and a multiplication control RRC filter outputter 7.
In fig. 1, an AGC (automatic gain controller) 3 can ensure that the preset conversion bits are utilized to the maximum extent possible when performing analog-to-digital conversion while controlling the proportion of overflow saturation to a small range. This control is performed by giving the amplifier gain value of the rf front-end. Taking TD-SCDMA terminals as an example, AGC is based on radio frames, predicts the power of the next frame or time slot by calculating the power (or amplitude) of a certain time slot of the current and previous frames, and then sets a gain for the next frame.
The invention is to ensure that the digital receiving demodulation unit after the RRC filter is included can use as few word lengths as possible to carry out multiplication, but the accumulated operation result can ensure the performance of a receiver. On the other hand, the invention can improve the operation precision of the receiver when the word length of the same bit is used, thereby improving the performance of the receiver.
Hereinafter, the apparatus of the embodiment of the present invention is described in detail.
As can be seen from the above description, the apparatus of the embodiment of the present invention is mainly designed to use the valid bit of the RRC output as much as possible. Since the signal after digital-to-analog conversion comprises an interfering signal, it is not possible to derive a shift value from the estimated RSSI (received desired signal strength).
The apparatus of the present embodiment calculates the amplitude gain value (shift value) by using mathematical calculation of the power estimation value before the RRC filter and the power estimation value after the RRC filter.
The apparatus and the use thereof are described in the following with the application in a TD-SCDMA terminal, which is one of the standards of the third generation mobile communication system.
Since the embodiment of the present invention is applied to TD-SCDMA based on frame, subframe and time slot, in order to more clearly describe the working principle of the apparatus of the present invention, the frame structure of TD-SCDMA is first briefly introduced, as shown in fig. 3, TD-SCDMA is a time unit with 5ms as a subframe. Each TD-SCDMA sub-frame is divided into 7 common time slots (TS 0-TS 6) and three special time slots.
The invention is primarily handled per time slot. Since the power of each slot in TD-SCDMA is different, the present invention is also directed to the same position slot in each subframe, as the agc is directed to the same position slot in each subframe.
The following describes various apparatuses and methods for implementing the apparatuses of the present invention with reference to fig. 1 and 2.
The radio frequency front end of the wireless receiver is firstly a radio frequency end analog signal amplifier 1, and the device controls the gain of a medium frequency signal (a superheterodyne receiver) or an analog baseband signal. The control can be single-stage amplification or multi-stage amplification. Represented in fig. 1 with a single level of enlargement. The amplified gain control value is output by the automatic gain controller.
The amplified signal is transmitted to an analog-to-digital converter (ADC) 2. The analog-to-digital converter 2 samples and quantizes the analog baseband signal into a digital signal for subsequent digital signal processing. There are several important characteristics for an analog-to-digital converter as follows: full amplitude voltage, conversion rate, quantization bit number.
The full-amplitude voltage has a corresponding full-amplitude signal power, and the corresponding relationship depends on the value range (non-random signal) or the random characteristic (random signal) of the signal input to the analog-to-digital converter. Generally, in wireless communication, signals passing through the rf front end are gaussian, but are by no means limited to gaussian. Let the full-amplitude power of the ADC be P ref 。
The conversion rate depends on the spectral characteristics of the input signal and the present invention does not relate to the conversion rate of the ADC.
Quantization bit number: this is the most important characteristic of the ADC, and the difference in the number of quantization bits determines the quantization accuracy of the signal after the ADC, quantization noise, and a dynamic range suitable for the input analog signal. In fig. 1, the signals passing through the rf-side analog signal amplifier include useful signals and interference, and these sum signals are converted into digital signals of M bits.
The receiving end of the wireless communication is also provided with an automatic gain controller 3 for controlling the gain of the analog signal amplification. The input of the automatic gain controller 3 is connected to the output of the analog-to-digital converter 2, and its output is connected to the analog signal amplifier. This is because the received amplitude/power of the received wireless signal is not only small but also time-varying. This requires that the received signal be amplified during processing, and that the amplification factor (gain) be kept as close as possible to the variation in received signal strength. When the signal changes to a small value, the amplification gain is increased accordingly, and when the signal changes to a large value, the amplification gain is decreased accordingly. The tracking process following the signal strength change is performed by an automatic gain controller. AGC is present not only in superheterodyne receivers but also in zero intermediate frequency receivers. The target criteria for it to amplify the signal are related to the full amplitude voltage and the full amplitude power of the analog-to-digital converter. Depending on the algorithm of the automatic gain control.
The adaptive valid bit adjusting apparatus and algorithm are described in detail below with reference to fig. 1 and 2.
As shown in the figure, the output gain device of the present invention includes: an RRC pre-signal power estimator 4, an RRC filter 6, an RSSI estimator 5 and a multiplication control RRC filtering output device 7.
The pre-RRC signal power estimator 4, which is used to estimate the signal power before the RRC filter, is arranged to receive the signal via the analog-to-digital converter 2:
the signals include the signals required by the user and interference signals. Let us convert from analog to digitalThe input signal from the device is r (N), N =1, 2. N is the total number of samples we estimate the signal power. In TD-SCDMA, N is P times the data length of each slot or Midamble's data, where P is a multiple of oversampling. The power estimate P of this signal r To (other power estimation methods may be used, e.g. smoothing filter estimation, but P r The estimation method of (2) does not affect the whole device of the patent of the invention):
the pre-RRC signal power estimator 4 outputs the signal to the multiplication control RRC filter outputter 7 after estimating the total power of the signal of the specific time slot of the frame, and the multiplication outputter 7 controls the fixed point number output by the RRC filter.
An RSSI estimator 5 for estimating the power of the received desired signal is arranged between the back-end reception digital processing means 8 and the multiplication control RRC filter outputter 7. The signal input here is the output of the RRC filter 6. The input signal of the device comprises a useful signal, an out-of-band signal remained after RRC filtering and noise, namely a residual interference signal.
Let the input signal from the RRC filter 6 be s (n), n =1, 2. L is the sum of the number of sample points that we estimate the useful signal. In TD-SCDMA, L is Q times the length of data or Midamble data per time slot, where Q is the RRC filtered signal rate divided by the chip rate. Then the power estimate P of this signal s To (other power estimation methods are also possible, e.g. smoothing filter estimation, but P s Does not affect the overall device of the invention)
The RSSI estimator 5 outputs the estimated useful signal power of the specific time slot of the frame to the multiplication control RRC filtering output device 7, and the shift control RRC filtering output.
The RRC filter 6 performs beamforming filtering for the wireless communication system. The frequency response of the filter is specified in 3G mobile communication systems, and the filter is realized in the form of a digital filter in system implementation. The bit cutting output of the last step is completed by a multiplication control RRC filtering output device 7.
A fixed point implementation of some RRC filter is described below, as shown in fig. 4.
It can be seen from the derivation of the RRC filter that since the fixed point operations do not take into account the filtering characteristics, the mathematical operations themselves are simply added from the multiplication of the mathematics. From the operation point of view, it is equivalent to the word length reservation of the all-pass filter.
The multiplication control RRC filter outputter 7 receives data transmitted from the RRC filter 6, and outputs a shift bit truncation to be controlled therein. The algorithm principle decomposition is shown in fig. 2.
The multiplication control RRC filtering output unit 7 includes a user signal power ratio calculator 701, an accumulation averager 702, a control coefficient generator 703, a delay Z frame 705, and a multiplication output unit 704.
The user signal power ratio calculator 701 receives the estimated value P output from the RSSI estimating device 5 s And a pre-filter power estimate P output by the pre-RRC signal power estimator 4 r And completing the calculation of the power ratio of the user signal in the received signal to the total received signal. The device completes the following operations:
B P ＝P s /P r (3)
in the formula, B P Representing the ratio of user power to total power that we need to compute. Wherein P is r ，P s As shown in equations (1) and (2). Thus 1-B P Approximately equal to the ratio of out-of-band interference power to total power. We will calculate the bit-truncation displacement value from this estimate of the interference power.
A cumulative averager 702 is disposed after the user signal power ratio calculator 701 for averagely calculating B of the user signal power ratio calculator 701 for the same slot in each frame P Is averaged over several consecutive frames. The calculation can be performed by means of a moving average or a kalman filter. Its function is to try to filter out the effects of noise and fast fading. Illustrative examples
In the formula
Indicating the average result value of the nth frame. L represents the average length of the sliding average, but L =1 may be adopted. At this time
The control coefficient generator 703 is arranged after the accumulation averager 702 to calculate a multiplication coefficient for the magnitude of the RRC output, which is smaller than 1. The relationship between the amplitude of the signal and the power of the signal is mainly related to the distribution of the signal, and in order to ensure that the received signal is not damaged, the power of the signal is the square of the amplitude (two-point zero-mean distribution)
In the formula (I), the compound is shown in the specification,
is the amplitude gain factor that we need to compute. In digital implementation, in particular in fixed-point operations implemented by hardware, fetching
In the above formula
Represents taking less thanIs the maximum power of 2 (k is more than or equal to 0 and less than or equal to 1 og) 2 (accumulator length), k is an integer). Therefore, the fixed point decimal shifting method can be directly carried out during actual implementation to achieve the multiplication effect.
And a multiplication outputter 704 for performing a function of multiplying and outputting the RRC-filtered signal. The multiplication coefficient is
If approximated by
The multiplication operation can be replaced by a shift operation, which greatly simplifies the implementation complexity of the device.
The apparatus shown in fig. 2 can also be simplified to the simplified apparatus shown in fig. 5 by integrating the user signal power ratio calculator 701, the accumulation averager 702, the control coefficient generator 703 and the multiplication output unit 704. The digital simplification process and the shift process of the shift output are shown in table 2. During the shifting process, the sign bit of the number is always kept unchanged, and the specific integer and decimal representation thereof is controlled by controlling the shift generator 703. The shift control generated by the control shift generator 703 removes invalid bits, improving the fixed-point representation accuracy of the numbers.
TABLE 2
| Sign |
0 | 0 | Significant bit | Significant bit | Significant bit | Significant bit | … |
↓ controlling shift
| Sign bit | Significant bit | Significant bit | Significant bit | Significant bit | Significant bit | Significant bit | … |
In addition, in some situations where the real-time processing requirement is relatively strict, the generation of the control bit for the current frame and then controlling the shift output of the current frame will not satisfy the time requirement of the system, so the control bit generated by the current frame will be used for the shift output of the next frame as long as the generated conditions and values are correlated and predictable. In fact, in many systems, this condition is true. For the same position time slot of different sub-frames of TD-SCDMA, the ratio of in-band power to out-of-band power is almost the same, so it can be used for delay control, setting the delay Z frame 705. Of course, for a system where real-time processing is not a strict requirement, the delay Z may be 0, i.e. the shift value generated by the present frame controls the present frame.
The rear-end reception digital processing device 8 completes reception of data, which is not a problem to be solved by the present invention, and thus, a detailed description thereof will be omitted.
Claims (7)
1. An output gain control device for a digital pulse shaping filter, comprising: an output gain control device for selecting a valid bit required for adaptive adjustment and calculating a shift value using a power estimation value before an RRC filter and a power estimation value after the RRC filter, the output gain control device comprising: an RRC filter, a pre-RRC signal power estimator, an RSSI estimator, a multiplication control RRC filter output device, wherein,
the pre-RRC signal power estimator is used for estimating the signal power before the RRC filter and receiving a signal from the analog-digital converter; after estimating the total power of the signals of the specific time slot of the frame, the pre-RRC signal power estimator outputs the signals to a multiplication control RRC filtering output device, and the multiplication control RRC filtering output device controls fixed-point numbers output by the RRC filtering;
an RSSI estimator for estimating the power of the received useful signal is arranged between the rear-end receiving digital processing device and the multiplication control RRC filtering output device;
the RSSI estimator outputs the estimated useful signal power of the specific time slot of the frame to the multiplication control RRC filtering output device, and the shift control RRC filtering output is carried out;
the multiplication control RRC filter outputter receives data transmitted from the RRC filter, and outputs a shift bit truncation to be controlled.
2. The digital pulse shaping filter output gain control of claim 1, wherein: the output gain control means is provided in a system comprising: the radio frequency end analog signal amplifier controls the gain of the intermediate frequency signal or the analog baseband signal;
the analog-to-digital converter is used for transmitting the amplified signal to the analog-to-digital converter;
the automatic gain controller controls the gain of the analog signal amplification, the input end of the automatic gain controller is connected with the output end of the analog-to-digital converter, and the output end of the automatic gain controller is connected to the analog signal amplifier;
the back end receives the digital processing device.
3. The digital pulse shaping filter output gain control of claim 2, wherein: the automatic gain controller is based on the radio frame, and predicts the power or time slot of the next frame by calculating the power or amplitude of a certain time slot of the current and previous frames and then sets a gain for the next frame.
4. The digital pulse shaping filter output gain control of claim 1, wherein: the multiplication control RRC filtering output device comprises: user signal power ratio calculator, accumulation averager, control coefficient generator, multiplication output device;
a user signal power ratio calculator receives an estimated value output by an RSSI estimated machine and a pre-filtering power estimated value output by an RRC pre-signal power estimated machine;
the accumulation averager is arranged after the user signal power ratio calculator and is used for averagely calculating the average value of the user signal power ratio calculation for continuous frames of the same time slot in each frame;
the control coefficient generator is arranged behind the accumulation averager and used for calculating a multiplication coefficient of the amplitude output by the RRC;
and the multiplication output device is used for completing the multiplication output of the RRC filtered signal.
5. The digital pulse shaping filter output gain control of claim 4, wherein: the multiplication control RRC filtering output device also comprises a delay Z frame which is used for delay control in the occasion of strict real-time processing requirements.
6. The digital pulse shaping filter output gain control of claim 4, wherein: the amplitude gain factor generated in the control factor generator is one of the power components of 2.
7. The digital pulse shaping filter output gain control of claim 1, wherein: user signal power ratio calculator, accumulation averager, control shift generator and shift output device.
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| CN102055503B (en) * | 2009-11-02 | 2014-04-09 | 中兴通讯股份有限公司 | Digital pre-distortion compensation method and device suitable for time division duplex mode |
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| CN100385995C (en) * | 2005-09-29 | 2008-04-30 | 凯明信息科技股份有限公司 | Method for measuring iso-frequency adjacent community AGC in TD-SCDMA system |
| CN101741348B (en) * | 2009-12-09 | 2012-05-30 | 北京天碁科技有限公司 | Polyphase filter, digital signal processing system and filtering method |
| CN102118139B (en) * | 2009-12-31 | 2014-03-19 | 中兴通讯股份有限公司 | Method and device for dealing with finite precision of filter |
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