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CN100361111C - bus integration system - Google Patents

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CN100361111C
CN100361111C CNB2004100462416A CN200410046241A CN100361111C CN 100361111 C CN100361111 C CN 100361111C CN B2004100462416 A CNB2004100462416 A CN B2004100462416A CN 200410046241 A CN200410046241 A CN 200410046241A CN 100361111 C CN100361111 C CN 100361111C
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bus
data transmission
peripheral device
data
data access
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CN1707458A (en
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蔡志福
谢建民
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RDC Semiconductor Co Ltd
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Abstract

应用在数据处理系统中的总线整合系统包括总线控制模块,搭接至至少一个周边装置,用于根据该周边装置发出的数据存取信息,驱动对应该周边装置数据存取信息的装置进行数据存取;以及总线整合处理器,包括至少一个第一总线数据存取信息接脚以及至少一个第二总线数据存取信息接脚,供该总线控制模块控制第一数据传输规格总线及第二数据传输规格总线的周边装置通过该单一总线,与相同及相异数据传输规格的另一周边装置进行数据存取;通过该总线整合系统,能供不同数据传输规格的总线仅通过单一总线及整合的总线控制系统即可进行数据传输的控制,达到减少硬件占用空间及制造成本的目的。

Figure 200410046241

A bus integration system used in a data processing system includes a bus control module connected to at least one peripheral device and used to drive a device corresponding to the data access information of the peripheral device to access data according to the data access information sent by the peripheral device; and a bus integration processor, including at least one first bus data access information pin and at least one second bus data access information pin, for the bus control module to control the peripheral devices of the first data transmission specification bus and the second data transmission specification bus to access data with another peripheral device of the same or different data transmission specification through the single bus; through the bus integration system, buses with different data transmission specifications can control data transmission only through a single bus and an integrated bus control system, thereby achieving the purpose of reducing hardware space occupation and manufacturing costs.

Figure 200410046241

Description

总线整合系统bus integration system

技术领域technical field

本发明是关于一种总线整合系统,特别是关于一种将不同数据传输规格的总线集成的总线整合系统。The invention relates to a bus integration system, in particular to a bus integration system integrating buses with different data transmission specifications.

背景技术Background technique

总线(BUS)是一组建立在许多计算机元件与元件间的电子电路(electrical circuits),用来在计算机系统的元件间传送数据。实际上可以将总线理解成是一条使用者可共享的高速公路(shared highway),连接着计算机系统的各种不同部分,如中央处理器、内存、磁盘驱动器、打印机、影像系统或输入输出端口等。总线不仅电性连接不同的元件及装置,并具有传送信息的功能。且总线是由中央处理器管理。一条总线同时能传送的数据量,是由移动的二进制电子信息数目的数量来决定。在一台PC里面一般都有下列的四条总线:处理器总线(processorbus)、内存总线(memory bus)、地址总线(address bus)以及输入输出总线(I/O bus)。A bus (BUS) is a group of electronic circuits (electrical circuits) built between many computer components and components, and is used to transmit data between components of a computer system. In fact, the bus can be understood as a shared highway (shared highway) that users can share, connecting various parts of the computer system, such as central processing unit, memory, disk drive, printer, imaging system or input and output ports, etc. . The bus not only electrically connects different components and devices, but also has the function of transmitting information. And the bus is managed by the CPU. The amount of data that can be transferred simultaneously on a bus is determined by the number of binary electronic messages moving. In a PC, there are generally the following four buses: processor bus (processorbus), memory bus (memory bus), address bus (address bus) and input and output bus (I/O bus).

以上述输入输出总线为例,它也称为扩展总线(expansion bus),可让个人计算机的使用者采用标准化的连接器,自行加装诸如显示卡、打印机、光驱等周边装置,所以输入输出总线是使用频率最高的总线。目前常用的总线结构可分为下列五种:工业标准结构总线(ISA-Industry Standard Architecture bus)、微通道结构总线(MCA-MicroChannel Architecture bus)、扩展工业标准结构总线(EISA-ExtendedIndustry Standard Architecture bus)、视频电子标准协会局部总线(VESAlocal-Video Electronics Standard Association Local BUS)、外部设备互联局部总线(PCI local-Peripheral Component Interconnect Local BUS)以及AGP总线(AGP-Accelerated Graphics Port)等。Taking the above-mentioned input and output bus as an example, it is also called an expansion bus (expansion bus), which allows users of personal computers to use standardized connectors to install peripheral devices such as display cards, printers, and optical drives. It is the most frequently used bus. Currently commonly used bus structures can be divided into the following five types: ISA-Industry Standard Architecture bus, MCA-MicroChannel Architecture bus, and EISA-Extended Industry Standard Architecture bus , VESAlocal-Video Electronics Standard Association Local Bus (VESAlocal-Video Electronics Standard Association Local BUS), PCI local-Peripheral Component Interconnect Local Bus (PCI local-Peripheral Component Interconnect Local BUS), and AGP Bus (AGP-Accelerated Graphics Port), etc.

上述外部设备互联局部总线(PCI Local BUS)是由INTEL公司开发的规格,该规格的定义了允许多个与周边元件互连(PCI)兼容的扩充卡安装在计算机中的局部总线系统上。PCI控制器和中央处理器可根据执行的状况决定一次交换32位或64位的数据,并允许具有智能的多个PCI兼容扩充卡,可借由使用总线主控(bus mastering)的技术与中央处理器同时执行工作,且PCI规格允许在总线上同时存在超过一个以上的PCI兼容装置的多任务技术,所以也可将其称为共享总线(share bus)。The above-mentioned PCI Local Bus (PCI Local BUS) is a specification developed by INTEL Corporation, which defines a local bus system that allows multiple PCI-compatible expansion cards to be installed in a computer. The PCI controller and the central processing unit can decide to exchange 32-bit or 64-bit data at a time according to the execution status, and allow multiple PCI-compatible expansion cards with intelligence, which can communicate with the central processing unit by using bus mastering technology. The processor performs work at the same time, and the PCI specification allows the multitasking technology of more than one PCI-compatible device to exist on the bus at the same time, so it can also be called a shared bus (share bus).

除了上述针对个人计算机所设计的总线以外,还有主要为提供笔记本型计算机、膝上型计算机、掌上型计算机和其它便携式计算机及智能型电子装置设计,用于安装PC卡(pC Card)Card BUS插槽的共同标准,它是由个人计算机存储卡国际协会(Personal Computer MemoryCard International Association;PCMCIA)所制定的接口设备连接标准。其中的PC卡是为可移动式的装置,大小如信用卡般,被设计插入PCMCIA规格的Card BUS插槽(PCMCIA Slot)中使用。其中32位的PC卡的PCMCIA总线标准称为卡片总线(Card BUS)。不同于上述PCILocal BUS,能够以共享方式提供允许在总线上同时存在超过一个以上的PCI兼容装置的多任务技术,单一的主桥接器(Host Bridge)仅能提供单一的Card BUS的装置与其连接,所以也可将其称为点对点总线(pointto point bus)。In addition to the above-mentioned buses designed for personal computers, there are also mainly designed to provide notebook computers, laptop computers, palmtop computers and other portable computers and intelligent electronic devices for installing PC cards (pC Card) Card BUS A common standard for slots, which is an interface device connection standard developed by the Personal Computer Memory Card International Association (PCMCIA). The PC card is a removable device, the size of a credit card, and is designed to be inserted into the Card BUS slot (PCMCIA Slot) of the PCMCIA specification. Among them, the PCMCIA bus standard of the 32-bit PC card is called the card bus (Card BUS). Different from the above-mentioned PCILocal BUS, it can provide multitasking technology that allows more than one PCI compatible device to exist on the bus in a shared manner. A single host bridge (Host Bridge) can only provide a single Card BUS device to connect with it. So it can also be called point-to-point bus (point to point bus).

承前所述,虽然PCI Local BUS与Card BUS在单一总线上是否能提供超过一个以上的电子装置方面有所不同,然而两者在系统运行与设定方法上极为相同。但是,迄今两者仍是分别由不同的控制器与中央处理器进行沟通,若能将这两种不同规格的总线结构整合,就能够减少硬件所占的空间及制造成本,因此如何将两者整合是目前急待解决的问题。As mentioned above, although PCI Local BUS and Card BUS are different in whether they can provide more than one electronic device on a single bus, they are very similar in system operation and setting methods. However, so far, the two are still communicated by different controllers and the central processing unit. If the bus structures of these two different specifications can be integrated, the space occupied by the hardware and the manufacturing cost can be reduced. Therefore, how to combine the two Integration is an urgent problem to be solved.

发明内容Contents of the invention

为克服上述现有技术的缺点,本发明的主要目的在于提供一种总线整合系统,借以提供数据传输规格不同但传输协议相似的总线结构,通过单一总线及整合的总线控制模块进行周边装置数据存取的控制。In order to overcome the above-mentioned shortcomings of the prior art, the main purpose of the present invention is to provide a bus integration system, so as to provide a bus structure with different data transmission specifications but similar transmission protocols, and perform peripheral device data storage through a single bus and an integrated bus control module. take control.

本发明的另一目的在于提供一种总线整合系统,提供原来须以点对点方式进行数据传输的总线结构,通过单一总线及整合的总线控制模块进行共享式周边装置数据存取的控制。Another object of the present invention is to provide a bus integration system that provides a bus structure that originally requires data transmission in a point-to-point manner, and controls data access of shared peripheral devices through a single bus and an integrated bus control module.

为达上述及其他目的,本发明的总线整合系统包括:总线控制模块,搭接至至少一个周边装置,根据该周边装置发出的数据存取信息,驱动对应该周边装置数据存取信息的装置,进行数据存取;以及总线整合处理器,其包括至少一个第一总线数据存取信息接脚以与该周边装置中的第一周边装置连接以及至少一个第二总线数据存取信息接脚以与该周边装置中的第二周边装置连接,该第一周边装置兼容于第一数据传输规格的共享式结构,而第二周边装置兼容于第二数据传输规格的点对点式结构,该总线整合处理器通过单一的共用总线与该第一周边装置及第二周边装置连接,且该第一周边装置及第二周边装置通过该共用总线连接,该总线整合处理器通过该共用总线分别控制该第一周边装置及第二周边装置的总线处理器以在不同周期下通过不同时间下激活该第一及第二总线数据存取信号接脚来进行数据的存取。To achieve the above and other purposes, the bus integration system of the present invention includes: a bus control module, connected to at least one peripheral device, and drives a device corresponding to the data access information of the peripheral device according to the data access information sent by the peripheral device, performing data access; and a bus integration processor, which includes at least one first bus data access information pin to connect with the first peripheral device in the peripheral devices and at least one second bus data access information pin to communicate with The second peripheral device in the peripheral device is connected, the first peripheral device is compatible with the shared structure of the first data transmission standard, and the second peripheral device is compatible with the point-to-point structure of the second data transmission standard, the bus integrated processor The first peripheral device and the second peripheral device are connected through a single shared bus, and the first peripheral device and the second peripheral device are connected through the shared bus, and the bus integration processor respectively controls the first peripheral device through the shared bus The bus processors of the device and the second peripheral device perform data access by activating the first and second bus data access signal pins at different times in different cycles.

与现有总线控制系统结构比较,本发明的总线整合系统除了可以提供不同数据传输规格的总线结构,通过单一整合的总线控制模块进行周边装置数据存取的控制外,还可以提供原来须以点对点方式进行数据传输的总线结构,通过单一整合的总线控制模块进行共享式周边装置数据存取的控制,达到减少硬件所占的空间及制造成本的目的。Compared with the structure of the existing bus control system, the bus integration system of the present invention can not only provide bus structures with different data transmission specifications, but also control the data access of peripheral devices through a single integrated bus control module. The bus structure for data transmission by means of a single integrated bus control module controls the data access of shared peripheral devices to achieve the purpose of reducing the space occupied by the hardware and the manufacturing cost.

附图说明Description of drawings

图1是系统结构方块示意图,显示本发明的总线整合的系统结构;Fig. 1 is a schematic block diagram of the system structure, showing the system structure of the bus integration of the present invention;

图2是总线整合系统在数据传输时的波形示意图。FIG. 2 is a schematic diagram of the waveform of the bus integration system during data transmission.

具体实施方式Detailed ways

实施例Example

以下通过特定的具体实施例说明本发明的实施方式。The implementation of the present invention will be described below through specific specific examples.

在以下实施例中,本发明的总线整合系统应用在个人计算机系统中,该个人计算机系统至少具有一个外部设备互联局部总线(PCI LocalBUS)系统,以及一个卡片总线(Card BUS)系统。其中,该PCI Local BUS系统,供使用者通过诸如周边元件互连插槽(PCI Slot),安装符合该PCI数据传输规格的扩充卡,例如网络卡及/或显示卡等;该Card BUS系统则供使用者通过PCMCIA规格的Card BUS插槽(PCMCIA Slot),安装符合该PCMCIA规格的PC卡(PC Card),且在本实施例中,该PC卡是32位的规格。由于该PCI及该Card BUS的总线结构是现有技术,所以,以下仅针对与本发明的总线整合系统有关的部分进行说明。In the following embodiments, the bus integration system of the present invention is applied in a personal computer system, which has at least one PCI LocalBUS system and a Card BUS system. Among them, the PCI Local BUS system is for users to install expansion cards that meet the PCI data transmission specifications, such as network cards and/or display cards, etc., through peripheral component interconnection slots (PCI Slots); the Card BUS system is For the user through the Card BUS slot (PCMCIA Slot) of PCMCIA specification, install the PC card (PC Card) that meets this PCMCIA specification, and in the present embodiment, this PC card is the specification of 32 bits. Because the bus structure of this PCI and this Card BUS is prior art, so, only illustrate for the part relevant to the bus integration system of the present invention below.

图1是本发明的总线整合系统100的系统结构示意图,该总线整合系统包括:总线控制模块110以及PCI总线整合处理器120。FIG. 1 is a schematic diagram of the system structure of the bus integration system 100 of the present invention, the bus integration system includes: a bus control module 110 and a PCI bus integration processor 120 .

该总线控制模块110,分别搭接至中央处理单元130、存储单元140与PCI总线150,根据中央处理单元130发出的数据存取信息,驱动该中央处理单元130、该存储单元140或周边装置相互之间进行数据存取。在本实施例中,该总线控制模块110除包括该用于处理PCI总线的PCI总线整合处理器120外,还包括处理与该中央处理单元130间总线的中央处理单元总线处理器(图未标),以及处理与该存储单元140间总线的存储单元总线处理器(图未标)。The bus control module 110 is connected to the central processing unit 130, the storage unit 140 and the PCI bus 150 respectively, and drives the central processing unit 130, the storage unit 140 or peripheral devices to communicate with each other according to the data access information sent by the central processing unit 130. data access between. In this embodiment, the bus control module 110 also includes a central processing unit bus processor (not marked in the figure) for processing the bus between the central processing unit 130 except the PCI bus integration processor 120 for processing the PCI bus. ), and a storage unit bus processor (not shown) that handles the bus between the storage unit 140.

该PCI总线整合处理器120,建置在该总线控制模块110中,至少包括PCI BUS数据传输起始信号接脚(frame)111以及至少一个CardBUS数据传输起始信号接脚(cframe)112,供该总线控制模块控制PCI及/或Card BUS的周边装置进行数据存取。其中该PCI BUS数据传输起始信号接脚(frame)111被激活,是从PCI装置发出数据存取请求信号或其它装置对该PCI装置发出数据存取请求信号;该Card BUS数据传输起始信号接脚(cframe)112被激活,是从Card BUS装置发出数据存取请求信号或其它装置对该Card BUS装置发出数据存取请求信号。通过激活不同的起始信号接脚,供相应的周边装置间进行数据存取。The PCI bus integration processor 120, built in the bus control module 110, at least includes a PCI BUS data transmission start signal pin (frame) 111 and at least one CardBUS data transmission start signal pin (cframe) 112, for The bus control module controls peripheral devices of PCI and/or Card BUS to perform data access. Wherein the PCI BUS data transmission start signal pin (frame) 111 is activated, which is to send a data access request signal from the PCI device or other devices to send a data access request signal to the PCI device; the Card BUS data transmission start signal The pin (cframe) 112 is activated to send a data access request signal from the Card BUS device or another device sends a data access request signal to the Card BUS device. By activating different start signal pins, data access is provided between corresponding peripheral devices.

其中,该中央处理单元130用于提供该个人计算机系统提取、译码及执行指令的功能,并可通过数据传输路径如上述介于该总线控制模块110间的中央处理单元总线处理器等,从其它资源处传递及接收数据等。Wherein, the central processing unit 130 is used to provide the personal computer system with the functions of extracting, decoding and executing instructions, and can transmit data from the central processing unit bus processor, etc. Other resources transmit and receive data, etc.

该存储单元140提供该个人计算机系统的其它模块或单元快速存取所需数据的随机存储器(Random Access Memory;RAM),例如动态随机存储器(Dynamic Random Access Memory;DRAM)、同步动态随机存储器(Synchronous Dynamic Random Access Memory;SDRAM)或双倍速同步动态随机存取存储器(Double Data Rate Synchronous DynamicRandom Access Memory;DDRSDRAM)等。且它也可如该中央处理单元130般,通过与该总线控制模块110间的存储单元总线处理器等从其它资源处传递及接收数据。The storage unit 140 provides random access memory (Random Access Memory; RAM) for other modules or units of the personal computer system to quickly access the required data, such as Dynamic Random Access Memory (Dynamic Random Access Memory; DRAM), Synchronous Dynamic Random Access Memory (Synchronous Dynamic Random Access Memory; SDRAM) or double-speed synchronous dynamic random access memory (Double Data Rate Synchronous Dynamic Random Access Memory; DDRSDRAM), etc. And it can also transmit and receive data from other resources through the storage unit bus processor between the bus control module 110 and the like, like the central processing unit 130 .

该PCI总线150在本实施例中是PCI Local BUS结构,并分别搭接至PCI插槽151与PCI slot152,以及PCMCIA规格的Card BUS插槽153;其中,该PCI插槽151与152分别用于提供使用者安装符合该PCI数据传输规格的网络卡154与显示卡155;该PCMCIA规格的Card BUS插槽153则用于提供使用者安装符合该PCMCIA规格的无线网络卡156。需特别说明的是,在本实施例中为便于突出本发明的技术特征,该PCI总线150是指除该PCI BUS数据传输起始信号接脚(frame)111及该Card BUS数据传输起始信号接脚(cframe)112两个接脚以外的数据传输线,与现有包括所有数据传输线在内的PCI BUS有所不同。The PCI bus 150 is a PCI Local BUS structure in this embodiment, and is respectively lapped to a PCI slot 151 and a PCI slot 152, and a Card BUS slot 153 of the PCMCIA specification; wherein, the PCI slots 151 and 152 are respectively used for Provide the user to install the network card 154 and the display card 155 that meet the PCI data transmission specification; the Card BUS slot 153 of the PCMCIA specification is used to provide the user to install the wireless network card 156 that meets the PCMCIA specification. It should be noted that, in the present embodiment, for the convenience of highlighting the technical characteristics of the present invention, the PCI bus 150 refers to the PCI BUS data transmission start signal pin (frame) 111 and the Card BUS data transmission start signal The data transmission lines other than the two pins of the pin (cframe) 112 are different from the existing PCI BUS including all data transmission lines.

承前所述,该总线控制模块110与该PCI总线150间至少设有以下的信号输出入接脚:该PCI BUS数据传输起始信号接脚(frame)111被激活,是在PCI装置发出数据存取请求信号或其它装置对该PCI装置发出数据存取请求信号,以及该Card BUS数据传输起始信号接脚(cframe)112被激活,是在Card BUS装置发出数据存取请求信号或其它装置对该Card BUS装置发出数据存取请求信号。此外,该总线控制模块110与该PCI总线150间还包括以下信号输出入接脚:As mentioned above, at least the following signal input and output pins are provided between the bus control module 110 and the PCI bus 150: the PCI BUS data transmission start signal pin (frame) 111 is activated, which is sent by the PCI device to store data. Get a request signal or other devices send a data access request signal to the PCI device, and the Card BUS data transmission start signal pin (cframe) 112 is activated, is to send a data access request signal or other devices to the Card BUS device The Card BUS device sends a data access request signal. In addition, the bus control module 110 and the PCI bus 150 also include the following signal input and output pins:

(1)脉冲信号接脚(CLK),供各该周边装置接收时序(Timing)信号输入的接脚。(1) Pulse signal pin (CLK), a pin for each peripheral device to receive a timing signal input.

(2)启动器就绪接脚(Initiator Ready;IRDY),供该主要装置发出告知目标装置已准备接收传输数据的信号。(2) Initiator Ready pin (Initiator Ready; IRDY), for the main device to send a signal to inform the target device that it is ready to receive transmission data.

(3)目标就绪接脚(Target Ready;TRDY),供该目标装置(Target)发出告知该主要装置已准备传输数据的信号。(3) Target ready pin (Target Ready; TRDY), for the target device (Target) to send a signal to inform the main device that it is ready to transmit data.

(4)装置选择接脚(Device Select;DEVSEL),供该目标装置发出告知已被主要装置选择的信号。(4) Device Select pin (Device Select; DEVSEL), for the target device to send a signal to inform that it has been selected by the main device.

(5)停止接脚(Stop),供该目标装置发出停止数据传输的信号。(5) Stop pin (Stop), for the target device to send a signal to stop data transmission.

(6)地址数据接脚(Address and Data;AD),传输地址及数据的信号。(6) Address and Data pin (Address and Data; AD), a signal for transmitting address and data.

(7)总线命令/字节激活接脚(Bus Command and Byte Enable;C/BE),供该主要装置发出传输总线控制命令的信号。(7) Bus Command and Byte Enable pin (Bus Command and Byte Enable; C/BE), for the main device to send a signal for transmitting bus control commands.

承前所述,需特别说明的是,在本实施例中,除该Card BUS数据传输起始信号接脚(cframe)112外,各该接脚均与现有PCI Local BUS的接脚功能兼容,且在此处仅显示与本发明的总线整合系统有关的接脚,其余的接脚均兼容于该PCI Local BUS的规格,故在此不再说明。As mentioned above, it should be noted that in this embodiment, except the Card BUS data transmission start signal pin (cframe) 112, each of these pins is compatible with the pin function of the existing PCI Local BUS, And only the pins related to the bus integration system of the present invention are shown here, and the rest of the pins are compatible with the PCI Local BUS specification, so they will not be described here.

图2是该总线控制模块110在执行周边装置间数据传输时的波形示意图。FIG. 2 is a schematic waveform diagram of the bus control module 110 when performing data transmission between peripheral devices.

承前所述,在本实施例中,当该无线网络卡156要从该存储单元140读取数据时,该无线网络卡156设定为主要装置,该PCI总线整合处理器120则设为目标装置,令该PCI总线整合处理器120可根据该无线网络卡156的读取数据请求,通过介于该存储单元140间的存储单元总线处理器向该存储单元140读取数据。此外,由该无线网络卡156发出总线数据存取信息,在此实施例中该总线数据存取信息是指Card BUS数据传输起始信号接脚(cframe)112发出低电位信号,用于表示符合卡片总线数据传输规格的该无线网络卡156在进行数据读取,并将该信号传送至该PCI总线整合处理器120。As mentioned above, in this embodiment, when the wireless network card 156 is to read data from the storage unit 140, the wireless network card 156 is set as the master device, and the PCI bus integrated processor 120 is set as the target device so that the PCI bus integration processor 120 can read data to the storage unit 140 through the storage unit bus processor interposed between the storage units 140 according to the data read request of the wireless network card 156 . In addition, the bus data access information is sent by the wireless network card 156. In this embodiment, the bus data access information means that the Card BUS data transmission start signal pin (cframe) 112 sends a low potential signal, which is used to indicate compliance with The wireless network card 156 of the card bus data transmission standard is reading data and sending the signal to the PCI bus integrated processor 120 .

其次,令该无线网络卡156发出启动器就绪的信号至该PCI总线整合处理器120,用于表示该无线网络卡156已做好数据读取的准备。Secondly, make the wireless network card 156 send an initiator ready signal to the PCI bus integrated processor 120 to indicate that the wireless network card 156 is ready for data reading.

接着,令该PCI总线整合处理器120发出装置选择信号,用于表示该PCI总线整合处理器120被选取,之后,通过该存储单元总线处理器取得该存储单元140的数据,令该PCI总线整合处理器120发出目标就绪信号,用于表示该PCI总线整合处理器120已做好被读取数据的准备。Then, make the PCI bus integration processor 120 send a device selection signal to indicate that the PCI bus integration processor 120 is selected, and then obtain the data of the storage unit 140 through the storage unit bus processor to make the PCI bus integration The processor 120 sends a target ready signal to indicate that the PCI bus integrated processor 120 is ready to read data.

同时,该无线网络卡156根据该总线命令/字节激活所设定的命令内容,通过该总线控制模块110的PCI总线整合处理器120进行数据的读取。At the same time, the wireless network card 156 reads data through the PCI bus integrated processor 120 of the bus control module 110 according to the command content set by the bus command/byte activation.

承前所述,若有另一网络卡154要从该存储单元140读取数据时,该网络卡154被设定为主要装置,而该PCI总线整合处理器120则设为目标装置,借以令该PCI总线整合处理器120可根据该网络卡154的读取数据请求,通过介于该存储单元140间的存储单元总线处理器向该存储单元140读取数据。由该网络卡154发出另一总线数据存取信息,在此实施例该另一总线数据存取信息是指PCI BUS数据传输起始信号接脚(frame)111发出低电位信号,用于表示符合PCI数据传输规格的该网络卡154要进行数据读取,并将该信号传送至该PCI总线整合处理器120。As mentioned above, if another network card 154 is to read data from the storage unit 140, the network card 154 is set as the master device, and the PCI bus integrated processor 120 is set as the target device, so that the The PCI bus integration processor 120 can read data to the storage unit 140 through the storage unit bus processor interposed between the storage units 140 according to the data read request of the network card 154 . Another bus data access information is sent by the network card 154. In this embodiment, the other bus data access information refers to that the PCI BUS data transmission start signal pin (frame) 111 sends a low potential signal, which is used to indicate compliance with The network card 154 of the PCI data transmission standard needs to read data and transmit the signal to the PCI bus integrated processor 120 .

其次,令该网络卡154发出启动器就绪的信号至该PCI总线整合处理器120,用于表示该网络卡154已做好数据读取的准备。Secondly, make the network card 154 send an initiator ready signal to the PCI bus integration processor 120 to indicate that the network card 154 is ready for data reading.

接着,令该PCI总线整合处理器120发出装置选择信号用于表示该PCI总线整合处理器120被选取,之后通过该存储单元总线处理器取得该存储单元140的数据,令该PCI总线整合处理器120发出目标就绪信号,用于表示该PCI总线整合处理器120已做好被数据读取的准备。Then, the PCI bus integration processor 120 is made to send a device selection signal for indicating that the PCI bus integration processor 120 is selected, and then the data of the storage unit 140 is obtained through the storage unit bus processor, so that the PCI bus integration processor 120 sends out a target ready signal, which is used to indicate that the PCI bus integrated processor 120 is ready to be read by data.

同时,该网络卡154根据该总线命令/字节激活所设定的命令内容,通过该总线控制模块110的PCI总线整合处理器120进行数据的读取。At the same time, the network card 154 reads data through the PCI bus integrated processor 120 of the bus control module 110 according to the command content set by the bus command/byte activation.

承前所述,该总线控制模块110的PCI总线整合处理器120通过接收不同总线数据传输规格的周边装置所发出的数据存取请求,借以判断该周边装置数据传输规格,并根据该周边数据传输规格供该周边装置进行数据存取。As mentioned above, the PCI bus integration processor 120 of the bus control module 110 receives data access requests from peripheral devices with different bus data transmission specifications to determine the data transmission specifications of the peripheral devices, and according to the peripheral data transmission specifications For the peripheral device to perform data access.

此外,另该PCI总线整合处理器120监控该PCI总线的数据传输状况,供周边装置在符合该总线规格下进行数据传输,借以避免不同数据传输的总线间发生总线竞争的情况。In addition, the PCI bus integration processor 120 monitors the data transmission status of the PCI bus for peripheral devices to perform data transmission in compliance with the bus specification, so as to avoid bus contention between different data transmission buses.

本发明的总线整合系统只需在该PCI总线整合处理器120上增加Card BUS数据传输起始信号接脚(cframe),即可连接相同于该CardBUS数据传输起始信号接脚(cframe)的卡片总线规格的周边装置,换言之,多个卡片总线规格周边装置借由该PCI总线整合处理器120,仅需通过总线接口即可进行数据的传输,达到如同周边装置总线般,允许在总线上同时存在超过一个以上的电子信号的多任务技术。The bus integration system of the present invention only needs to increase the Card BUS data transmission start signal pin (cframe) on the PCI bus integration processor 120, and can connect the same card as the CardBUS data transmission start signal pin (cframe) Peripheral devices with bus specifications, in other words, multiple peripheral devices with card bus specifications can transmit data only through the bus interface through the PCI bus integrated processor 120, allowing them to exist simultaneously on the bus just like the peripheral device bus Multitasking of more than one electronic signal.

综上所述,本发明的总线整合系统除可提供不同数据传输规格的总线结构,通过单一总线及整合的总线控制模块进行周边装置数据存取的控制外,还可以提供原来须以点对点进行数据传输的总线结构,通过单一总线及整合的总线控制模块进行共享式周边装置数据存取的控制,达到减少硬件所占的空间及制造成本的目的。In summary, the bus integration system of the present invention can not only provide bus structures with different data transmission specifications, but also control peripheral device data access through a single bus and an integrated bus control module, and can also provide point-to-point data access control. The bus structure of the transmission uses a single bus and an integrated bus control module to control the data access of the shared peripheral devices, so as to achieve the purpose of reducing the space occupied by the hardware and the manufacturing cost.

此外,本发明的总线整合系统应用在Card BUS规格的周边装置时,该Card BUS数据传输起始信号接脚(cframe)的数量可根据该CardBUS周边装置的数量进行增减,则该Card BUS周边装置的数量可根据使用者的需要进行增减。另一方面,根据上述总线整合系统的原理,该总线整合系统也可应用在仅具有多个Card BUS周边装置的个人计算机系统上,通过对应这些Card BUS周边装置数量的多个Card BUS数据传输起始信号接脚(cframe),提供这些Card BUS周边装置在其它周边装置进行数据的存取工作。In addition, when the bus integration system of the present invention is applied to a peripheral device of the Card BUS specification, the number of the Card BUS data transmission start signal pin (cframe) can be increased or decreased according to the number of the Card BUS peripheral device, and the Card BUS peripheral The number of devices can be increased or decreased according to the needs of users. On the other hand, according to the principle of the above-mentioned bus integration system, the bus integration system can also be applied to a personal computer system with only a plurality of Card BUS peripheral devices. The start signal pin (cframe) provides these Card BUS peripheral devices to perform data access work in other peripheral devices.

此外,本发明的总线整合系统还可整合在集成电路芯片(IC Chip)中,用于提供各种电子装置有效率的总线整合的解决方案。In addition, the bus integration system of the present invention can also be integrated into an integrated circuit chip (IC Chip) to provide efficient bus integration solutions for various electronic devices.

Claims (17)

1.一种总线整合系统,应用在数据处理系统中,提供与该数据处理系统相互连接的不同数据传输规格的周边装置,通过单一总线整合处理机制进行数据传输,其特征在于,该总线整合系统包括:1. A bus integration system, which is applied in a data processing system, provides peripheral devices of different data transmission specifications interconnected with the data processing system, and performs data transmission through a single bus integration processing mechanism. It is characterized in that the bus integration system include: 总线控制模块,供至少一个总线处理器搭接至所属的周边装置,用于根据该周边装置发出的数据存取信息,驱动对应该周边装置数据存取信息的总线处理器,进行数据存取,进而达到各总线处理器间的数据交换;以及The bus control module is used to connect at least one bus processor to the associated peripheral device, and is used to drive the bus processor corresponding to the data access information of the peripheral device to perform data access according to the data access information sent by the peripheral device, Thereby achieving data exchange among bus processors; and 总线整合处理器,其包括至少一个第一总线数据存取信息接脚以与该周边装置中的第一周边装置连接以及至少一个第二总线数据存取信息接脚以与该周边装置中的第二周边装置连接,该第一周边装置兼容于第一数据传输规格的共享式结构,而第二周边装置兼容于第二数据传输规格的点对点式结构,该总线整合处理器通过单一的共用总线与该第一周边装置及第二周边装置连接,且该第一周边装置及第二周边装置通过该共用总线连接,该总线整合处理器通过该共用总线分别控制该第一周边装置及第二周边装置的总线处理器以在不同周期下通过不同时间下激活该第一及第二总线数据存取信号接脚来进行数据的存取。A bus integration processor comprising at least one first bus data access information pin for connecting with the first peripheral device among the peripheral devices and at least one second bus data access information pin for connecting with the first peripheral device among the peripheral devices Two peripheral devices are connected, the first peripheral device is compatible with the shared structure of the first data transmission standard, and the second peripheral device is compatible with the point-to-point structure of the second data transmission standard, and the bus integrated processor communicates with the bus through a single shared bus The first peripheral device and the second peripheral device are connected, and the first peripheral device and the second peripheral device are connected through the shared bus, and the bus integration processor controls the first peripheral device and the second peripheral device respectively through the shared bus The bus processor performs data access by activating the first and second bus data access signal pins at different times in different cycles. 2.如权利要求1所述的系统,其特征在于,该第一数据传输规格是外部设备互联局部总线,该第一总线数据存取信息接脚是该外部设备互联局部总线规格的数据传输起始信号接脚。2. The system according to claim 1, wherein the first data transmission specification is an external device interconnection local bus, and the first bus data access information pin is a data transmission start of the external device interconnection local bus specification. start signal pin. 3.如权利要求1所述的系统,其特征在于,该第一数据传输规格是卡片总线,该第一总线数据存取信息接脚是该卡片总线规格的数据传输起始信号接脚。3. The system according to claim 1, wherein the first data transmission standard is a card bus, and the data access information pin of the first bus is a data transmission start signal pin of the card bus standard. 4.如权利要求1所述的系统,其特征在于,该第二数据传输规格是卡片总线;该第二总线数据存取信息接脚是该卡片总线规格的数据传输起始信号接脚。4. The system of claim 1, wherein the second data transmission standard is a card bus; the data access information pin of the second bus is a data transmission start signal pin of the card bus standard. 5.如权利要求1所述的系统,其特征在于,该共用总线可以是规格内定义完整功能的外部设备互联局部总线或支持部分功能的外部设备互联局部总线中的一种。5 . The system according to claim 1 , wherein the shared bus can be one of a local bus for interconnecting peripheral devices with complete functions defined in the specification or a local bus for interconnecting peripheral devices supporting partial functions. 6 . 6.如权利要求1所述的系统,其特征在于,该共用总线可以是规格内所定义完整功能的卡片总线或支持部分功能的卡片总线中的一种。6. The system according to claim 1, wherein the shared bus can be one of a full-function card bus or a card bus supporting partial functions defined in the specification. 7.如权利要求1所述的系统,其特征在于,该第一数据传输规格可以是共享式结构的总线规格。7. The system of claim 1, wherein the first data transmission standard is a bus standard of a shared structure. 8.如权利要求1所述的系统,其特征在于,该第一数据传输规格可以是点对点式结构的总线规格。8. The system of claim 1, wherein the first data transmission standard is a point-to-point bus standard. 9.如权利要求1所述的系统,其特征在于,该总线整合处理器可以是支持第一数据传输规格全部功能或部分功能的总线处理器中的一种。9. The system of claim 1, wherein the bus integration processor is one of the bus processors supporting all or part of the functions of the first data transmission specification. 10.如权利要求1所述的系统,其特征在于,该总线整合处理器可以是支持第二数据传输规格全部功能或部分功能的总线处理器中的一种。10. The system of claim 1, wherein the bus integration processor is one of the bus processors supporting all or part of the functions of the second data transmission specification. 11.如权利要求1所述的系统,其特征在于,该总线整合处理器包括多个该第二总线数据存取信息接脚时,各该第二总线数据存取信息接脚与该周边装置中兼容于第二数据传输规格的一个周边装置连接,供各周边装置借由相对应的第二总线数据存取信息接脚,发出数据存取请求信号或其它装置对该周边装置发出数据存取请求信号。11. The system according to claim 1, wherein when the bus integration processor includes a plurality of data access information pins of the second bus, each of the data access information pins of the second bus is connected to the peripheral device A peripheral device compatible with the second data transmission standard is connected, for each peripheral device to send a data access request signal or other devices to send data access to the peripheral device through the corresponding second bus data access information pin request signal. 12.如权利要求1所述的系统,其特征在于,该系统可应用在电子产品中。12. The system according to claim 1, characterized in that the system can be applied in electronic products. 13.如权利要求12所述的系统,其特征在于,该电子产品可以是个人计算机、笔记本型计算机、掌上型计算机、个人数字助理、平板型计算机、服务器系统、工作站、数字家电、移动设备、通信设备、多媒体设备、医疗器材、自动化控制设备中的一种。13. The system according to claim 12, wherein the electronic product can be a personal computer, a notebook computer, a palmtop computer, a personal digital assistant, a tablet computer, a server system, a workstation, a digital home appliance, a mobile device, One of communication equipment, multimedia equipment, medical equipment, and automation control equipment. 14.如权利要求1所述的系统,其特征在于,该总线控制模块整合在集成电路芯片中。14. The system of claim 1, wherein the bus control module is integrated in an integrated circuit chip. 15.如权利要求1所述的系统,其特征在于,该总线整合处理器整合在集成电路芯片中。15. The system of claim 1, wherein the bus integration processor is integrated in an integrated circuit chip. 16.如权利要求1所述的系统,其特征在于,该总线整合处理器整合在该总线控制模块中。16. The system of claim 1, wherein the bus integration processor is integrated in the bus control module. 17.如权利要求1所述的系统,其特征在于,该总线控制模块与该总线整合处理器是独立的集成电路芯片。17. The system of claim 1, wherein the bus control module and the bus integration processor are independent integrated circuit chips.
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