CN100365924C

CN100365924C - Regulator of reduction voltage

Info

Publication number: CN100365924C
Application number: CNB2004100615731A
Authority: CN
Inventors: 吴永禄; 沈文君; 陈建尧
Original assignee: Quanta Computer Inc
Current assignee: Quanta Computer Inc
Priority date: 2004-12-27
Filing date: 2004-12-27
Publication date: 2008-01-30
Anticipated expiration: 2024-12-27
Also published as: CN1797914A

Abstract

The present invention relates to a regulator of voltage reduction, which comprises a first transistor, a second transistor, a filter circuit, a capacitor and a switch, wherein a drain electrode of the first transistor receives first direct current voltage, a grid electrode of the first transistor receives a first control signal, and a source electrode of the first transistor is coupled with a node. A drain electrode of a second transistor is coupled with the node, a grid electrode of the second transistor receives a second control signal, and a source electrode of the second transistor is coupled with fixed voltage. The filter circuit is electrically connected with the node and outputs second direct current voltage. The switch is provided with a first end, a second end and a control end, wherein the first end is electrically connected with the grid electrode of the second transistor through the capacitor; the second end is electrically connected with the source electrode of the second transistor. The control end receives the first control signal; the switching speed of the switch is greater than that of the first transistor. When the first control signal is enabled, the first transistor is switched on with the switch; the capacitor is connected in parallel with the grid electrode of the second transistor and both ends of the source electrode.

Description

Regulator of reduction voltage

Technical field

The relevant a kind of regulator of reduction voltage (buck converter) of the present invention, and particularly relevant a kind of inhibition runs through the synchronous buck adjuster (Synchronous buck converter) of voltage (shoot through voltage).

Background technology

Please refer to Fig. 1, it is the circuit diagram of conventional synchronization regulator of reduction voltage.Synchronous buck adjuster (Synchronous buck converter) 100 receives the first direct voltage Vin, and exports the adjustable second direct voltage Vout according to this.Synchronous buck adjuster 100 comprises the first transistor Q1, transistor seconds Q2, filter circuit 102.The drain D 1 of the first transistor Q1 receives the first direct voltage Vin.The grid G 1 of the first transistor Q1 receives the first control signal C1, and its source S 1 is coupled to a node N.The grid G 2 of transistor seconds Q2 couples the second control signal C2, and its source S 2 couples fixed voltage, for example is ground connection.Filter circuit 102 couples node N, in order to export the second direct voltage Vout behind the voltage filtering interchange noise with node N.

Because of

drain D

2 and 2 of the grid G of transistor seconds Q2 has grid-drain parasitic capacitance Cgd2, and 2 of grid G 2 and source S also have grid-source electrode parasitic capacitance Cgs2, so when the first transistor Q1 conducting (turn on), the first direct voltage Vin put on the first transistor Q1, grid-drain parasitic capacitance Cgd2, with grid-source electrode parasitic capacitance Cgs 2, therefore can produce one in the grid G 2 of transistor seconds Q2 and run through voltage (Shoot-throughvoltage) SV, please refer to Fig. 2, it is the oscillogram of the voltage VG2 of the voltage VG1 of gate terminal G1 and gate terminal G2.As can be seen from Figure 2 when the first transistor Q1 conducting, the first direct voltage Vin can produce in the gate terminal G2 of transistor seconds Q2 and run through voltage SV, when serious, because the aisle resistance value of two transistor Q1, Q2 is all little, when this runs through voltage SV when also bigger than the forward bias voltage drop (threshold) of transistor seconds Q2, will make two transistor Q1, Q2 conductings simultaneously and burnt by the first direct voltage Vin.

And tradition solves that to run through voltage method be to utilize a capacitor C add Cgs2 is in parallel with grid-source electrode parasitic capacitance, runs through the size of voltage with reduction after making the direct voltage Vin that wins via capacitor C add and grid-source electrode parasitic capacitance Cgs2 dividing potential drop.But the capacitor C add that increases can cause the time of transistor seconds Q2 conducting (turn on) slack-off, because of getting, the second control signal C2 earlier capacitor C add is charged, make the power switched loss of transistor seconds Q2 increase, and reduce the efficient of synchronous buck adjuster 100.Therefore, increase capacitor C add solution and run through the problem that voltage burns the first transistor Q1 and transistor seconds Q2, but cause the efficient step-down of synchronous buck adjuster 100.Therefore, for the efficient that suppresses to run through voltage and improve synchronous buck adjuster 100 simultaneously, this is the problem that industry is badly in need of solution.

Summary of the invention

In view of this, the purpose of this invention is to provide a kind of regulator of reduction voltage, it has the effect that suppresses to run through the size of voltage and improve the efficient of regulator of reduction voltage.

According to regulator of reduction voltage of the present invention (buck converter), it comprises the first transistor, transistor seconds, filter circuit, electric capacity and switch.The drain electrode of the first transistor receives first direct voltage, and its grid receives first control signal, and source electrode is coupled to node.The drain electrode of transistor seconds couples this node, and its grid receives second control signal, and source electrode is coupled to fixed voltage.Filter circuit and node electrically connect are also exported second direct voltage.Switch has first end, second end and control end.First end electrically connects via the grid of electric capacity and transistor seconds.The source electrode of second end and transistor seconds electrically connects.Control end receives first control signal.

Wherein, the switch speed of switch is greater than the switch speed of the first transistor.When the first control signal activation, the first transistor and switch conduction, electric capacity are parallel to the grid and the source electrode two ends of transistor seconds.The capacitance of electric capacity is enough to make first direct voltage to run through the critical voltage that voltage (Shoot-through voltage) is lower than transistor seconds in what the grid of transistor seconds produced.

For the present invention's above-mentioned purpose, characteristics and advantage can be become apparent, below will be especially exemplified by a preferred embodiment, and conjunction with figs. is elaborated.

Description of drawings

Fig. 1 is the circuit diagram of conventional synchronization regulator of reduction voltage.

Fig. 2 is the oscillogram of the voltage VG2 of the voltage VG1 of gate terminal G1 and gate terminal G2.

Fig. 3 is the circuit diagram according to a kind of regulator of reduction voltage of a preferred embodiment of the present invention.

Embodiment

Please refer to Fig. 3, it is the circuit diagram according to a kind of regulator of reduction voltage of a preferred embodiment of the present invention.Regulator of reduction voltage 200 for example is synchronous buck adjuster (Synchronous buck converter), and it comprises the first transistor Q1 ', transistor seconds Q2 ', filter circuit 202, capacitor C add ' and switch SW.Transistor Q1 ', Q2 ' for example are NMOS.The drain D 1 of the first transistor Q1 ' ' reception first direct voltage Vin, its grid G 1 ' reception first control signal Ctrl 1, and source S 1 ' be coupled to node N '.

The drain D 2 of transistor seconds Q2 ' ' couple node N ', its grid G 2 ' reception second control signal Ctrl2, and source S 2 ' being coupled to fixed voltage, fixed voltage for example is an earthed voltage.Filter circuit 202 is with node N ' electrically connect and export the second direct voltage Vout '.

Switch SW has the first end X1, the second end X2 and control end CX.The first end X1 is via the grid G 2 ' electric connection of capacitor C add ' with transistor Q2 '.The source S 2 of the second end X2 and transistor Q2 ' ' electric connection.Control end CX receives the first control signal Ctrl 1.When the first control signal Ctrl, 1 activation, transistor Q1 ' and switch SW just can conductings, capacitor C add ' be parallel to the grid G 2 of transistor Q2 ' ' and source S 2 '.The capacitance of capacitor C add ' is enough to make run through the critical voltage that voltage (Shoot-through voltage) be lower than transistor Q2 ' of the first direct voltage Vin in grid G 2 ' generation of transistor Q2 '.

Furthermore, switch SW for example is the 3rd transistor Q3, and it is according to the first control signal Ctrl, 1 conducting or end.Transistor Q3 for example is NMOS, and its drain electrode is that the first end X1 of switch SW, its source electrode are the second end X2 of switch SW, and grid is the control end CX of switch SW.Via suitable design, make that the parasitic input capacitance of transistor Q3 is the parasitic input capacitance less than transistor Q1 ', so the switch speed of transistor Q3 can be greater than the switch speed of transistor Q1 '.So when the first control signal Ctrl, 1 activation, transistor Q3 is than the first conducting of transistor Q1 ', with the grid G 2 that earlier capacitor C add ' is parallel to transistor Q2 ' ' with source S 2 ', to run through voltage (Shoot-through voltage) in grid G 2 ' generation of transistor seconds Q2 ' after the Q1 ' conducting of inhibition transistor.

Utilize the switch speed of the switch speed (switching speed) of the 3rd transistor Q3 greater than the first transistor Q1 ', when making the same foundation of the 3rd transistor Q3 and the first transistor Q1 ' first control signal Ctrl 1 with conducting, the 3rd transistor Q3 is but than the faster conducting of the first transistor Q1 '.So when the first control signal Ctrl, 1 activation, the conducting of the 3rd transistor Q3 elder generation, make that the parasitic input capacitance Cgs2 ' of grid-source electrode of capacitor C add ' and transistor seconds Q2 ' is in parallel, so grid G 2 of transistor seconds Q2 ' ' with source S 2 ' the equivalent capacitance value increase.When so the first transistor Q1 ' follows conducting, the first direct voltage Vin runs through the size of voltage with reduction after via the parasitic input capacitance Cgs2 ' dividing potential drop of capacitor C add ' and grid-source electrode, make the forward bias voltage drop (threshold) that runs through voltage and be unlikely to exceed transistor seconds Q2 ', with the forward bias voltage drop of avoiding running through voltage ratio transistor seconds Q2 ' when also big, make two transistor Q1 ', Q2 ' while conducting and the situation of being burnt by the first direct voltage Vin.

And when the second control signal Ctrl, 2 activations, because the first control signal Ctrl 1 of control the 3rd transistor Q3 is a disabled, so the 3rd transistor Q3 is for ending (turn off), this moment, capacitor C add ' can't be in parallel with the parasitic input capacitance Cgs2 ' of grid-source electrode.So, the conducting speed of transistor seconds Q2 ' just can not be subjected to the influence of capacitor C add '.Solved traditional because of the second control signal Ctrl 2 earlier to capacitor C add ' charging, make transistor seconds Q2 ' power switched loss increase and make the slack-off problem of conducting speed, and reduced the efficiency of synchronous buck adjuster 200.

In addition, transistor has power switched loss (switching loss) when making switch.Power switched loss is because transistor has parasitic input capacitance, makes transistor turns/slack-off by the time of (turn-on/off), the power loss that is caused.So in order to improve the efficient of synchronous buck adjuster 200, the parasitic input capacitance value of the first transistor Q1 ' is reduced to improve switch speed (switchingspeed).But also since the switch speed of the first transistor Q1 ' accelerate, can cause be reflected at grid G 2 ' on run through voltage and will become bigger.But by spirit of the present invention, can reach the size that suppresses to run through voltage, so just can select than traditional switch speed faster transistor think the first transistor Q1 ', make the efficient of regulator of reduction voltage 200 more improve.For example select the first transistor Q1 ' to be model SI4392DY (being made by Siliconix), its parasitic input capacitance is about 1350pF.And select the transistor littler to think the 3rd transistor Q3 than parasitic input capacitance 1350pF, for example be model 2N7002E (making) by Siliconix, its parasitic capacitance is about 30pF, so that when the first control signal Ctrl, 1 conducting, transistor Q3 is than the faster conducting of transistor Q1 '.

The regulator of reduction voltage that the above embodiment of the present invention disclosed, by with after the 3rd transistor AND gate capacitances in series, be parallel between the grid-source electrode of transistor seconds, to suppress when the first transistor conducting, the size that runs through voltage that produces in the gate terminal of transistor seconds, avoid running through the forward bias voltage drop of voltage ratio transistor seconds when also big, make two transistor Q1 ', Q2 ' while conducting and the situation of being burnt by the first direct voltage Vin.And make the efficient of regulator of reduction voltage 200 to improve.

In sum; though the present invention discloses as above with a preferred embodiment; yet it is not in order to limit the present invention; any person skilled in the art person; without departing from the spirit and scope of the present invention; when the variation that can do various equivalences or replacement, so protection scope of the present invention is when looking accompanying being as the criterion that the application's claim scope defined.

Claims

1. regulator of reduction voltage comprises:

One the first transistor, the drain electrode of this first transistor receive one first direct voltage, and the grid of this first transistor receives one first control signal, and the source electrode of the first transistor is coupled to a node;

One transistor seconds, the drain electrode of this transistor seconds couples this node, and the grid of this transistor seconds receives one second control signal, and the source electrode of this transistor seconds is coupled to a fixed voltage;

One filter circuit, itself and this node electrically connect is also exported one second direct voltage;

One electric capacity; And

One switch, it has one first end, one second end and a control end, and this first end electrically connects via the grid of this electric capacity and this transistor seconds, and the source electrode of this second end and this transistor seconds electrically connects, and this control end receives this first control signal;

Wherein, the switch speed of this switch is greater than the switch speed of this first transistor;

Wherein, when this first control signal activation, this the first transistor and this switch conduction, this electric capacity is parallel to the grid and the source electrode two ends of this transistor seconds, and the capacitance of this electric capacity is enough to make this first direct voltage to run through the critical voltage that voltage is lower than this transistor seconds in what the grid of this transistor seconds produced.

2. regulator of reduction voltage as claimed in claim 1, it is characterized in that, this switch is one the 3rd transistor, and the 3rd transistorized parasitic input capacitance makes the switch speed of the 3rd transistorized switch speed greater than this first transistor less than the parasitic input capacitance of this first transistor.

3. regulator of reduction voltage as claimed in claim 1 is characterized in that, this regulator of reduction voltage is a synchronous regulator of reduction voltage.