CN100364230C - Synchronous Enable Conditional Precharge CMOS Flip-Flops - Google Patents

Abstract

The present invention relates to a synchronous enabled type condition precharging CMOS trigger which belongs to the technical field of a D trigger. The present invention is characterized in that the synchronous enabled type condition precharging CMOS trigger is formed by once connecting a synchronous enabled circuit, a first stage latch and a second stage latch in series, wherein the synchronous enabled circuit comprises two CMOS transmission gates, the input of the synchronous enabled circuit is respectively an input data signal and an output signal in the second stage latch, the two transmission gates are respectively controlled by a synchronous enabled signal and an inversion signal to output synchronous enabled input data signals to the first stage latch, the first stage latch uses a condition precharging circuit controlled by the input data signal to reduce circuit power consumption, the second stage latch is composed of two single-phase clock latches with the same circuit parameters, and the rising edge and the falling edge of the output end of the second stage latch is symmetrical in time delay. A holding circuit is connected to the output ends of the two latches for maintaining and determining electric potential when a clock signal is low.

Description

Synchronous Enable Conditional Precharge CMOS Flip-Flops

technical field

The presented circuit is part of the series "Conditional Precharged CMOS Flip-Flops". It is characterized by "synchronous scanning" control. The technical field of direct application is the design of low-power flip-flop circuits.

Background technique

With the advancement of CMOS integrated circuit manufacturing technology, the scale and complexity of integrated circuits are increasing day by day, and the power consumption and heat dissipation of integrated circuits have been paid more and more attention from industry and academia. Based on the current integrated circuit design style, in large-scale digital circuit systems, the energy consumed by the clock network accounts for a high proportion of the total energy consumption of the entire circuit; among them, in the working state of the circuit, the energy consumed in the clock interconnection network and timing The energy of the circuit unit (flip-flop: Flip-Flop) has become an important source of energy consumption of the clock network, and the power consumption ratio of the two has an increasing trend (see the literature David E. Duarte, N. Vijaykrishnan, and Mary Jane Irwin , "A Clock Power Model to Evaluate Impact of Architectural and Technology Optimizations", IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol.10, no.6, pp.844-855, December 2002.).

The power consumption sources of CMOS integrated circuits mainly include dynamic power consumption, static power consumption, short-circuit current power consumption and leakage current power consumption. Among them, dynamic power consumption accounts for the main part. Under certain circuit performance constraints, the dynamic power consumption P _Dynamic of a node in a CMOS integrated circuit is a function of the load capacitance _CL of the node, the power supply voltage V _DD and the voltage swing V _Swing of the node, namely:

P _Dynamic = C _L V _DD V _Swing fα (1)

Among them, f is the operating frequency of the circuit, and α is the signal activity. It can be seen from formula (1) that reducing α, _CL , V _DD and V _Swing can reduce the dynamic power consumption of the circuit. Different from the data signal network, the clock signal network has the characteristics of large interconnect parasitic capacitance and high signal activity. By reducing the voltage signal swing V _Swing of the clock signal network, the clock interconnection can be reduced under the condition of ensuring circuit performance. Energy expended on the wire. Flip-flop circuit cells are widely used in integrated circuit design. As shown in Figure 1 is a schematic diagram of the flip-flop circuit unit. As shown in Figure 2, the basic circuit structure of the traditional flip-flop circuit unit widely used in the design of the digital circuit standard cell library, the main feature of this circuit structure is that the circuit structure is relatively simple, but every time the clock signal flips will cause the circuit internal When the node is flipped, the power consumption of the circuit is relatively large. H.Kawaguchi proposed a flip-flop circuit RCSFF that can be driven by a low-voltage swing clock signal (see H.Kawaguchi and T.Sakurai: "A Reduced Clock-Swing Flip-Flop (RCSFF) for 63% Power Reduction", IEEE JOURNAL OF SOLID-STATECIRCUITS, VOL.33, NO.5, MAY 1998, PP.807-811.), but the problem with this circuit is that every time the clock signal is low, it will precharge the internal node conditions of the circuit, will cause additional energy consumption. On the basis of the RCSFF circuit, SALATCH_P.Zhang proposed a flip-flop circuit SAFF_CP driven by a low voltage swing clock signal with a conditional precharge structure (see literature Y.Zhang, H.Yang, and H.Wang, "Low clock -swing conditional-precharge flip-flop for more than 30% power reduction," Electron. Lett., vol.36, no.9, pp.785-786, Apr.2000.), as shown in Figure 3. The biggest feature of this kind of flip-flop circuit is that if the flip-flop circuit input remains unchanged when the clock signal is low, the circuit will not precharge its internal node conditions during the low clock signal period. The adoption of this technology greatly reduces the power consumption of the flip-flop circuit itself. However, the problem with the SAFF_CP circuit is that since the output latch circuit adopts a cross-coupled NAND2 (NAND2: two-input NAND gate) structure, the delay of the rising edge and falling edge of the output of the flip-flop circuit will be extremely different. Symmetry, which brings potential problems to the use of circuit cells. Figure 4 shows the cross-coupled NAND2 latch circuit. Take the output terminal of V _outa as an example, when V _ina is at low level '0' and at the same time V _inb is at high level '1', the signal passes through the NAND gate NAND2_a, causing V _outa to generate a rising edge flip; when V _ina is High level '1', while V _inb is low level '0', V _outa will not flip immediately, but will wait until V _outb first flips to high level '1', and then V _outa will be generated Falling edge toggles. It can be seen that for the SAFF_CP circuit that uses a cross-coupled NAND2 latch circuit as the output terminal, the output terminal signal will always have a delay of one gate more than the rising edge inversion when the falling edge of the output signal occurs, thus causing the rising edge delay of the circuit and The problem of asymmetrical falling edge delay.

On the basis of the existing conditional pre-charge structure flip-flop circuit, SAFF_CP circuit, there is a conditional pre-charge CMOS flip-flop SAFF_CP_BRF with a symmetrical delay and a small settling time when the output signal falls and rises, such as Figure 5 shows.

Invention content:

An application circuit is proposed based on the existing SAFF_CP_BRF circuit: a synchronous enable conditional precharge CMOS flip-flop SAFF_CP_BRF_EC, as shown in Figure 6.

The present invention is characterized in that: the CMOS flip-flop is a rising edge flip-flop, including a first-stage latch, a second-stage latch, and a synchronous enabling circuit, wherein:

The first-stage latch includes a first OR logic circuit, a second OR logic circuit, a first PMOS transistor MP1, a second PMOS transistor MP2, a third PMOS transistor MP3, a fourth PMOS transistor MP4, and a fourth NMOS transistor MN4, The fifth NMOS transistor MN5, the second NMOS transistor MN2, the third NMOS transistor MN3, the first NMOS transistor MN1, and the first inverter φ ₁ , wherein:

The first OR logic circuit includes an eighth NMOS transistor MN8 and a ninth NMOS transistor MN9, the drains of the eighth NMOS transistor MN8 and the ninth NMOS transistor MN9 are connected, the substrates are connected and grounded, and the source of the eighth NMOS transistor MN8 The electrode and the gate are connected to the first data signal VD, the gate of the ninth NMOS transistor MN9 is connected to the second data signal VDb, the second data signal VDb is the inversion signal of the first data signal VD, and the ninth NMOS transistor MN9 The source of the tube MN9 is connected to the clock signal CLK,

The second OR logic circuit includes the tenth NMOS transistor MN10 and the eleventh NMOS transistor MN11, the drains of the tenth NMOS transistor MN10 and the eleventh NMOS transistor MN11 are connected, the substrates are connected and grounded, and the tenth NMOS transistor MN10 The source and gate of the eleventh NMOS transistor MN11 are connected to the second data signal VDb, the gate of the eleventh NMOS transistor MN11 is connected to the first data signal VD, the source of the eleventh NMOS transistor MN11 is connected to the clock signal CLK,

The first PMOS transistor MP1, the clock signal CLK and the second data signal VDb in the first OR logic circuit form OR logic, and are connected to the gate of the first PMOS transistor MP1 through the drain of the ninth NMOS transistor MN9 , the source of the first PMOS transistor MP1 is connected to the substrate and then connected to the power supply voltage VDD,

The second PMOS transistor MP2, the clock signal CLK and the first data signal VD in the second OR logic circuit form an OR logic, and pass through the drain of the eleventh NMOS transistor MN11 and the drain of the second PMOS transistor MP2 The gate is connected, the source of the second PMOS transistor MP2 is connected to the substrate and then connected to the power supply voltage VDD,

The third PMOS transistor MP3, the source of the third PMOS transistor MP3 is connected to the power supply voltage VDD after being connected to the substrate,

The fourth PMOS transistor MP4, the source of the fourth PMOS transistor MP4 is connected to the power supply voltage VDD after being connected to the substrate,

A fourth NMOS transistor MN4, the source of the fourth NMOS transistor MN4 is simultaneously connected to the drains of the first PMOS transistor MP1 and the third PMOS transistor MP3, and the gate of the fourth PMOS transistor MP4 to form a first node SALATCH_N, The gate of the fourth NMOS transistor MN4 is connected to the gate of the third PMOS transistor MP3, the drains of the fourth PMOS transistor MP4 and the second PMOS transistor MP2 to form a second node SALATCH_P. The fourth NMOS transistor MN4 the substrate grounded,

The fifth NMOS transistor MN5, the source of the fifth NMOS transistor MN5 is connected to the second node SALATCH_P, the gate of the fifth NMOS transistor MN5 is connected to the first node SALATCH_N, the lining of the fifth NMOS transistor MN5 bottom ground,

The second NMOS transistor MN2, the source of the second NMOS transistor MN2 is connected to the drain of the fourth NMOS transistor MN4, the substrate of the second NMOS transistor MN2 is grounded,

The third NMOS transistor MN3, the source of the third NMOS transistor MN3 is connected to the drain of the fifth NMOS transistor MN5, the substrate of the third NMOS transistor MN3 is grounded,

The first NMOS transistor MN1, the source of the first NMOS transistor MN1 is connected to the drains of the second NMOS transistor MN2 and the third NMOS transistor MN3 at the same time, the gate of the first NMOS transistor MN1 is connected to the clock signal CLK, and the gate of the first NMOS transistor MN1 is connected to the clock signal CLK. The substrate of the first NMOS transistor MN1 is grounded,

The first inverter φ ₁ , the input terminal of the first inverter φ ₁ is connected to the gate of the second NMOS transistor MN2, and the output terminal of the first inverter φ ₁ is connected to the gate of the third NMOS transistor MN2 The grid of the tube MN3 is connected;

The second-stage latch includes the seventh PMOS transistor MP0_1, the eighth PMOS transistor MP0_2, the fourteenth NMOS transistor MN1_1, the fifteenth NMOS transistor MN1_2, the second inverter φ ₂ and the third inverter φ ₃ , The twelfth NMOS transistor MN0_1, the thirteenth NMOS transistor MN0_2, the fourth inverter φ ₄ , and the fifth inverter φ ₅ , wherein:

The seventh PMOS transistor MP0_1, the source of the seventh PMOS transistor MP0_1 is connected to the substrate and then connected to the power supply voltage VDD, the gate of the seventh PMOS transistor MP0_1 is connected to the second node SALATCH_P,

The eighth PMOS transistor MP0_2, the source of the eighth PMOS transistor MP0_2 is connected to the substrate and then connected to the power supply voltage VDD, the gate of the eighth PMOS transistor MP0_2 is connected to the first node SALATCH_N,

The fourteenth NMOS transistor MN1_1, the gate of the fourteenth NMOS transistor MN1_1 is connected to the second node SALATCH_P, the substrate of the fourteenth NMOS transistor MN1_1 is grounded,

The fifteenth NMOS transistor MN1_2, the gate of the fifteenth NMOS transistor MN1_2 is connected to the first node SALATCH_N, the substrate of the fifteenth NMOS transistor MN1_2 is grounded,

The second inverter φ ₂ and the third inverter φ ₃ , the input terminal of the second inverter φ ₂ is connected to the output terminal of the third inverter φ ₃ and then simultaneously connected with the seventh PMOS The drain of the transistor MP0_1 and the source of the fourteenth NMOS transistor MN1_1 are connected to form the third node QI, and the output terminal of the second inverter _φ2 is connected to the input terminal of the third inverter φ3 and then connected to the input terminal of the third inverter _φ3 . The drain of the eighth PMOS transistor MP0_2 and the source of the fifteenth NMOS transistor MN1_2 are connected to form a fourth node QNI,

The twelfth NMOS transistor MN0_1, the drain of the twelfth NMOS transistor MN0_1 is grounded after being connected to the substrate, the gate of the twelfth NMOS transistor MN0_1 is connected to the clock signal CLK, and the source is connected to the fourteenth NMOS transistor Drain of MN1_1,

The thirteenth NMOS transistor MN0_2, the drain of the thirteenth MOS transistor MN0_2 is grounded after being connected to the substrate, the gate is connected to the clock signal CLK, and the source is connected to the drain of the fifteenth NMOS transistor MN1_2,

A fourth inverter φ ₄ , the input terminal of the fourth inverter φ ₄ is connected to the fourth node QNI, and the output is the first output signal Qb of the CMOS flip-flop,

A fifth inverter φ ₅ , the input terminal of the fifth inverter φ ₅ is connected to the third node QI, and the output is the second output signal Q of the CMOS flip-flop;

A synchronous enabling circuit, comprising a zeroth inverter φ ₀ , a first CMOS transmission gate, and a second CMOS transmission gate, wherein:

The zeroth inverter φ ₀ , the input terminal of the zeroth inverter φ ₀ is connected to the synchronous enable signal E, and the output signal is the third data signal EN,

The first CMOS transmission gate includes two fifth PMOS transistor MPV and sixth NMOS transistor MNN connected in parallel, the sources of the fifth PMOS transistor MPV and the sixth NMOS transistor MNN are connected and then connected to the input data signal D, the The fifth PMOS transistor MPV is connected to the drain of the sixth NMOS transistor MNN and then connected to the gate of the second NMOS transistor MN2 of the first-stage latch, and the substrate of the fifth PMOS transistor MPV is connected to the power supply voltage VDD, The substrate of the sixth NMOS transistor MNN is grounded,

The second CMOS transmission gate includes two parallel-connected sixth PMOS transistor MPV' and seventh NMOS transistor MNN', the drains of the sixth PMOS transistor MPV' and the seventh NMOS transistor MNN' are connected in parallel and then connected to the first The gate of the second NMOS transistor MN2 of the first-level latch, the sources of the sixth PMOS transistor MPV' and the seventh NMOS transistor MNN' are connected in parallel and then connected to the fourth node QNI in the second-level latch , the synchronization enable signal E is connected to the gates of the sixth NMOS transistor MNN and the sixth PMOS transistor MPV' at the same time, and the third data signal EN is respectively connected to the fifth PMOS transistor MPV and the seventh NMOS transistor MNN' The gate of the sixth PMOS transistor MPV' is connected to the power supply voltage VDD, and the substrate of the seventh NMOS transistor MNN' is connected to the ground.

The beneficial effect of the invention is that the flip-flop with the same function as that in the GSMC15 library can save more than 30% of power consumption. The circuit delay characteristic is equal to or better than GSMC15. The circuit technology proposed by GSMC15 is very suitable as a digital circuit standard unit and applied in low power consumption integrated circuit design.

Description of drawings

Figure 1. Schematic diagram of the flip-flop circuit unit, D is the data signal input end, CK is the clock signal input end, E is the synchronization enable control signal input end, Q and QN are complementary signal output ends;

Figure 2. (a) Circuit structure diagram of FFEDHD1X flip-flop circuit unit FFEDHD1X with synchronous enable type complementary output and rising edge trigger in GSMC’s 0.15um process digital standard cell library; (b) signal generation circuit

Figure 3. SAFF_CP flip-flop circuit structure diagram;

Figure 4. Cross-coupled NAND2 latch circuit structure diagram;

Figure 5. SAFF_CP_BRF trigger circuit structure diagram;

Fig. 6. SAFF_CP_BRF_EC trigger circuit structural diagram that the present invention proposes;

Figure 7. SAFF_CP_BRF_EDCR trigger circuit structure diagram;

Figure 8. A diagram illustrating the definition of trigger static delay and total delay.

Detailed ways:

The technical solution of the present invention to solve the technical problem is: the synchronous enable type conditional precharge flip-flop SAFF_CP_BRF_EC proposed by the present invention, as shown in FIG. 6 . The SAFF_CP_BRF_EC flip-flop uses conditional prefill technology to reduce the power consumption of the flip-flop circuit itself, and since the complementary output terminals of the first-stage latch are respectively connected to two independent single-clock phase latches with the same circuit parameters, It can be guaranteed that both complementary output terminals Q and _Qn of the SAFF_CP_BRF_EC flip-flop can realize symmetrical rising edge delay and falling edge delay. Compared with the SAFF_CP flip-flop circuit, since the NMOS transistor MN6 is removed from the SAFF_CP_BRF_EC flip-flop, the settling time characteristics of the circuit can be greatly improved, the dynamic power consumption is reduced, and the circuit structure is simpler. In addition, an additional high-voltage power supply line is reduced. V _well (substrate bias is provided for the PMOS transistors MP1 and MP2, V _well > V _DD ), which is more conducive to the use and design of the circuit.

The working principle of the SAFF_CP_BRF_EC flip-flop is: the synchronization enable signal E and its inversion signal En control two CMOS transmission gates, and one transmission gate sends the data D to the output terminal when E=1, and the output remains when E=0 Two-state; another transmission sends the same QNI as the Q waveform to the output terminal when E=0, and the output remains two-state when E=1. The output terminals of the two transmissions are connected together as a post-stage trigger The data input terminal VD of the device. In this way, when E=1, the input signal of the rear-stage flip-flop is data D, and the output follows the data D jump under clock control. When E=0, the input signal of the rear-stage flip-flop becomes QNI (in phase with Q ), which realizes "synchronous enable". The clock signals CLK and VD form an OR logic and are connected to the gate of the PMOS transistor MP1, while the clock signals CLK and VDb (the inversion signal of VD) form an OR logic and are connected to the PMOS gate of MP2. When CLK is at a high level, both MP1 and MP2 are turned off, and the NMOS transistor MN1 is turned on. If VD is at a high level at this time, the node SALATCH_N is discharged, and the node SALATCH_P remains at a high level. At this time, the second-stage latch is driven by the nodes SALATCH_N and SALATCH_P, and since CLK is high level, NMOS transistors MN4 and MN5 are turned on, so that the complementary output terminal Q of the flip-flop is high level, and _Qb is low level. When CLK is at low level, if the input signal VD is still at high level, MP1 remains off, and the node SALATCH_N will not be conditionally precharged; at this time, for the second-stage latch, since CLK is at low level , MN4 and MN5 are cut off, and the complementary output signal of the flip-flop will also be maintained. When CLK is at low level, if the input signal VD flips to low level, MP1 is turned on, and the SALATCH_N node is conditionally precharged; and when the next rising edge of the clock arrives, the node SALATCH_P is discharged, and the node SALATCH_N remains at a high level and Drive the second-stage latch so that the complementary output terminal Q of the flip-flop is at low level, and Q _n is at high level. The output nodes SALATCH_N and SALATCH_P of the first-stage latch are respectively connected to two independent single-clock phase latches with the same circuit parameters. This connection method can not only ensure that when CLK is low, the flip-flop The complementary output terminal can keep the signal level unchanged; at the same time, it can ensure that both the complementary output terminals Q and Q _n of the SAFF_CP_BRF_EC flip-flop can realize symmetrical rising edge delay and falling edge delay.

The essential technical features of the present invention are: firstly, it has reliable synchronous enabling control Enable. Secondly, the flip-flop circuit uses the conditional precharge control circuit controlled by the input data signal VD to complete the conditional precharge process of the internal nodes of the circuit, which reduces the power consumption of the flip-flop itself. The conditional precharge process of the first-stage latch cooperates with the second-stage latch to ensure that the complementary output of the flip-flop can maintain the signal level when the circuit is at low level and does not conditionally precharge the SALATCH_N or SALATCH_P node. constant. Again, the output nodes SALATCH_N and SALATCH_P of the first-stage latch are respectively connected to two independent single-clock phase latches with the same circuit parameters. This connection method can ensure that the complementary output terminals Q and Both Q _b can realize symmetrical rising and falling edge delays. In addition, compared with the basic flip-flop SAFF_CP, since the NMOS transistor MN6 is removed from the SAFF_CP_BRF_EC flip-flop, the settling time characteristics of the circuit can be greatly improved, and the dynamic power consumption is also reduced. At the same time, the circuit structure is simpler and an additional high-voltage power supply is reduced. Line V _well (provides substrate bias for PMOS transistors MP1 and MP2, V _well > V _DD ), which is more conducive to the use and design of the circuit, and a potential holding circuit (composed of φ ₂ and φ ₃ ) is added at the output stage.

In order to compare the performance of the SAFF_CP_BRF_EC flip-flop proposed by the present invention with that of the FFEDHD1X flip-flop with the same function in the GSMC15 library, a post-simulation comparative analysis of the two circuit structures was carried out using the circuit simulation tool HSPICE. Table 1 shows the comparison of the simulated dynamic power consumption and circuit area data after the two flip-flops. In the dynamic power consumption simulation of the circuit, the clock signal input CLK is 100MHz, a 50% duty ratio square wave signal (0V-1.5V), and the data signal input D is 20MHz, a 50% duty ratio square wave signal (0V-1.5V). The data signal has a delay of 1ns relative to the clock signal, and the edge width of all input signals is 0.104ns. "Q load/Qn empty" means: the output terminal Q of the flip-flop is connected to a 20fF capacitive load, and the Qn terminal is suspended. The units of dynamic power consumption and circuit area data are microwatts (uW) and micrometers*micrometers (um*um), respectively.

Table 1 Simulation dynamic power consumption and circuit area comparison after flip-flop

Dynamic power consumption (uW) Circuit area (um*um) Q load/Qn empty Qn load/Q empty FFEDHD1X 6.283 6.313 12.30*4.32 SAFF_CP_BRF_EC 4.050 4.028 11.76*4.32

Table 2 shows the comparison of the total delay TotalDelay of the simulation after the two flip-flops.

As shown in Figure 8: D-CK delay vs CK-Q delay curve, as the D-CK delay increases, the CK-Q delay tends to a stable value - static delay (TstaticDelay) , define 105% of the static delay as D0, and the corresponding D-CK delay is defined as Tmp, and D0+Tmp is defined as the total delay (TotalDelay)

The two flip-flop circuits adopt the same circuit configuration, the input signal conversion time is 0.05ns, and both output terminals of the circuit are connected with a load of 20fF. RISE and FALL represent the rising edge of the output signal and the falling edge of the output signal respectively; the unit of delay data is nanosecond (ps).

Table 2 The total delay of simulation after FFEDHD1X trigger & SAFF_CP_BRF_EC trigger (TotalDelay)

Edge Tmp D0 Total Delay FFEDHD1X RISE 75.7 311 386.7 FALL 131 315 446 SAFF_CP_BRF_EC RISE 163 221.5 384.5 FALL 192 256 448

Table 3 and Table 3B show the relationship between the simulation static delay (TstaticDelay) and the circuit load after the two flip-flops. The two flip-flop circuits adopt the same circuit configuration, the input signal transition time is 0.104ns, and the unit load is 4fF. Compared with the FFEDHD1X flip-flop in the GSMC15 library, the SAFF_CP_BRF_EC trigger circuit has basically the same circuit delay and the rising edge delay is basically the same as the falling edge delay, and the metastable effect is not considered here. tQ and tQ _n indicate the delay of the non-inverting output terminal and the inverting output terminal respectively; RISE and FALL respectively indicate the rising edge of the output signal and the falling edge of the output signal; the delay data unit is nanosecond (ps).

Table 3A The relationship between static delay and load after FFEDHD1X trigger simulation

Fan-out load/unit load 4 8 16 32 64 Transition edge RISE FALL RISE FALL RISE FALL RISE FALL RISE FALL tQ(ns) 277 284 351 345 495 449 782 644 1356 1031 tQ_n(ns) 369 348 438 399 580 497 867 690 1440 1077

Table 3B Simulation static delay and load relationship after SAFF_CP_BRF_EC trigger

Fan-out load/unit load 4 8 16 32 64 Transition edge RISE FALL RISE FALL RISE FALL RISE FALL RISE FALL tQ(ns) 201 239 274 287 417 383 704 576 1278 963 tQ_n(ns) 224 268 295 319 442 417 728 610 1302 996

Table 4A and Table 4B show the relationship between the simulation delay and the input signal transition time after the two flip-flops. The two flip-flop circuits adopt the same circuit configuration, the unit conversion time of the input signal is 0.05ns, and the circuit load is 20fF. Compared with the FFEDHD1X flip-flop in the GSMC15 library, the SAFF_CP_BRF_EC trigger circuit has basically the same circuit delay and the rising edge delay is basically the same as the falling edge delay, and the metastable effect is not considered here. tQ and tQ _n indicate the delay of the non-inverting output terminal and the inverting output terminal respectively; RISE and FALL respectively indicate the rising edge of the output signal and the falling edge of the output signal; the delay data unit is nanosecond (ns).

Table 4A Relationship between simulation delay and conversion time after FFEDHD1X trigger

Circuit load = 20fF, unit conversion time = 0.05ns

Input conversion time/unit conversion time 1 5 10 15 20 Transition edge RISE FALL RISE FALL RISE FALL RISE FALL RISE FALL tQ(ns) 296 300 334 334 365 371 388 393 408 411 tQ_n(ns) 386 361 415 399 453 431 475 455 496 474

Table 4B Relationship between simulation delay and conversion time after SAFF_CP_BRF_EC trigger

Input conversion time/unit conversion time 1 5 10 15 20 Transition edge RISE FALL RISE FALL RISE FALL RISE FALL RISE FALL tQ(ns) 211 244 242 263 273 281 297 292 311 299 tQ_n(ns) 242 281 270 298 296 313 316 325 329 332

Claims (1)

1. synchronously just can the type condition prechargig CMOS trigger, it is characterized in that described CMOS trigger is the rising edge trigger, contains first order latch, second level latch, and synchronous enabled circuit, wherein:

First order latch contains first or logical circuit, second or logical circuit, the one PMOS manages (MP1), the 2nd PMOS manages (MP2), and the 3rd PMOS manages (MP3), and the 4th PMOS manages (MP4), the 4th NMOS manages (MN4), the 5th NMOS manages (MN5), and the 2nd NMOS manages (MN2), and the 3rd NMOS manages (MN3), the one NMOS manages (MN1), the first inverter (φ ₁), wherein:

First or logical circuit, contain the 8th NMOS pipe, (MN8) and the 9th NMOS pipe, (MN9), the 8th NMOS pipe, (MN8) and the 9th NMOS pipe, (MN9) drain electrode links to each other, ground connection after substrate links to each other, the 8th NMOS pipe, (MN8) source electrode and grid connect first data-signal, (VD), the 9th NMOS pipe, (MN9) grid connects second data-signal, (VDb), this second data-signal, (VDb) be described first data-signal, (VD) inversion signal, the 9th NMOS pipe, (MN9) source electrode connects clock signal, (CLK)

Second or logical circuit, contain the tenth NMOS pipe (MN10) and the 11 NMOS pipe (MN11), the tenth NMOS pipe (MN10) links to each other with the drain electrode of the 11 NMOS pipe (MN11), ground connection after substrate links to each other, the source electrode and the grid of the tenth NMOS pipe (MN10) connect second data-signal (VDb), the grid of the 11 NMOS pipe (MN11) connects first data-signal (VD), and the source electrode of the 11 NMOS pipe (MN11) connects clock signal (CLK)

The one PMOS manages (MP1), described first or logical circuit in clock signal (CLK) and second data-signal (VDb) is formed or logic, and link to each other with the grid that a described PMOS manages (MP1) through the drain electrode of the 9th NMOS pipe (MN9), the source electrode of the one PMOS pipe (MP1) with connect supply voltage (VDD) after substrate links to each other

The 2nd PMOS manages (MP2), described second or logical circuit in clock signal (CLK) and first data-signal (VD) is formed or logic, and the drain electrode of described the 11 NMOS pipe of process (MN11) links to each other with the grid that described the 2nd PMOS manages (MP2), the source electrode of the 2nd PMOS pipe (MP2) with connect supply voltage (VDD) after substrate links to each other

The 3rd PMOS manages (MP3), the source electrode of the 3rd PMOS pipe (MP3) with connect supply voltage (VDD) after substrate links to each other,

The 4th PMOS manages (MP4), the source electrode of the 4th PMOS pipe (MP4) with connect supply voltage (VDD) after substrate links to each other,

The 4th NMOS manages (MN4), the source electrode while of the 4th NMOS pipe (MN4) and the drain electrode of described PMOS pipe (MP1) and the 3rd PMOS pipe (MP3), after linking to each other, the grid of the 4th PMOS pipe (MP4) forms first node (SALATCH_N), the grid while of the 4th NMOS pipe (MN4) and the grid of described the 3rd PMOS pipe (MP3), after linking to each other, the drain electrode of the 4th PMOS pipe (MP4) and the 2nd PMOS pipe (MP2) forms Section Point (SALATCH_P), the substrate ground connection of the 4th NMOS pipe (MN4)

The 5th NMOS manages (MN5), and the source electrode of the 5th NMOS pipe (MN5) links to each other with described Section Point (SALATCH_P), and the grid of the 5th NMOS pipe (MN5) links to each other with described first node (SALATCH_N), the substrate ground connection of the 5th NMOS pipe (MN5),

The 2nd NMOS manages (MN2), and the source electrode of the 2nd NMOS pipe (MN2) links to each other with the drain electrode that described the 4th NMOS manages (MN4), the substrate ground connection of the 2nd NMOS pipe (MN2),

The 3rd NMOS manages (MN3), and the source electrode of the 3rd NMOS pipe (MN3) links to each other with the drain electrode that described the 5th NMOS manages (MN5), the substrate ground connection of the 3rd NMOS pipe (MN3),

The one NMOS manages (MN1), drain electrode with the 3rd NMOS pipe (MN3) links to each other the source electrode of the one NMOS pipe (MN1) with described the 2nd NMOS pipe (MN2) simultaneously, the grid of the one NMOS pipe (MN1) connects clock signal (CLK), the substrate ground connection of NMOS pipe (MN1)

First inverter (the φ ₁), this first inverter (φ ₁) input link to each other this first inverter (φ with the grid that described the 2nd NMOS manages (MN2) ₁) output be to link to each other with the grid of described the 3rd NMOS pipe (MN3);

Second level latch contains the 7th PMOS pipe (MP0_1), and the 8th PMOS manages (MP0_2), and the 14 NMOS manages (MN1_1), and the 15 NMOS manages (MN1_2), the second inverter (φ ₂) and the 3rd inverter (φ ₃), the 12 NMOS manages (MN0V_1), and the 13 NMOS manages (MN0_2), the 4th inverter (φ ₄) and the 5th inverter (φ ₅), wherein:

The 7th PMOS manages (MP0_1), the source electrode of the 7th PMOS pipe (MP0_1) with connect supply voltage (VDD) after substrate links to each other, the grid that the 7th PMOS manages (MP0_1) connects described Section Point (SALATCH_P),

The 8th PMOS manages (MP0_2), the source electrode of the 8th PMOS pipe (MP0_2) with connect supply voltage (VDD) after substrate links to each other, the grid that the 8th PMOS manages (MP0_2) connects described first node (SALATCH_N),

The 14 NMOS manages (MN1_1), and the grid of the 14 NMOS pipe (MN1_1) connects described Section Point (SALATCH_P), the substrate ground connection of the 14 NMOS pipe (MN1_1),

The 15 NMOS manages (MN1_2), and the grid of the 15 NMOS pipe (MN1_2) connects described first node (SALATCH_N), the substrate ground connection of the 15 NMOS pipe (MN1_2),

Second inverter (the φ ₂) and the 3rd inverter (φ ₃), this second inverter (φ ₂) input with the 3rd inverter (φ ₃) output link to each other with the drain electrode of described the 7th PMOS pipe (MP0_1) and the source electrode of the 14 NMOS pipe (MN1_1) simultaneously again after linking to each other, form the 3rd node (QI), the second inverter (φ ₂) output with the 3rd inverter (φ ₃) input link to each other with the drain electrode of described the 8th PMOS pipe (MP0_2) and the source electrode of the 15 NMOS pipe (MN1_2) again after linking to each other, form the 4th node (QNI),

The 12 NMOS manages (MN0_1), and the drain electrode of the 12 NMOS pipe (MN0_1) is the back ground connection that links to each other with substrate, and the grid of the 12 NMOS pipe (MN0_1) connects clock signal (CLK), and source electrode connects the drain electrode of described the 14 NMOS pipe (MN1_1),

The 13 NMOS manages (MN0_2), and the drain electrode of the 13 NMOS pipe (MN0_2) is the back ground connection that links to each other with substrate, and grid connects clock signal (CLK), and source electrode connects the drain electrode of described the 15 NMOS pipe (MN1_2),

The 4th inverter (φ ₄), the 4th inverter (φ ₄) input link to each other with described the 4th node (QNI), be output as first output signal (Qb) of described CMOS trigger,

The 5th inverter (φ ₅), the 5th inverter (φ ₅) input link to each other with described the 3rd node (QI), be output as second output signal (Q) of described CMOS trigger;

Synchronous enabled circuit contains invert on zero device (φ ₀), first cmos transmission gate, and second cmos transmission gate, wherein:

Invert on zero device (φ ₀), this invert on zero device (φ ₀) input link to each other with synchronous enabled signal (E), output signal is the 3rd data-signal (EN),

First cmos transmission gate, contain two the 5th PMOS pipes parallel with one another, (MPV) and the 6th NMOS pipe, (MNN), described the 5th PMOS pipe, (MPV) and the 6th NMOS pipe, (MNN) source electrode connects input data signal after linking to each other, (D), described the 5th PMOS pipe, (MPV) and the 6th NMOS pipe, (MNN) after linking to each other, drain electrode connects the 2nd NMOS pipe of described first order latch, (MN2) grid, described the 5th PMOS pipe, (MPV) substrate connects supply voltage, (VDD), the 6th NMOS pipe, (MNN) substrate ground connection

Second cmos transmission gate, contain two the 6th PMOS parallel with one another pipes (MPV ') and the 7th NMOS and manage (MNN '), the 2nd NMOS that connects described first order latch after the drain electrode parallel connection of described the 6th PMOS pipe (MPV ') and the 7th NMOS pipe (MNN ') manages the grid of (MN2), connect interior the 4th node (QNI) of described second level latch after the source electrode parallel connection of described the 6th PMOS pipe (MPV ') and the 7th NMOS pipe (MNN '), synchronous enabled signal (E) is managed simultaneously (MPV ') with described the 6th NMOS pipe (MNN) and the 6th PMOS grid links to each other, described the 3rd data-signal (EN) connects described the 5th PMOS pipe (MPV) respectively and the 7th NMOS manages the grid of (MNN '), the substrate of described the 6th PMOS pipe (MPV ') connects supply voltage (VDD), the substrate ground connection of the 7th NMOS pipe (MNN ').

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