CN100357905C

CN100357905C - Detection method for failure of address bus

Info

Publication number: CN100357905C
Application number: CNB2004100695863A
Authority: CN
Inventors: 黄春明
Original assignee: Huawei Technologies Co Ltd
Current assignee: Huawei Technologies Co Ltd
Priority date: 2004-07-20
Filing date: 2004-07-20
Publication date: 2007-12-26
Anticipated expiration: 2024-07-20
Also published as: CN1725190A

Abstract

The present invention discloses a detection method for the failure of an address bus. The method comprises the following steps: step a, a link address bus is connected to the signal input end of a register; step b, a control unit sends reading or writing signals to a detected functional unit, and the register is triggered; step c, the control unit reads data in the register and compares the data with the address of the detected functional unit; step d, if the data and the address of the detected functional unit are different, the address bus of the functional unit has a failure. The method of the present invention can effectively detect the address bus of each functional unit, and can avoid apparatus accidents.

Description

A kind of fault detection method of address bus

Technical field

The present invention relates to the detection technique of the electronics or the communications field, relate in particular to a kind of fault detection method of address bus.

Background technology

For the reliability that improves electronic product and avoid accident to take place, the fault detect that electronic product may exist need be come out.Usually, after electronic product powers on, at first to carry out self check to total system.Generally (control module is meant the functional module that includes CPU, and it can be that a chip also can be a veneer by the CPU of system or control module in the product self check.The certain software of its general operation is finished all or part of function that equipment need be finished.) (functional unit is meant controlled unit controls, finishes the unit of certain function to its external function unit.It can be one or several chip, also can be a veneer.) check, comprise storer and functional chip etc. substantially.This power-on self-test is whether detect control module normal with the communication of other functional units, just, guarantees the working properly of the essential address bus of communication, data bus, control bus.

For data bus and control bus, general if guarantee data that write and the data consistent of reading just can the judgment data bus and control bus be correct.

For address bus, because address information is to be issued the individual event output information of functional unit by control module, cause control module to operate wrong address even therefore damage or process reasons such as causing network open loop at chip pin, control module also is difficult to find the existence of its mistake.Therefore, how effectively whether the address bus of measuring ability unit is working properly, is the problem that industry need be solved always.Yet, also do not have at present preferably means come the address bus of measuring ability unit whether working properly.

Summary of the invention

The invention provides a kind of detection method of address bus fault.

The fault detection method of address bus of the present invention may further comprise the steps:

A: the signal input part of link address bus and register;

B: control module sends to detected functional unit and reads or writes signal, and trigger register latchs the current address bus message;

C: control module read the current address bus message that latchs in the register and with the correct address bus message of detected functional unit relatively;

D:, then judge the address bus fault of this detected functional unit if both are inequality.

Described step c also comprises, after control module reads the current address bus message that latchs in the register, makes the current address bus message that latchs in the register be updated to the address of register.

Described method further comprises: control module judges whether to detect the address bus of other functional unit, if then go to step b, otherwise finish detection.

Among the described step b, the concrete grammar of trigger register is: the reading and writing by control module or its composite signal are as the trigger pip of register.

Among the described step c, control module reads the current address bus message that latchs in the register and sends read signal by control module to register and come this register of gating.

Among the described step c, it is to come this register of gating by the composite signal of address decoding and read signal that control module reads the current address bus message that latchs in the register.

Among the described step c, control module read the current address bus message that latchs in the register be by control module I the O control signal come this register of gating.

Described register is a d type flip flop.

Adopting method of the present invention can be effectively the address bus of each functional unit to be detected, whether wrong, thereby effectively avoid electronic equipment accident to occur if prejudging address bus.

Description of drawings

Fig. 1 is the annexation synoptic diagram of control module congenerous unit;

Fig. 2 is the present invention realizes address latch with register a connection diagram;

Fig. 3 is the inventive method process flow diagram.

Embodiment

The annexation of control module congenerous unit as shown in Figure 1, control module is specified the address location of its operation by address bus; Need mutual information by the data bus transmission; Finish the control of whole information interactive process by control bus.Address bus is the passage that control module is issued functional units addresses information, is unidirectional output information.Data bus is two-way, promptly from control module data is sent to functional unit, also can send the data of functional unit back to control module.Control bus is finished the reciprocal process of information by different control signals.

The address information that the present invention exports during by a register-stored control module last time information interaction, and when control module is visited this register with register in address stored information feed back to control module by data bus.

The signal of register connects as shown in Figure 2, among the figure with the register of d type flip flop OPADD information when realizing the storage control unit information interaction.The input end of this d type flip flop is connected with address bus, clock signal is to read or write and composite signal in the control module control bus, the address of output terminal Q end output latch, the ternary gating signal of the output of this d type flip flop can be the read signal that control module reads this register, also can be the composite signal of address decoding and read signal, can also be the I/O control signal of control module.

The specific implementation process of the inventive method is as follows: control module sends to detected functional unit and reads or writes signal, and d type flip flop reads or writes signal as its trigger pip with control module, and the information of address bus is latched.Owing to need constantly to read the operational order of CPU from internal memory when control module moves, for fear of the interference of control module reading command to d type flip flop, suggestion uses write signal as trigger pip.Detect in the implementation at this simultaneously, shield of the interference of other programs detecting by exclusively enjoying CPU.

Control module reads the address information that it latchs by the gating d type flip flop, and with the address information of detected functional unit relatively, if both differences illustrate that then detected functional units addresses bus breaks down.

After control module read the address information that this d type flip flop latchs, d type flip flop upgraded the address information of its latch data for this trigger self.

When the fault judgement of address bus, can take the traversal mode to read some address.At this moment preserved corresponding information in the d type flip flop.Subsequently, control module is read the content in the d type flip flop, and judges whether the content of this d type flip flop storage is identical with the address information of operation last time.

In the time of the recommendation device power-on self-test, all working address section of control module measuring ability unit, and judge whether the function of address bus is normal.Fig. 3 is for realizing the fault detect process flow diagram of a plurality of functional units addresses buses, and its concrete steps are as follows:

The functional unit that control module detects to need sends and reads or writes order; And triggering d type flip flop;

The control module gating also reads the content that latchs in the d type flip flop, and the address information of detected functional unit compared with last time;

If both are inequality, then judge this functional units addresses bus failure;

Control module judges whether to continue to detect the address bus of other functional unit;

Continue if desired to detect, then continue the start detection flow process;

If do not need to continue to detect, then process ends.

The method according to this invention, when the logic function of design function unit, can be by adding a special register, the address information that this register was exported during the control module information interaction in order to storage last time, and when control module is visited this register with register in address stored information feed back to control module by data bus, whether working properly with this address bus that detects this functional unit.

The above; only for the preferable embodiment of the present invention, but protection scope of the present invention is not limited thereto, and anyly is familiar with those skilled in the art in the technical scope that the present invention discloses; the variation that can expect easily or replacement all should be encompassed within protection scope of the present invention.Therefore, protection scope of the present invention should be as the criterion with the protection domain of claims.

Claims

1, a kind of fault detection method of address bus may further comprise the steps:

A: the signal input part of link address bus and register;

2, the method for claim 1 is characterized in that: described step c also comprises, after control module reads the current address bus message that latchs in the register, makes the current address bus message that latchs in the register be updated to the address of register.

3, the method for claim 1 is characterized in that: comprise the steps: that further control module judges whether to detect the address bus of other functional unit, if then go to step b, otherwise finish detection.

4, the method for claim 1 is characterized in that: among the described step b, the concrete grammar of trigger register is: the reading and writing by control module or its composite signal are as the trigger pip of register.

5, as claim 1,2,3 or 4 described methods, it is characterized in that: among the described step c, control module reads the current address bus message that latchs in the register and sends read signal by control module to register and come this register of gating.

6, as claim 1,2,3 or 4 described methods, it is characterized in that: among the described step c, it is to come this register of gating by the composite signal of address decoding and read signal that control module reads the current address bus message that latchs in the register.

7, as claim 1,2,3 or 4 described methods, it is characterized in that: among the described step c, control module read the current address bus message that latchs in the register be by control module I the O control signal come this register of gating.

8, as claim 1,2,3 or 4 described methods, it is characterized in that: described register is a d type flip flop.