CN109976660B - Random signal sampling rate reconstruction method based on linear interpolation and data sampling system - Google Patents
Random signal sampling rate reconstruction method based on linear interpolation and data sampling system Download PDFInfo
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Abstract
The invention discloses an arbitrary signal sampling rate reconstruction method and a data sampling system based on linear interpolation. According to the random resampling method, interpolation can be carried out while input data is written, interpolation is not needed to be carried out after input data is written, interpolation time is saved, meanwhile, all input data do not need to be stored simultaneously, and occupied resources are small.
Description
Technical Field
The invention relates to the field of signal sampling, in particular to an arbitrary signal sampling rate reconstruction method and a data sampling system based on linear interpolation.
Background
The digital receiver has very wide application in the fields of electronic communication, electronic countermeasure, radar receivers and the like, and has the advantages of small volume, good stability, flexible design, high sensitivity and the like. When the intermediate frequency signal of the receiver is converted by A/D, the Nyquist theorem is satisfied, the sampling rate is larger than the baseband rate, and for different communication systems, the required signal rates are different, which requires different signal rate conversion.
The conversion to achieve the sampling rate in the digital domain typically includes integer-multiple decimation, integer-multiple interpolation, rational-factor rate conversion, etc. The integer multiple interpolation and decimation are simple to realize and can be realized by using a low-pass filter, CIC decimation filtering and a multiphase structure. Rational factor rate conversion I/D, where I is the interpolation multiple and D is the decimation multiple. If the values of I and D are not very large, the cascade implementation of I-time interpolation and D-time extraction can be adopted. If the values of I and D are relatively large, it is difficult to implement them by using a cascade method, and a Farrow filter is generally used.
The multiphase filter realizes I/D times rational rate conversion, which is equivalent to firstly realizing interpolation by using the multiphase filter factor of the I branch and then extracting D times. If the factor I is large, a large number of multi-branch filter factors are required, which increases the amount of calculation, and the data rate requirement is high, which is difficult to implement in practical application.
The Farrow filter structure is commonly used to achieve rate conversion of the rational factors of I/D. The Farrow filter is realized by a plurality of filter branches and fractional delay, and the interpolated or decimated output value of the Farrow filter can be obtained by multiplying the output of the filter by the fractional delay factor. The number of branches of the filter and the filter factor are fixed and unchanged, and interpolation or extraction of any multiple can be realized only by changing the fractional delay factor. However, the Farrow structure requires more multipliers and the design difficulty is also high. The Farrow structure requires an additional I & D circuit and a fractional delay control circuit, which is difficult to implement in an FPGA. If the delay factor is stored in a memory module in the FPGA, a large memory space is required. In addition, sometimes the fractional delay offset is too large, resulting in a relatively large error.
Conventionally, a DSP is used to realize interpolation and decimation processing of signals, but the DSP is executed sequentially, the throughput of data is relatively small, the processing speed is relatively slow, and it is difficult to meet the requirement of high processing speed. And the FPGA is used for processing parallel signals, so that the data throughput is high, the processing speed is high, and the requirements can be met.
Disclosure of Invention
The present invention is directed to solving, at least to some extent, one of the technical problems in the related art. Therefore, the first aspect of the present invention provides an arbitrary resampling method with fast processing speed and less occupied resources.
A second aspect of the invention proposes a data sampling system.
A third aspect of the invention proposes a non-transitory readable storage medium.
An arbitrary resampling method according to the first aspect of the present invention, comprising the steps of:
writing and storing the interpolated input data;
reading the input data while the input data is written and stored;
and carrying out decimal multiple interpolation according to the input data to obtain output data.
According to the random resampling method of the first aspect of the present invention, interpolation can be performed while input data is written, interpolation is not required to be performed after input data is written first, interpolation time is saved, and meanwhile, all input data is not required to be stored simultaneously, and less resources are occupied.
Further, performing fractional multiple interpolation according to the input data, comprising: and performing decimal multiple interpolation according to the time sequence points to determine interpolation data corresponding to the time sequence point positions.
Further, performing fractional multiple interpolation according to the time series points, including: when the interpolation multiple is less than or equal to A, performing decimal multiple interpolation according to the time sequence points; and when the interpolation multiple is larger than A, performing integer multiple interpolation on the input data, and then performing decimal multiple interpolation according to the time sequence point.
Further, performing fractional multiple interpolation according to the input data, comprising: when the number of the stored non-interpolation values of the input data is more than or equal to 2, entering a reading state; and when the number of the stored non-interpolation values of the input data is less than 2, entering a waiting state.
Further, assuming that the frame length of the input data is N, the length of the output data is I, and the number MM of data interpolation gaps satisfies MM = N-1, the arbitrary resampling method includes the steps of:
initializing to an idle state;
when the number of the stored non-interpolation values of the input data is more than or equal to 2, entering a reading state, generating a reading address and a reading enable according to the position n of the input data, and reading the input data;
Entering an interpolation state, and performing decimal multiple interpolation on the input data to obtain output data;
when the position m of the output data meets the condition that m + MM < I + 1, the interpolation state is kept, and the output data is output;
and when the position m of the output data meets the condition that m + MM is more than or equal to I + 1, returning to the reading state.
Optionally, the arbitrary signal sampling rate reconstruction method is implemented based on an FPGA programmable logic chip.
The data sampling system according to the second aspect of the present invention includes a RAM storage module, a control module, and an interpolation module, where the control module is respectively in communication with the RAM storage module and the interpolation module, the RAM storage module is in communication with the interpolation module, the RAM storage module is used to write and store interpolated input data, and the control module is used to control the interpolation module to read the input data stored in the RAM storage module while writing and storing the input data in the RAM storage module, and output the output data after performing fractional multiple interpolation on the input data to obtain output data.
According to the data sampling system of the second aspect of the invention, the interpolation can be performed while the input data is written, the interpolation is not required to be performed after the input data is written first, the interpolation time is saved, and meanwhile, the RAM storage module is not required to store all the input data at the same time, so that the occupied resources are small.
Further, the interpolation module comprises a state machine, and the control module controls the interpolation module to perform fractional multiple interpolation on the data through the state machine.
Further, when the control module judges that the number of the non-interpolated values of the input data stored in the RAM storage module is greater than or equal to 2, the controller sends the reading signal =1 to the state machine, and the state machine enters a reading state;
and when the control module judges that the number of the non-interpolation values of the input data stored in the RAM storage module is less than 2, the controller sends the reading signal =0 to the state machine, and the state machine enters a waiting state.
A non-transitory readable storage medium according to a third aspect of the present invention has stored thereon a program which, when executed by a processor, implements the linear interpolation based arbitrary signal sample rate reconstruction method according to the first aspect of the present invention.
According to the non-transitory readable storage medium of the third aspect of the present invention, interpolation can be performed while input data is written, and interpolation after input data is written is not required, so that interpolation time is saved, all input data are not required to be stored simultaneously, and less resources are occupied.
Additional aspects and advantages of the invention will be set forth in part in the description which follows and, in part, will be obvious from the description, or may be learned by practice of the invention.
Drawings
The above and/or additional aspects and advantages of the present invention will become apparent and readily appreciated from the following description of the embodiments, taken in conjunction with the accompanying drawings of which:
FIG. 1 is a schematic structural diagram of an arbitrary signal sampling rate reconstruction method based on linear interpolation according to an embodiment of the present invention;
fig. 2 is a flowchart of an arbitrary signal sampling rate reconstruction method based on linear interpolation according to an embodiment of the present invention.
Reference numerals:
the data sampling system 100, the RAM storage module 1, the control module 2, the interpolation module 3, a read address addra, a read enable ren, a write address addrb, a write enable wen, a frame length N, input data x (N), output data y (m), a write clock clka, a read clock clkb, and a reading signal data _ en.
Detailed Description
Reference will now be made in detail to embodiments of the present invention, examples of which are illustrated in the accompanying drawings, wherein like or similar reference numerals refer to the same or similar elements or elements having the same or similar function throughout. The embodiments described below with reference to the drawings are illustrative and intended to be illustrative of the invention and are not to be construed as limiting the invention.
Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of the present invention, "a plurality" means at least two, e.g., two, three, etc., unless specifically limited otherwise.
In the present invention, unless otherwise expressly stated or limited, the terms "mounted," "connected," "secured," and the like are to be construed broadly and can, for example, be fixedly connected, detachably connected, or integrally formed; can be mechanically connected, electrically connected or can communicate with each other; either directly or indirectly through intervening media, either internally or in any other relationship. The specific meanings of the above terms in the present invention can be understood by those skilled in the art according to specific situations.
The invention is described below with reference to specific embodiments in conjunction with the accompanying drawings.
An arbitrary resampling method of an embodiment of the present invention is first described with reference to fig. 1 and 2.
As shown in fig. 1, the arbitrary resampling method according to the embodiment of the present invention may include writing interpolated input data x (n) into the RAM storage module 1 and storing the interpolated input data x (n), and controlling the interpolation module 3 to read the input data x (n) stored in the RAM storage module 1 and controlling the interpolation module 3 to perform fractional multiple interpolation on the input data x (n).
In other words, when data interpolation is performed, firstly, the input data x (n) to be interpolated is written into the RAM storage module 1, and in the process of writing the interpolated input data x (n) into the RAM storage module 1, that is, when the part of the interpolated input data x (n) is written into the RAM storage module 1, the control module 2 controls the interpolation module 3 to read the part of the input data x (n) already written into the RAM storage module 1, and controls the interpolation module 3 to perform fractional multiple interpolation on the part of the input data x (n).
Therefore, compared with the algorithm that all input data x (n) are written into the storage module and then interpolation is carried out in the prior art, the random resampling method in the embodiment can carry out interpolation while the input data x (n) are written, interpolation does not need to be carried out after the input data x (n) are written into, interpolation time is saved, and meanwhile, the RAM storage module 1 does not need to store all the input data x (n) at the same time, and occupied resources are few.
The RAM storage module 1 stores interpolated input data x (n), when fractional interpolation is realized, the input data x (n) before interpolation and the interpolated output data y (m) are not in an integer multiple relationship, at this time, interpolation is performed by using a write clock clka matched with the input data x (n) and a read clock clkb matched with the output data y (m), if the data taken out by the storage module is not aligned with the clock, risk impact occurs, which causes data errors, and the RAM storage module 1 can be used for realizing data buffering, which does not have the problem.
In addition, according to the arbitrary resampling method in the embodiment of the present invention, only one adder and two multipliers are used for interpolation output of the primary output data y (m), and the hardware resources used are few. The algorithm has the advantages of simple implementation, small distortion degree, less used hardware resources, capability of realizing resampling of any decimal number and the like.
Specifically, the arbitrary resampling method further includes: the interpolation module 3 performs decimal multiple interpolation according to the time sequence points to determine interpolation data corresponding to the time sequence point positions. When the interpolation module 3 implements the fractional resampling algorithm, it needs to determine the position of the interpolation point to be resampled relative to the original sampling point according to the time sequence. Since the reconstructed interpolation data does not always exist at the original time-series point, it is necessary to construct the required output data y (m) values corresponding to the time-series points from the input data x (n) values at the original time-series points.
Because any resampling method adopts linear interpolation to reconstruct signals, when the interpolation multiple is large, the signals are distorted. Specifically, when the interpolation multiple is less than or equal to a, the interpolation multiple is smaller, and the interpolation module 3 performs decimal multiple interpolation according to the time sequence point. When the interpolation multiple is larger than A, the interpolation multiple is larger at this time, the filter performs integral multiple interpolation on the input data x (n) first and then transmits the input data x (n) to the interpolation module 3, and the interpolation module 3 performs decimal multiple interpolation according to the time sequence point, namely, the interpolation of the filter and the decimal interpolation can be realized by adopting a method of cascading. Therefore, the accuracy of decimal multiple interpolation calculation can be ensured. Specifically, a = 4.
Because the interpolation algorithm needs two sample data to perform interpolation, specifically, the arbitrary resampling method includes: the control module 2 enters a reading state and further enters an interpolation state when judging that the number of the input data x (n) which is not subjected to interpolation calculation and is stored in the RAM storage module 1 is more than or equal to 2, so that the control module 2 controls the interpolation module 3 to perform decimal multiple interpolation on the input data x (n). When the control module 2 judges that the number of the input data x (n) which are stored in the RAM storage module 1 and not subjected to interpolation calculation is less than 2 (namely 0 or 1), the control module 2 makes the interpolation module 3 in a waiting state to temporarily wait for new input data x (n) to be input into the RAM storage module 1, and then performs interpolation after the number of the input data x (n) which are not subjected to interpolation calculation meets the interpolation condition (namely is more than or equal to 2). The control module 2 provides an enabling signal for the interpolation module 3 according to the number of data stored in the RAM storage module 1 so as to change the working state of the interpolation module 3. Therefore, by adopting the processing method, data storage and data interpolation can be carried out simultaneously, and the processing speed is improved.
When frame data is interpolated, the frame length of input data x (N) is set as N, and the length of output data y (m) is set as I, and the interpolation multiple is I/N. The data is equivalent to firstly carrying out I-time interpolation and then carrying out N-time data extraction.
The number of I-1 samples is inserted between two samples of data, which is equivalent to I times of the original data, and the interpolation of the I times of the data is performed. The length of the input data x (N) before interpolation is equal to the length N of the data frame, and interpolation is carried out between every two numbers, which is equivalent to that the number of data interpolation gaps is MM = N-1. The assumed data reconstruction has a data length of L:
performing N-1 times of data extraction on reconstructed data
The interpolation is equivalent to the interpolation of I times, and the reconstructed data is subjected to the access MM of N-1 position intervals.
The value of the interpolated output y (m) does not always exist in x (n), and the required position points are constructed according to the original sample values x (n) of each position. We only need the data at time y (m) and x (t), other data is not of interest. So only the data at this moment need be recovered. Therefore, it is mainly to determine the position m of the data and construct the output data y (m) value corresponding to the position m, where m is incremented by MM.
When m + MM > = I + 1, the next input data x (n) is read and interpolated, and the position of m relative to the new two input data x (n) is
The output value is equivalent to the value of m position after I-1 point is inserted between two interpolation points, and the calculation formula of linear interpolation data
Fig. 2 is a flow chart of an implementation of the interpolation module 3. Initializing m =1, inputting two data, and calculating an output value according to a formula. And when the position of the next interpolation m is judged, and m + MM > = I +1, the interpolation data position is between x (n +1) and x (n +2), data input is needed, and interpolation is carried out again after the input of one data is finished. When m + MM < I +1, the position of the interpolation output data y (m) is still between x (n) and x (n +1), and the data output value can be directly calculated.
Specifically, the interpolation module 3 includes a state machine, and the control module 2 controls the interpolation module 3 to interpolate data through the state machine. This allows interpolation to be performed while writing the input data x (n).
More specifically, as shown in fig. 2, the arbitrary resampling method includes:
the state machine is in an idle state;
when the number of the stored input data x (n) without interpolation is more than or equal to 2, the state machine enters a reading state, generates a reading address addra and a reading enable ren according to the position n of the input data x (n), and reads the input data x (n) from the RAM storage module 1;
The state machine enters an interpolation state, and decimal multiple interpolation is carried out on input data x (n) to obtain output data y (m);
when the state machine judges that the position m of the output data y (m) meets the condition that m + MM < I + 1, the state machine keeps an interpolation state and outputs the output data y (m);
when the state machine judges that the position m of the output data y (m) meets the condition that m + MM is more than or equal to I + 1, the state machine returns to the reading state to perform the interpolation of the next group;
when the number of the stored input data x (n) without interpolation is less than 2, the state machine enters a waiting state;
and when the interpolation is completely finished, the state machine is restored to the idle state.
Thus, an interpolation process of an arbitrary resampling method can be realized, and interpolation can be performed while writing the input data x (n).
Further, when the control module 2 determines that the number of the non-interpolated values of the input data x (n) stored in the RAM storage module 1 is greater than or equal to 2, the controller sends a reading signal data _ en =1 to the state machine, and the state machine enters a reading state; when the control module 2 judges that the number of the non-interpolation values of the input data x (n) stored in the RAM storage module 1 is less than 2, the controller sends a reading signal data _ en =0 to the state machine, and the state machine enters a waiting state. Therefore, by adopting the processing method, data storage and data interpolation can be carried out simultaneously, and the processing speed is improved.
Optionally, any resampling method in any embodiment of the present invention may be implemented based on an FPGA programmable logic chip, so that it can be ensured that hardware resources used by any resampling method are few. The data storage module is composed of an RAM storage module 1 of the FPGA programmable logic chip, and the storage module realizes the caching of data.
According to the write clock clka and the read clock clkb of the data in the RAM memory module 1, the data read and write speed can be changed to match the asynchronous read and write clock clka, so as to avoid the generation of burrs due to the data misalignment. And storing data into the RAM according to the enable (such as write enable wen and read enable ren) and the clock of the input data x (N), wherein the number of the stored data reaches a frame length value N, the write address addrb becomes 0, and the write address addrb becomes 0 after receiving the emptying command. And calculating the data reading address addra according to the data position required by the interpolation algorithm, and initializing the data reading address addra to be 0 when the state machine is in an idle state or receives a clearing command.
It should be noted that the method for reconstructing an arbitrary signal sampling rate based on linear interpolation according to the embodiments of the present invention has many application fields, for example, it can be applied to rate conversion and display data interpolation of a receiver and a spectrometer, and can also be applied to audio data rate conversion, for example.
A data sampling system 100 of an embodiment of the present invention is described below.
The data sampling system 100 of the embodiment of the invention comprises a RAM storage module 1, a control module 2 and an interpolation module 3, wherein the control module 2 is respectively communicated with the RAM storage module 1 and the interpolation module 3, the RAM storage module 1 is communicated with the interpolation module 3, the RAM storage module 1 is used for writing and storing interpolated input data x (n), the control module 2 is used for controlling the interpolation module 3 to read the input data x (n) stored in the RAM storage module 1 while the input data x (n) is written and stored in the RAM storage module 1, and after the input data x (n) is interpolated to obtain output data y (m), the output data y (m) is output.
According to the data sampling system 100 of the embodiment of the invention, by setting any resampling method, interpolation can be carried out while input data x (n) is written, interpolation does not need to be carried out after input data x (n) is written first, interpolation time is saved, and simultaneously the RAM storage module 1 does not need to store all input data x (n) at the same time, and occupied resources are less.
The following describes a non-transitory readable storage medium of an embodiment of the present invention.
According to a non-transitory readable storage medium of the present invention, there is stored thereon a program which, when executed by a processor, implements an arbitrary signal sampling rate reconstruction method based on linear interpolation according to any embodiment of the present invention.
According to the non-transitory readable storage medium provided by the embodiment of the invention, interpolation can be carried out while the input data x (n) is written, interpolation does not need to be carried out after the input data x (n) is written, the interpolation time is saved, and meanwhile, the occupied resources are less.
In the description herein, references to the description of the term "one embodiment," "some embodiments," "an example," "a specific example," or "some examples," etc., mean that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the invention. In this specification, the schematic representations of the terms used above are not necessarily intended to refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples. Furthermore, various embodiments or examples described in this specification can be combined and combined by those skilled in the art.
Although embodiments of the present invention have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting the present invention, and that variations, modifications, substitutions and alterations can be made to the above embodiments by those of ordinary skill in the art within the scope of the present invention.
Claims (6)
1. A method for reconstructing any signal sampling rate based on linear interpolation is characterized in that the reconstruction of the signal sampling rate is carried out by adopting the linear interpolation;
the linear interpolation includes the steps of:
writing and storing interpolated input data;
performing decimal multiple interpolation according to the input data, including;
when the number of the non-interpolation values of the input data is more than or equal to 2, entering a reading state;
when the number of the non-interpolation values of the input data is less than 2, entering a waiting state;
setting the frame length of the input data as N, the length of the output data as I, and the number MM of data interpolation gaps to satisfy MM = N-1, wherein the method for reconstructing any signal sampling rate comprises the following steps:
initializing to an idle state;
when the number of the stored non-interpolation values of the input data is more than or equal to 2, entering a reading state, generating a reading address and a reading enable according to the position n of the input data, and reading the input data;
entering an interpolation state, and performing decimal multiple interpolation on the input data to obtain output data;
when the position m of the output data meets the condition that m + MM < I + 1, the interpolation state is kept, and the interpolated data is output;
when the position m of the output data meets the condition that m + MM is more than or equal to I + 1, returning to the reading state;
Performing fractional multiple interpolation according to the input data, comprising: performing decimal multiple interpolation according to the time sequence points to determine interpolation data corresponding to the time sequence point positions;
and performing decimal multiple interpolation according to the time sequence points, wherein the decimal multiple interpolation comprises the following steps: when the interpolation multiple is less than or equal to 4, performing decimal multiple interpolation according to the time sequence points;
when the interpolation multiple is larger than 4, the filter firstly performs integer multiple interpolation on the input data and then transmits the input data to the interpolation module, and the interpolation module performs decimal multiple interpolation according to the time sequence points.
2. The linear interpolation based arbitrary signal sampling rate reconstruction method of claim 1, wherein the arbitrary signal sampling rate reconstruction method is implemented based on an FPGA programmable logic chip.
3. A data sampling system for performing the method of reconstructing an arbitrary signal sampling rate based on linear interpolation according to any one of claims 1 to 2, the data sampling system comprising a RAM memory module, a control module, and an interpolation module, the control module being in communication with the RAM memory module and the interpolation module, respectively, the RAM memory module being in communication with the interpolation module, the RAM memory module being configured to write and store interpolated input data, and the control module being configured to control the interpolation module to read the input data stored in the RAM memory module and output data after fractional-multiple interpolation of the input data while the input data is written and stored in the RAM memory module.
4. The data sampling system of claim 3, wherein the interpolation module includes a state machine, and the control module controls the interpolation module to perform fractional multiple interpolation on the data via the state machine.
5. The data sampling system of claim 4, wherein when the control module determines that the number of the non-interpolated values of the input data stored in the RAM storage module is greater than or equal to 2, the controller sends a reading signal =1 to the state machine, and the state machine enters a reading state;
and when the control module judges that the number of the non-interpolation values of the input data stored in the RAM storage module is less than 2, the controller sends the reading signal =0 to the state machine, and the state machine enters a waiting state.
6. A non-transitory readable storage medium having stored thereon a program, wherein the program, when executed by a processor, implements the linear interpolation based arbitrary signal sample rate reconstruction method according to any one of claims 1-2.
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| CN101207372A (en) * | 2007-12-04 | 2008-06-25 | 中兴通讯股份有限公司 | Apparatus and method for implementation of fixed decimal sampling frequency conversion |
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