CN109920792A - A kind of manufacturing method of 3D nand memory part - Google Patents
A kind of manufacturing method of 3D nand memory part Download PDFInfo
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Abstract
The present invention provides a kind of manufacturing method of 3D nand memory part, it is formed after memory cell string in stack layer, the separation layer of dielectric material is formed on the dielectric layer of stepped region, later, using the grid line gap of perforation stack layer, the replacement of sacrificial layer in stack layer is carried out, after sacrificial layer is replaced with grid layer, filling and the flatening process for carrying out grid line gap form common source contact in grid line gap, and flatening process is using the dielectric layer in core memory area as stop-layer.In this way, the separation layer of dielectric material is additionally formed on stepped region, separation layer raises the dielectric layer of stepped region, when forming common source contact, even if can have the residual of conductive material in stepped region, in planarization, remaining contact material can be removed together, to avoid the residual of stepped region conductive material, improve yield of devices.
Description
Technical field
The present invention relates to semiconductor devices and its manufacturing field, in particular to a kind of manufacturer of 3D nand memory part
Method.
Background technique
Nand memory part is the non-volatile memory product with low in energy consumption, light weight and excellent performance, in electronic product
It is widely used.
The limit of the NAND device of planar structure nearly true extension reduces every to further improve memory capacity
The carrying cost of bit proposes 3D nand memory part.In 3D nand memory part structure, using vertical stacking multilayer
The mode of grid, the central area of stack layer is core memory area, fringe region is step structure, and core memory area is used to form
Go here and there storage unit, grid line of the conductive layer as each layer of storage unit in stack layer, grid line is drawn by the contact on step,
To realize the 3D nand memory part of stack.
In the manufacturing process of 3D nand memory part, using the grid line gap of perforation stack layer, carry out sacrificial in stack layer
After the replacement of domestic animal layer, in the region of step structure it is possible that being recessed, and then when grid line gap forms common source contact, hold
Tungsten (W) is easily caused to remain in the recess, tungsten remains the contact process that will affect stepped area, causes the failure of device.
Summary of the invention
In view of this, avoiding stepped region the purpose of the present invention is to provide a kind of manufacturing method of 3D nand memory part
The residual of conductive material improves yield of devices.
To achieve the above object, the present invention has following technical solution:
A kind of manufacturing method of 3D nand memory part, comprising:
Substrate is provided, well region is formed in the substrate, it is alternately laminated with sacrificial layer that insulating layer is formed on the substrate
Stack layer, the stack layer includes core memory area and stepped region, and the stepped region is formed with step structure, the core
It is formed with memory cell string in memory block, the stepped region is formed with perforation to the pseudo- channel hole of substrate, covers on the stack layer
It is stamped dielectric layer；
The separation layer of dielectric material is formed on the dielectric layer of the stepped region；
It is formed and is penetrated through to the grid line gap of substrate in the core memory area and stepped region, and utilize the grid line gap
Sacrificial layer in the stack layer is replaced with into grid layer；
Filling and the flatening process in grid line gap are carried out, is contacted with the common source formed in grid line gap on well region,
The flatening process is using the dielectric layer in the core memory area as stop-layer.
Optionally, the filling for carrying out grid line gap and flatening process, to be formed on well region in grid line gap
Common source contact, the flatening process is using the dielectric layer in the core memory area as stop-layer, comprising:
Form first conductive layer in the grid line gap of fill part depth；
The deposition of the second conductive layer is carried out, to form the second conductive layer in grid line gap and on dielectric layer, separation layer；
Using the dielectric layer in the core memory area as stop-layer, flatening process is carried out, to form trap in grid line gap
Common source contact in area, the second conductive layer of the common source contact including first conductive layer and thereon.
Optionally, first conductive layer in the grid line gap for forming fill part depth, comprising:
Carry out the deposition of the first conductive layer；
It carries out returning for first conductive layer to carve, to form the first conductive layer in the grid line gap of partial depth.
Optionally, the material of first conductive layer includes polysilicon, and the material of second conductive layer includes tungsten.
Optionally, the shape method of the step structure includes:
Using the first mask plate, photoresist layer is covered on the stack layer in the stepped region and core memory area, is gone forward side by side
The etching of the row stack layer, etch thicknesses are a step thicknesses；
Multiple step technique is carried out, until forming step structure, the step technique includes: to carry out the photoresist layer
The etching of the stack layer of the stepped region is trimmed and carries out, etch thicknesses are a step thicknesses.
Optionally, the dielectric layer includes first medium floor and the covering core memory area for filling the stepped region
And the second dielectric layer of the first medium layer, the forming method of the first medium layer include:
Carry out the deposition of first medium layer；
Using the second mask plate, photoetching and etching technics are carried out, first of segment thickness in the core memory area is removed
Dielectric layer；
The flatening process of first medium layer is carried out, only to form fill the stepped region the on the step structure
One dielectric layer.
Optionally, the separation layer that dielectric material is formed on the dielectric layer of the stepped region, comprising:
Carry out the deposition of dielectric material；
Using first mask plate, carry out photoetching and etching technics, remove the stepped region and core memory area it
The outer dielectric material；And
Using second mask plate, photoetching and etching technics are carried out, being given an account of in the core memory area is removed
Material, to form the separation layer of dielectric material on the dielectric layer of the stepped region.
Optionally, the first medium layer, second dielectric layer and the separation layer are silica.
Optionally, the grid layer includes tungsten.
The manufacturing method of 3D nand memory part provided in an embodiment of the present invention, forms memory cell string in stack layer
Later, on the dielectric layer of stepped region formed dielectric material separation layer, later, using perforation stack layer grid line gap,
The replacement for carrying out sacrificial layer in stack layer carries out the filling in grid line gap and flat after sacrificial layer is replaced with grid layer
Chemical industry skill forms common source contact in grid line gap, and flatening process is using the dielectric layer in core memory area as stop-layer.This
Sample is additionally formed the separation layer of dielectric material on stepped region, and separation layer raises the dielectric layer of stepped region, connects forming common source
When touching, even if there can be the residual of conductive material in stepped region, in planarization, remaining contact material can be removed together,
To avoid the residual of stepped region conductive material, improve yield of devices.
Detailed description of the invention
In order to more clearly explain the embodiment of the invention or the technical proposal in the existing technology, to embodiment or will show below
There is attached drawing needed in technical description to be briefly described, it should be apparent that, the accompanying drawings in the following description is the present invention
Some embodiments for those of ordinary skill in the art without creative efforts, can also basis
These attached drawings obtain other attached drawings.
Fig. 1 shows the flow diagram of the manufacturing method of 3D nand memory part according to embodiments of the present invention；
Fig. 2-8 shows the structural schematic diagram during manufacturing method formation memory device according to an embodiment of the present invention.
Specific embodiment
In order to make the foregoing objectives, features and advantages of the present invention clearer and more comprehensible, with reference to the accompanying drawing to the present invention
Specific embodiment be described in detail.
In the following description, numerous specific details are set forth in order to facilitate a full understanding of the present invention, but the present invention can be with
It is different from other way described herein using other and implements, those skilled in the art can be without prejudice to intension of the present invention
In the case of do similar popularization, therefore the present invention is not limited by the specific embodiments disclosed below.
Secondly, combination schematic diagram of the present invention is described in detail, when describing the embodiments of the present invention, for purposes of illustration only, table
Show that the sectional view of device architecture can disobey general proportion and make partial enlargement, and the schematic diagram is example, is not answered herein
Limit the scope of protection of the invention.In addition, the three-dimensional space of length, width and depth should be included in actual fabrication.
As the description in background technique, in the manufacturing process of 3D nand memory part, the grid of perforation stack layer are utilized
Linear slit gap carries out in stack layer after the replacement of sacrificial layer, in the region of step structure it is possible that being recessed, and then in grid line
When gap forms common source contact, it is easy that tungsten (W) is caused to remain in the recess, tungsten remains the contact work that will affect stepped area
Skill causes the failure of device.
For this purpose, the application provides a kind of manufacturing method of 3D nand memory part, memory cell string is formed in stack layer
Later, on the dielectric layer of stepped region formed dielectric material separation layer, later, using perforation stack layer grid line gap,
The replacement for carrying out sacrificial layer in stack layer carries out the filling in grid line gap and flat after sacrificial layer is replaced with grid layer
Chemical industry skill forms common source contact in grid line gap, and flatening process is using the dielectric layer in core memory area as stop-layer.This
Sample is additionally formed the separation layer of dielectric material on stepped region, and separation layer raises the dielectric layer of stepped region, connects forming common source
When touching, even if there can be the residual of conductive material in stepped region, in planarization, remaining contact material can be removed together,
To avoid the residual of stepped region conductive material, improve yield of devices.
The technical solution and technical effect of the application in order to better understand, below with reference to flow chart Fig. 1 and attached drawing 2-8
Specific embodiment is described in detail.
Refering to what is shown in Fig. 1, providing substrate 100 in step S01, well region, the substrate 100 are formed in the substrate 100
On be formed with insulating layer 104 and the alternately stacked stack layer 110 of sacrificial layer 102, the stack layer 110 includes core memory area
1101 and stepped region 1102, the stepped region 1102 be formed with step structure 120, be formed in the core memory area 1101
Memory cell string 150 is covered with dielectric layer 130,170 on the stack layer 110, with reference to shown in Fig. 2.
In the embodiment of the present application, substrate 100 is semiconductor substrate, such as can be Si substrate, Ge substrate, SiGe lining
Bottom, SOI (silicon-on-insulator, Silicon On Insulator) or GOI (germanium on insulator, Germanium On
Insulator) etc..In other embodiments, the semiconductor substrate can also be include other elemental semiconductors or compound
The substrate of semiconductor, such as GaAs, InP or SiC etc. can also be laminated construction, such as Si/SiGe etc. can be with other outer
Prolong structure, such as SGOI (silicon germanium on insulator) etc..In the present embodiment, the substrate 100 is body silicon substrate.
The stack layer 110 can be formed on well region (not shown go out), and well region is formed in substrate 100, and well region is core
The array common source area (Array Common Source) of memory device in memory block, can be by p-type or N-type heavy doping come shape
At in the present embodiment, which is p-type heavy doping well region (HVPW), is also formed in p-type heavy doping well region periphery and mixes on the contrary
Miscellaneous peripheral well region, N-type heavy doping well region (HVNW), the periphery well region be formed in core memory area 1101 and stepped region 1102 it
Outer region.
Stack layer 110 can be formed by alternately stacked insulating layer and sacrificial layer.Specifically, perpendicular to substrate direction
When the via etch in channel hole, there is the dry etching of almost 1:1 to select ratio for sacrificial layer and insulating layer；Substrate side will be parallel to
To sacrificial layer be replaced by grid layer when, there is very high wet etching to select ratio for sacrificial layer and insulating layer, such as can be 30:
1 is even higher, and the number of plies of stack layer can be determined according to specific needs.In the present embodiment, sacrificial layer for example can be
Silicon nitride (Si3N4), insulation layers such as can be silica (SiO2)。
Stack layer 110 includes core memory area 1101 and stepped region 1102, and core memory area 1101 is usually in stack layer
Central region, usually in the surrounding in core memory area, one of direction coker feels 1101 two sides of storage area for stepped region 1102
Step can be used for forming gate contact, and the step on another direction can be not used to form contact, for pseudo- step.Core
Memory cell string will be used to form by feeling storage area 1101, and stepped region 1102 will be used for the contact (Contact) of grid layer.It needs
It is bright, in the attached drawing of the embodiment of the present application, only illustrate the step structure 120 of stack layer side, and with the side stage rank
The part core memory area 1101 that structure 120 connects.
Step structure 120 can for along substrate planar direction separate unit stage structure incremented by successively, separate unit rank
Structure can be formed by the trimming (Trim) and stack layer etching technics of alternate photoresist；Step structure 120 can also be with
For subregion step (Staircase Divide Scheme, SDS), subregion step along substrate planar two it is orthogonal
Step is all formed on direction, subregion step can have different subregions, such as 3 subregions, 4 subregions or more multi partition etc.,
Such as different subregion plates can be used, it is tight after trimming each time by the multiple trimming of photoresist in 2 orthogonal directions
With the etching of a stack layer, to form subregion step.
Dielectric layer 130,170, i.e. the core memory area 1101 and stepped region of stack layer 110 are covered on stack layer 110
The dielectric layer 130,170 of substantially flat is covered on 1102 step structure, which can form by multiple technique.This
In embodiment, dielectric layer includes the first medium layer 130 that stepped region 1102 is filled on step structure 120, and covering core is deposited
Storage area 1101 and the second dielectric layer of first medium layer 130 170.The first medium layer 130 can be laminated construction, fill
After first medium layer 130, so that step structure 120 and the upper surface in core memory area 1101 are substantially flush.More preferably, first
Dielectric layer 130 is laminated construction, can be initially formed the first sub- film layer with preferable step coverage, the first sub- film layer is for example
It can be with HDP (High Density Plasma, high-density plasma) silica (SiO2) or ALD (atomic layer deposition) oxygen
SiClx etc. then can continuously form the second sub- film layer with high charging efficiency, the second sub- film layer for example can for based on
Silica (the TESO-based SiO of TEOS2) etc., and planarized, to form the first medium layer 130.
Memory cell string 150 is along perpendicular to the memory cell layers on 100 direction of substrate, and each layer of grid layer and storage are single
Member string constitutes a storage unit.Wherein, memory cell string 152 includes store function layer and the ditch being sequentially formed in channel hole
Channel layer, store function layer play the role of charge storage, including barrier layer, charge storage layer and the tunnelling stacked gradually
(Tunneling) layer store function layer, channel layer is formed on the side wall of store function layer and the bottom in channel hole, with extension
Structure 150 contacts, and can also be formed with the filled layer of insulating materials between channel layer, in the present embodiment, barrier layer, charge storage
Layer and tunnelling (Tunneling) layer are specifically as follows ONO lamination, and ONO (Oxide-Nitride-Oxide) lamination aoxidizes
The lamination of object, nitride and oxide, channel layer can be polysilicon layer, and filled layer can be silicon oxide layer.
In the embodiment of the present application, it is also formed with epitaxial structure 140 under memory cell string 150, which can lead to
It crosses substrate epitaxial to grow to be formed, the channel of the lower gating tube device as memory cell string 150, under bottom grid layer 1021 is used as
Gate the grid of tube device.Conductive layer 152 is also formed on memory cell string 150, which, which can be used for being formed, deposits
The upper gating tube device of storage unit string 150 will also form interconnection architecture on conductive layer 152, to be further formed bit line.
Second dielectric layer 170 can be single or multi-layer structure, and the second dielectric layer 170 is by core memory area 1101 and platform
Rank area 1102 covers, and conductive layer 152 is covered by second dielectric layer 170.In the present embodiment, which can be
The second dielectric layer 170 of silica, the silica is formed by technique twice, and first time technique is to be formed before forming channel hole
Channel hole silica (channel hole plug oxide), second of technique is to form the ditch formed after conductive layer 152
Road hole cap layers silica (channel hole cap oxide).
In addition, can also be formed with perforation in stepped region 1102 to the pseudo- channel hole 160 of substrate 100, pseudo- channel hole 160 is used
In when sacrificial layer is replaced, play the role of support to stepped region 1102, which can be dielectric material, such as
It can be silica.In the present embodiment, the puppet channel hole 160 can be formed after forming conductive layer 152.
In specific application, above-mentioned structure can be obtained using suitable material and by suitable mode, step.
More preferably, in the present embodiment, the shape method of step structure 120 may include:
S011 covers photoresist layer on the stack layer in the stepped region and core memory area using the first mask plate,
And the etching of the stack layer is carried out, etch thicknesses are a step thicknesses；
S012 carries out multiple step technique, until forming step structure, the step technique includes: to carry out the photoetching
The etching of the stack layer of the trimming and progress stepped region of glue-line, etch thicknesses are a step thicknesses.
First mask plate mask plate used when being the bottom step to form step structure 120, using photoetching technique,
Photoetching process is utilized under the mask plate, photoresist layer is covered on stepped region 1102 and core memory 1101, in the photoresist
It under layer masking, performs etching, the etching of stack layer is etched downwards to one step thicknesses of removal, completion etches for the first time, the secondary quarter
Erosion defines memory device region, i.e. core memory area and stepped region in stack layer；Then, under different mask plates
By the trimming (trim) of photoresist layer, and the etching of a step thicknesses is and then carried out after each trimming, thus shape
At the step structure highly successively changed, a step thicknesses can be the thickness of one or more insulating layers and the lamination of sacrificial layer
Degree, this method utilize a photoetching process, form multi-stage stairs structure, manufacturing cost is effectively reduced.Wherein, photoetching process is benefit
The technique that the photoresist layer of specific pattern is formed with mask plate mainly includes gluing, baking, development.
The forming method of above-mentioned formation first medium layer may include:
S013 carries out the deposition of first medium layer；
S014 carries out photoetching and etching technics, removes segment thickness in the core memory area using the second mask plate
First medium layer；
S015 carries out the flatening process of first medium layer, fills the step only to be formed on the step structure
The first medium floor in area.
In the dielectric layer filling for carrying out stepped region, stack layer 110 is completely covered in the depth direction, needs to deposit
Therefore very thick first medium layer is situated between first with photoetching and etching technics by first of most of thickness in core memory area
The removal of matter layer, then, then carries out flatening process, thus, realize the filling of stepped region, this method is imitated with higher removal
Rate reduces the process time, effectively improves manufacture efficiency.In photoetching and etching technics, firstly, being passed through using the second mask plate
Photoetching process forms the photoresist layer except covering core memory area, then, is masking with the photoresist layer, performs etching work
Skill gets rid of the first medium floor of segment thickness in core memory area, then, removes the photoresist layer.
In step S02, the separation layer 173 of dielectric material, ginseng are formed on the dielectric layer 130,170 of the stepped region 1102
It examines shown in Fig. 5.
The separation layer 173 is only formed on stepped region 1102, in this way, stepped region 1102 will be elevated, so that stepped region
The height of dielectric material 170,173 is higher than the height of the dielectric material 170 in core memory area 1101 on 1102.The separation layer uses
Dielectric material is formed, and can be single layer or laminated construction, in the present embodiment, which can be silica.
In the present embodiment, the separation layer 173 that dielectric material is formed on the dielectric layer 170 of the stepped region 1102, can
To include:
S021 carries out the deposition of dielectric material 172, with reference to shown in Fig. 3；
S022 carries out photoetching and etching technics, removes the edge of the stepped region 1102 using first mask plate
Except the dielectric material 172, with reference to shown in Fig. 4；And
S023 carries out photoetching and etching technics, removes in the core memory area 1101 using second mask plate
The dielectric material 172, on the dielectric layer 170 of the stepped region 1102 formed dielectric material separation layer 173, reference
Shown in Fig. 5.
In this embodiment, when forming the separation layer 173 on stepped region 1102, using being formed in step structure 120
The first mask plate when bottom step, and form the first medium floor 130 when filling stepped region in etching core memory area
When mask plate while improving processing quality, not will increase manufacturing cost without in addition developing new mask plate, mention
High technology integrated level.It should be noted that in this embodiment, not doing special limit to the execution sequence of step S022 and S023
It is fixed, step S022 can be first carried out, step S023 is then executed, step S023 can also be first carried out, then executes step S022.
Specifically, deposits dielectric materials 172, as shown in figure 3, such as silica；Then, one is carried out using the first mask plate
Secondary photoetching process and etching technics, i.e., the spin coating photoresist layer on dielectric material 172, and the pattern in the first mask plate is shifted
Into the photoresist layer, photoresist layer covering core memory area 1101 and stepped region 1102 after patterning, and with the patterning
Photoresist afterwards is masking, and the etching for carrying out dielectric material 172 removes the photoresist layer later, in this way, just remaining step
Dielectric material 172 in area 1102 and core memory area 1101, as shown in Figure 4；Then, one is carried out again using the second mask plate
Secondary photoetching process and etching technics, i.e. spin coating photoresist layer again, and the pattern in the second mask plate is transferred to the photoresist
In layer, the photoresist layer after patterning covers stepped region 1102, and is masking with the photoresist after the patterning, carries out medium material
The etching of material 172 removes the photoresist layer later, in this way, the dielectric material on stepped region 1102 is just remained, thus, in institute
The separation layer 173 that dielectric material is formed on the dielectric layer 170 of stepped region 1102 is stated, as shown in Figure 5.
In step S03, stitched in the grid line that the core memory area 1101 and stepped region 1102 form perforation to substrate 100
Gap 180, and the sacrificial layer 102 in the stack layer 110 is replaced with into grid layer 103 using the grid line gap 180, with reference to figure
Shown in 6.
Grid line gap (Gate Line Seam) 180 is set in stack layer 110, along wordline (WL, Word Line) by heap
Lamination is divided into multiple memory blocks, which is used to remove the sacrificial layer 102 in stack layer 110 and replaces with grid
Pole layer 103, meanwhile, also the contact for the well region being used to form in substrate is contacted as common source in the grid line gap 180.
It specifically, by lithographic technique, such as can be reactive ion etching, be sequentially etched the in core memory area 1101
Second medium layer 170, stack layer 110, until perforation is sequentially etched separation layer 172, second in stepped region 1102 and is situated between to substrate 100
Matter layer 170, first medium layer 130 and step structure 120, until penetrating through to substrate 100, to form grid line gap 180.
Then, can be using the sacrificial layer 102 in acid system erosion removal stack layer, in the realization of the present embodiment, selection
The removal of silica is avoided, such as can while silicon nitride is removed in realization to the acid solution of the high selectivity ratio of silicon nitride and silica
To use phosphoric acid (H3PO4) carry out silicon nitride layer removal.
After the removal of sacrificial layer 102, stack layer 110 is engraved structure, is vacancy layer between insulating layer 104, then,
Using grid line gap 180, grid material is filled into vacancy layer to form grid layer 103, which is the control of storage unit
Grid processed.In the present embodiment, grid material can be metal material, such as tungsten, tungsten can use physical vapour deposition (PVD)
(PVD) it is formed.
And in a series of this step, due to stack layer in technique and dielectric layer high temperature deformation difference and stepped region 1102
With 1101 stress of core memory area it is unbalanced the problems such as presence, can make stepped region 1101 occur recess 182, with reference to Fig. 6
It is shown, if there are metal residual in the recess 182, the problem of will lead to component failure.
In step S04, filling and the flatening process in grid line gap 180 are carried out, to form trap in grid line gap 180
Common source contact 190,192 in area, the dielectric layer 170 that the flatening process deposits area 1101 with the core are joined for stop-layer
It examines shown in Fig. 8.
When forming common source contact in grid line gap 180, needs first to carry out the filling of conductive material, pass through flat chemical industry
Skill only retains the conductive material in grid line gap 180, thus, common source contact is formed in grid line gap 180.However, if replacing
It changes after grid layer completion, recess 182 occurs in stepped region 1101, conductive material is filled in recess 182, due to conductive material
There is high selectivity ratio with dielectric material, in planarization process, the conductive material being difficult to remove in recess 182, to be easy to lead
Cause the residual conductive material in recess 182.And in the application, on the dielectric layer of stepped region 1102, it has been additionally formed medium material
The separation layer 173 of material, in this way, recess 182 is present in separation layer 173 even if there is recess 182, filling conductive material it
It is the dielectric layer 170 with the core memory area 1101 on lower surface for stop-layer in flatening process afterwards, when planarization, meeting
Conductive material in the separation layer 173 of segment thickness and recess is removed together, thus, avoid the residual of stepped region conductive material
It stays, improves yield of devices.
In the present embodiment, the forming step that common source contacts 190,192 includes:
S041 forms first conductive layer 190 in the grid line gap 180 of fill part depth, with reference to shown in Fig. 7.
S042 carries out the deposition of the second conductive layer, in grid line gap 180 and on dielectric layer 170, separation layer 173
The second conductive layer 192 is formed, with reference to shown in Fig. 7.
S043, the dielectric layer 170 with the core memory area 1101 is stop-layer, flatening process is carried out, in grid line
Form the common source contact on well region in gap 180, common source contact includes first conductive layer 190 and second leading thereon
Electric layer 192, with reference to shown in Fig. 8.
It is possible, firstly, to first carry out the deposition of the first conductive layer, the material of the first conductive layer for example can be polysilicon, can be with
The first conductive layer that the polysilicon is filled using atomic vapor deposition after filling, is carried out returning for first conductive layer and carved, from
And the first conductive layer 190 can be formed in the grid line gap of partial depth.Then, the heavy of second conductive layer is carried out
Product, the second conductive layer can be for example tungsten, can use physical gas-phase deposition.Then, flatening process is carried out, is put down
Smooth chemical industry skill can be for example chemical mechanical grinding (CMP, Chemical Mechanical Polishing), when planarization, with
Dielectric layer 170 in core memory area 1101 is stop-layer.
In the present embodiment, the first conductive layer 190 can fill most of depth in grid line gap, only the partial depth at top
It is filled by the second conductive layer, the first conductive layer, which can be selected, is easier to deep trouth filling and the lower material of process costs, such as polycrystalline
Silicon, the second conductive layer can select the material more conducively connecting with upper layer interconnection architecture, such as tungsten, thus, it is whole to improve
Process integration.
So far, the 3D nand memory part of the embodiment of the present application is formd, later, other processing of device can be completed
Technique, such as form interconnection architecture etc..
It should also be noted that, herein, relational terms such as first and second and the like are used merely to one
Entity or operation are distinguished with another entity or operation, without necessarily requiring or implying between these entities or operation
There are any actual relationship or orders.
The above is only a preferred embodiment of the present invention, although the present invention has been disclosed in the preferred embodiments as above, so
And it is not intended to limit the invention.Anyone skilled in the art is not departing from technical solution of the present invention ambit
Under, many possible changes and modifications all are made to technical solution of the present invention using the methods and technical content of the disclosure above,
Or equivalent example modified to equivalent change.Therefore, anything that does not depart from the technical scheme of the invention, according to the present invention
Technical spirit any simple modification, equivalent variation and modification made to the above embodiment, still fall within the technology of the present invention side
In the range of case protection.
Claims (9)
1. a kind of manufacturing method of 3D nand memory part characterized by comprising
Substrate is provided, well region is formed in the substrate, insulating layer and the alternately stacked heap of sacrificial layer is formed on the substrate
Lamination, the stack layer include core memory area and stepped region, and the stepped region is formed with step structure, the core memory
It is formed with memory cell string in area, the stepped region is formed with perforation to the pseudo- channel hole of substrate, is covered on the stack layer
Dielectric layer；
The separation layer of dielectric material is formed on the dielectric layer of the stepped region；
It is formed and is penetrated through to the grid line gap of substrate in the core memory area and stepped region, and utilize the grid line gap by institute
The sacrificial layer stated in stack layer replaces with grid layer；
Filling and the flatening process in grid line gap are carried out, it is described with the common source contact formed in grid line gap on well region
Flatening process is using the dielectric layer in the core memory area as stop-layer.
2. the manufacturing method according to claim 1, which is characterized in that the filling and planarization for carrying out grid line gap
Technique, with the common source contact formed on well region in grid line gap, the flatening process is with the medium in the core memory area
Layer is stop-layer, comprising:
Form first conductive layer in the grid line gap of fill part depth；
The deposition of the second conductive layer is carried out, to form the second conductive layer in grid line gap and on dielectric layer, separation layer；
Using the dielectric layer in the core memory area as stop-layer, flatening process is carried out, to be formed on well region in grid line gap
Common source contact, common source contact includes first conductive layer and the second conductive layer thereon.
3. manufacturing method according to claim 2, which is characterized in that the grid line seam for forming fill part depth
First conductive layer of gap, comprising:
Carry out the deposition of the first conductive layer；
It carries out returning for first conductive layer to carve, to form the first conductive layer in the grid line gap of partial depth.
4. manufacturing method according to claim 2, which is characterized in that the material of first conductive layer includes polysilicon,
The material of second conductive layer includes tungsten.
5. manufacturing method described in any one of -4 according to claim 1, which is characterized in that the shape method packet of the step structure
It includes:
Using the first mask plate, photoresist layer is covered on the stack layer in the stepped region and core memory area, and carries out institute
The etching of stack layer is stated, etch thicknesses are a step thicknesses；
Multiple step technique is carried out, until forming step structure, the step technique includes: to carry out the trimming of the photoresist layer
And the etching of the stack layer of the stepped region is carried out, etch thicknesses are a step thicknesses.
6. manufacturing method according to claim 5, which is characterized in that the dielectric layer includes fill the stepped region
One dielectric layer and the second dielectric layer for covering the core memory area and the first medium floor, the first medium layer
Forming method includes:
Carry out the deposition of first medium layer；
Using the second mask plate, photoetching and etching technics are carried out, the first medium of segment thickness in the core memory area is removed
Layer；
The flatening process of first medium layer is carried out, only to form first Jie for filling the stepped region on the step structure
Matter layer.
7. manufacturing method according to claim 6, which is characterized in that described formed on the dielectric layer of the stepped region is situated between
The separation layer of material, comprising:
Carry out the deposition of dielectric material；
Using first mask plate, photoetching and etching technics are carried out, is removed except the stepped region and core memory area
The dielectric material；And
Using second mask plate, photoetching and etching technics are carried out, the medium material in the core memory area is removed
Material, to form the separation layer of dielectric material on the dielectric layer of the stepped region.
8. manufacturing method according to claim 6, which is characterized in that the first medium layer, second dielectric layer and described
Separation layer is silica.
9. the manufacturing method according to claim 1, which is characterized in that the grid layer includes tungsten.
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