CN109873008A - A kind of MRAM chip being isolated using deep N-well - Google Patents
A kind of MRAM chip being isolated using deep N-well Download PDFInfo
- Publication number
- CN109873008A CN109873008A CN201711250206.XA CN201711250206A CN109873008A CN 109873008 A CN109873008 A CN 109873008A CN 201711250206 A CN201711250206 A CN 201711250206A CN 109873008 A CN109873008 A CN 109873008A
- Authority
- CN
- China
- Prior art keywords
- deep
- well
- mram
- trap
- circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 claims abstract description 25
- 239000000758 substrate Substances 0.000 claims abstract description 15
- 230000002093 peripheral effect Effects 0.000 claims abstract description 3
- 230000015572 biosynthetic process Effects 0.000 claims description 2
- 230000015654 memory Effects 0.000 description 11
- 238000005516 engineering process Methods 0.000 description 9
- 230000005415 magnetization Effects 0.000 description 6
- 238000010586 diagram Methods 0.000 description 4
- 238000000034 method Methods 0.000 description 4
- 238000002955 isolation Methods 0.000 description 3
- XEEYBQQBJWHFJM-UHFFFAOYSA-N Iron Chemical compound [Fe] XEEYBQQBJWHFJM-UHFFFAOYSA-N 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 230000005291 magnetic effect Effects 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 238000004458 analytical method Methods 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 230000006399 behavior Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 238000002474 experimental method Methods 0.000 description 1
- 230000005294 ferromagnetic effect Effects 0.000 description 1
- 239000003302 ferromagnetic material Substances 0.000 description 1
- 238000007429 general method Methods 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 229910052742 iron Inorganic materials 0.000 description 1
- 239000000696 magnetic material Substances 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000005259 measurement Methods 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 230000006641 stabilisation Effects 0.000 description 1
- 238000011105 stabilization Methods 0.000 description 1
- 238000013517 stratification Methods 0.000 description 1
Landscapes
- Semiconductor Memories (AREA)
Abstract
The invention discloses a kind of MRAM chips being isolated using deep N-well, and the MRAM chip includes MRAM device and circuit, P-type semiconductor substrate, N trap and deep N-well；The N trap is located at the MRAM device and circuit peripheral, and the deep N-well is located at below the MRAM device and circuit, and N trap bottom links together with the deep N-well, forms three-dimensional N trap-deep N-well to the MRAM device and circuit and is isolated.The present invention can effectively completely cut off noise, improve MRAM chip and read stability.
Description
Technical field
The invention belongs to semiconductor chip memory area more particularly to a kind of MRAM chips being isolated using deep N-well.
Background technique
Magnetic RAM (MRAM) is a kind of emerging non-volatile holographic storage technology.It possesses the read or write speed of high speed
And high integration, and can be repeatedly written by unlimited number of.MRAM can as SRAM/DRAM quick random read-write, may be used also
With the permanent reservation data after a loss of power as Flash flash memory.
MRAM has good economy and a performance, and the silicon area ratio SRAM that its unit capacity occupies has very big excellent
Gesture, the NOR Flash than being commonly used in such chip is also advantageous, bigger than the advantage of embedded NOR Flash.MRAM
Time delay is read and write close to best SRAM, power consumption is then best in various memories and memory technology；And MRAM is partly led with standard CMOS
Body technology compatibility, DRAM and Flash and standard CMOS semiconductor technique are incompatible；MRAM can also be integrated into logic circuit
In one chip.
MRAM is based on MTJ (magnetic tunnel junction) structure.By two layers of ferrimagnet clip one layer very thin it is non-ferromagnetic absolutely
Edge material composition, one layer of following ferromagnetic material is the reference layer with fixed magnetisation direction, iron above as shown in Figure 1:
Magnetic material is the memory layer of changeable magnetization direction, its direction of magnetization can be parallel or antiparallel with fixed magnetization layer.Due to
The effect of quantum physics, electric current can pass through intermediate tunnel barrier layer, but the magnetization side of the resistance of MTJ and variable magnetization layer
To related.The previous case resistance is low, and latter situation resistance is high.
The process for reading MRAM is exactly to measure to the resistance of MTJ.It writes MRAM and uses newer STT-MRAM technology
MTJ progress write operation is passed through using than reading stronger electric current.One electric current from bottom to top variable magnetization stratification at fixation
The parallel direction of layer, top-down circuit are set to it in antiparallel direction.
The memory unit of each MRAM is made of MTJ and NMOS tube.The gate pole (gate) of NMOS tube is connected to
The Word Line of chip is responsible for switching on or off this unit, and MTJ and metal-oxide-semiconductor are serially connected on the Bit Line of chip.Read-write behaviour
Work carries out on Bit Line.
As shown in Fig. 2, a MRAM chip is made of the array of one or more mram memory cells, if each array has
Dry external circuit, such as:
● row-address decoder: the address received is become the selection of Word Line
● column address decoder: the address received is become the selection of Bit Line
● read-write controller: operation is write and (adds electric current) in the reading (measurement) on control Bit Line
● input and output control: and external exchange data
The reading circuit of MRAM needs to detect the resistance of MRAM memory unit.Due to MTJ resistance can with temperature etc. and
Drift, general method are to use some high-impedance state or low resistance state memory units of being written on chip as with reference to single
Member.Sense amplifier (Sense Amplifier) is reused to compare the resistance of memory unit and reference unit.
In cmos semiconductor technique, NMOS tube mixes area by P-type semiconductor substrate injection N-type and forms source electrode and drain electrode,
Centre is isolated with the gate pole for having oxide underlayer.Source electrode connects source electrode line, and drain electrode is connect by through-hole with the MTJ that etching is formed,
As shown in Figure 3.
In chip operation, P type substrate is connected with ground wire.
The characteristics of MRAM, is integrated with CMOS technology, can be done on a single die with logic circuit.CPU and memory are integrated
There is huge meaning and market on a single die.
Embedded MRAM still in the exploratory stage, has many problems to need to solve at present, present in a problem be high
The logic circuit (such as CPU) of speed operation has very big noise.If integrated on a single die with MRAM, this noise can lead to
Cross the region that substrate enters MRAM.And the read operation of MRAM must use very little voltage (usually < 200mV, otherwise will affect interior
Deposit stabilization), it is especially sensitive to noise.It is likely to result in readout error.
In CMOS technology, chip is usually made in the substrate of P-type semiconductor.N is formed in the miserable sundries of N-type injected above
Type mixes area and N trap, can also have p-type to mix area in N trap.NMOS and PMOS tube are realized by this kind of structure.In addition, there are also one
The miserable sundries of N-type, is directly injected into certain depth, is typically used to be isolated by the technology of kind deep n-type.
Summary of the invention
In view of the above drawbacks of the prior art, the purpose of the present invention is to provide a kind of MRAM cores being isolated using deep N-well
Piece is added one layer of deep N-well in the lower section of MRAM circuit, is surrounded around circuit with N trap and connected with following deep N-well, can
Effectively isolation noise.
To achieve the above object, the present invention provides a kind of MRAM chip being isolated using deep N-well, the MRAM chip packets
Include MRAM device and circuit, P-type semiconductor substrate, N trap and deep N-well；
The P-type semiconductor substrate is located at below the MRAM device and circuit；
The N trap and the deep N-well are located in the P-type semiconductor；
The N trap is located at the MRAM device and circuit peripheral, and the deep N-well is located under the MRAM device and circuit
Side, N trap bottom links together with the deep N-well, to the MRAM device and circuit formed three-dimensional N trap-deep N-well every
From.
The present invention also provides a kind of MRAM chip being isolated using deep N-well, the MRAM chip includes MRAM array, reads
Circuit, P-type semiconductor substrate, N trap and deep N-well；
The P-type semiconductor substrate is located at below the MRAM array and the reading circuit；
The N trap and the deep N-well are located in the P-type semiconductor；
The N trap is located at the MRAM array periphery, and the deep N-well is located at below the MRAM array, N trap bottom
It links together with the deep N-well, the formation MRAM array three-dimensional N trap-deep N-well is isolated；
The N trap is located at around the reading circuit, and the deep N-well is located at below the reading circuit, N trap bottom
It links together with the deep N-well, three-dimensional N trap-deep N-well is formed to the reading circuit and is isolated.
The MRAM chip disclosed by the invention being isolated using deep N-well, which is formd, surrounds the three-dimensional of MRAM circuit, Neng Gouyou
Effect isolation noise, improves MRAM chip and reads stability.
Detailed description of the invention
Fig. 1 is prior art MTJ schematic diagram.
Fig. 2 is prior art MRAM chip architecture diagram.
Fig. 3 is prior art MRAM chip along bit line diagrammatic cross-section.
Fig. 4 is the MRAM chip structural schematic diagram being isolated using deep N-well of a preferred embodiment of the present invention.
Fig. 5 is the MRAM chip structural schematic diagram of another preferred embodiment of the present invention being isolated using deep N-well.
Specific embodiment
The preferred embodiments of the present invention will be described in detail below so that advantages and features of the invention can be easier to by
It will be appreciated by those skilled in the art that so as to make a clearer definition of the protection scope of the present invention.
Embodiment 1
Fig. 4 shows a kind of MRAM chip being isolated using deep N-well, including MRAM device and circuit 1, P-type semiconductor lining
Bottom 2, N trap 3 and deep N-well 4；
P-type semiconductor substrate 2 is located at 1 lower section of MRAM device and circuit；N trap 3 and deep N-well 4 are located in P-type semiconductor 2, N
Trap 3 is located at 1 two sides of MRAM device and circuit, and deep N-well 4 is located at 1 lower section of MRAM device and circuit, and 3 bottom of N trap is connect with deep N-well 4
Together, three-dimensional N trap-deep N-well is formed to MRAM device and circuit 1 to be isolated.
The present embodiment is formd by two parts N trap 3 and deep N-well 4 and is surrounded to MRAM device and the three-dimensional of circuit 1.By N trap
It is connected with System on Chip/SoC positive voltage V_DD, P type substrate connects ground wire when due to operation, in this way inside and outside N trap-deep N-well
P-N junction forms reverse bias, non-conductive, it is sufficient to completely cut off noise.
Embodiment 2
Fig. 5 shows a kind of MRAM chip being isolated using deep N-well, including MRAM array 1, reading circuit 2, P-type semiconductor
Substrate 3, N trap 4 and deep N-well 5.
P-type semiconductor substrate 2 is located at 2 lower section of MRAM array 1 and reading circuit；N trap 4 and deep N-well 5 are located at P-type semiconductor 3
It is interior.
N trap 4 is located at 1 periphery of MRAM array, and deep N-well 5 is located at 1 lower section of MRAM array, and 4 bottom of N trap and deep N-well 5 connect
It is connected together, three-dimensional N trap-deep N-well is formed to MRAM array 1 and is isolated.
N trap 4 is located at around reading circuit 2, and deep N-well 5 is located at 2 lower section of reading circuit, and 4 bottom of N trap is connected to deep N-well 5
Together, three-dimensional N trap-deep N-well is formed to reading circuit 2 to be isolated.
MRAM array and reading circuit are isolated respectively using three-dimensional N trap-deep N-well isolation in the embodiment of the present invention, into
One step completely cuts off influence of the periphery high-speed digital circuit to MRAM chip, improves MRAM chip and reads stability.
The preferred embodiment of the present invention has been described in detail above.It should be appreciated that the ordinary skill of this field is without wound
The property made labour, which according to the present invention can conceive, makes many modifications and variations.Therefore, all technician in the art
Pass through the available technology of logical analysis, reasoning, or a limited experiment on the basis of existing technology under this invention's idea
Scheme, all should be within the scope of protection determined by the claims.
Claims (2)
1. a kind of MRAM chip being isolated using deep N-well, the MRAM chip includes MRAM device and circuit, P-type semiconductor lining
Bottom, N trap and deep N-well, which is characterized in that
The P-type semiconductor substrate is located at below the MRAM device and circuit；
The N trap and the deep N-well are located in the P-type semiconductor；
The N trap is located at the MRAM device and circuit peripheral, and the deep N-well is located at below the MRAM device and circuit, institute
It states N trap bottom to link together with the deep N-well, three-dimensional N trap-deep N-well is formed to the MRAM device and circuit and is isolated.
2. a kind of MRAM chip being isolated using deep N-well, the MRAM chip includes MRAM array, reading circuit, P-type semiconductor lining
Bottom, N trap and deep N-well, which is characterized in that
The P-type semiconductor substrate is located at below the MRAM array and the reading circuit；
The N trap and the deep N-well are located in the P-type semiconductor；
The N trap is located at the MRAM array periphery, and the deep N-well is located at below the MRAM array, N trap bottom and institute
It states deep N-well to link together, the formation MRAM array three-dimensional N trap-deep N-well is isolated；
The N trap is located at around the reading circuit, and the deep N-well is located at below the reading circuit, N trap bottom and institute
It states deep N-well to link together, three-dimensional N trap-deep N-well is formed to the reading circuit and is isolated.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201711250206.XA CN109873008A (en) | 2017-12-01 | 2017-12-01 | A kind of MRAM chip being isolated using deep N-well |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201711250206.XA CN109873008A (en) | 2017-12-01 | 2017-12-01 | A kind of MRAM chip being isolated using deep N-well |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN109873008A true CN109873008A (en) | 2019-06-11 |
Family
ID=66913662
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201711250206.XA Pending CN109873008A (en) | 2017-12-01 | 2017-12-01 | A kind of MRAM chip being isolated using deep N-well |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN109873008A (en) |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20060291115A1 (en) * | 2005-06-23 | 2006-12-28 | Samsung Electronics Co., Ltd. | Semiconductor integrated circuit device and method of fabricating the same |
| CN101452886A (en) * | 2007-12-07 | 2009-06-10 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor device and method for forming the same |
| CN103594107A (en) * | 2012-08-17 | 2014-02-19 | 三星电子株式会社 | Architecture of magneto-resistive memory device |
-
2017
- 2017-12-01 CN CN201711250206.XA patent/CN109873008A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20060291115A1 (en) * | 2005-06-23 | 2006-12-28 | Samsung Electronics Co., Ltd. | Semiconductor integrated circuit device and method of fabricating the same |
| CN101452886A (en) * | 2007-12-07 | 2009-06-10 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor device and method for forming the same |
| CN103594107A (en) * | 2012-08-17 | 2014-02-19 | 三星电子株式会社 | Architecture of magneto-resistive memory device |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| Kawahara et al. | 2 Mb SPRAM (SPin-transfer torque RAM) with bit-by-bit bi-directional current write and parallelizing-direction current read | |
| TWI445000B (en) | Semiconductor device | |
| CN104051001A (en) | Source line floating circuits, memory devices including the same and methods of reading data in a memory device | |
| TW201701285A (en) | Spin torque magnetic integrated circuits and method of fabricating the same | |
| WO2015083754A1 (en) | Semiconductor storage device using stt-mram | |
| CN105917411A (en) | Multi-level cell designs for high density low power gshe-stt mram | |
| US8270207B2 (en) | Raising programming current of magnetic tunnel junctions by applying P-sub bias and adjusting threshold voltage | |
| CN105741864B (en) | A kind of sense amplifier and MRAM chip | |
| Zhang et al. | A 16 Kb spin-transfer torque random access memory with self-enable switching and precharge sensing schemes | |
| Hanyu et al. | Spintronics-based nonvolatile logic-in-memory architecture towards an ultra-low-power and highly reliable VLSI computing paradigm | |
| US9318178B2 (en) | Semiconductor storage device and data processing method | |
| JP5488833B2 (en) | MRAM mixed loading system | |
| CN105761745B (en) | A kind of sense amplifier and MRAM chip | |
| CN109859784A (en) | A kind of array structure of MRAM chip | |
| US10311931B2 (en) | Semiconductor memory device | |
| US7280388B2 (en) | MRAM with a write driver and method therefor | |
| CN109873008A (en) | A kind of MRAM chip being isolated using deep N-well | |
| CN109817253A (en) | A kind of MRAM chip controlling bulk potential | |
| KR102523714B1 (en) | Memory device | |
| CN108182957A (en) | A kind of MRAM reading circuits using reference voltage | |
| CN110136760B (en) | MRAM chip | |
| Takemura et al. | 32-mb 2t1r spram with localized bi-directional write driver and ‘1’/‘0’dual-array equalized reference cell | |
| TW202027079A (en) | Switched source lines for memory applications | |
| CN108133725A (en) | A kind of MRAM reading circuits using action of low-voltage pulse | |
| CN109873009A (en) | A kind of MRAM chip using ground connection dummy argument |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| RJ01 | Rejection of invention patent application after publication | ||
| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20190611 |