CN109872699B - Shift register, gate drive circuit and display device - Google Patents
Shift register, gate drive circuit and display device Download PDFInfo
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- CN109872699B CN109872699B CN201910299331.2A CN201910299331A CN109872699B CN 109872699 B CN109872699 B CN 109872699B CN 201910299331 A CN201910299331 A CN 201910299331A CN 109872699 B CN109872699 B CN 109872699B
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Abstract
The present disclosure provides a shift register, including: the pre-charging module is used for charging the pull-up node in a pre-charging stage; the pull-up module is used for transmitting the clock signal output by the clock signal end to the first output end and the second output end in the output stage; the reset module is used for communicating the first power supply with the pull-up node in a reset stage so as to reset the pull-up node; the pull-down control module is used for writing a second power supply signal into the first pull-down node under the control of the second power supply signal output by the second power supply in the noise reduction stage; and the noise reduction module is used for writing a third power supply signal output by a third power supply into the pull-up node under the control of the second power supply signal output by the first pull-down node in the noise reduction stage, so that the pull-up module does not work under the control of the third power supply signal output by the pull-up node in the noise reduction stage. The disclosure also provides a gate driving circuit and a display device.
Description
Technical Field
The embodiment of the disclosure relates to the technical field of display, in particular to a shift register, a gate driving circuit and a display device.
Background
In the display process of the liquid crystal display panel, the grid driving circuit is used for generating grid scanning voltage of pixels, outputting grid scanning signals through the grid driving circuit and scanning pixels in each row line by line. The Gate Driver On Array (GOA) is a technology that integrates a Gate Driver circuit On a TFT substrate, and each GOA unit is used as a shift register to sequentially transmit a scanning signal to a next GOA unit, and turns On TFT switches corresponding to pixels in each row line by line to complete data signal input of the pixel unit.
Disclosure of Invention
The embodiment of the disclosure provides a shift register, a gate driving circuit and a display device.
In a first aspect, an embodiment of the present disclosure provides a shift register, including:
the pre-charging module is connected with the signal input end and the pull-up node and is used for charging the pull-up node under the control of an input signal output by the signal input end in a pre-charging stage;
a pull-up module, connected to the pull-up node, the clock signal terminal, the first output terminal and the second output terminal, for transmitting the clock signal output by the clock signal terminal to the first output terminal and the second output terminal under the control of the voltage output by the pull-up node in an output stage;
the reset module is connected with a reset signal end, a first power supply and the pull-up node and is used for communicating the first power supply with the pull-up node under the control of a reset signal output by the reset signal end in a reset stage so as to reset the pull-up node;
the pull-down control module is connected with a second power supply and a first pull-down node and is used for writing a second power supply signal into the first pull-down node under the control of the second power supply signal output by the second power supply in a noise reduction stage;
and the noise reduction module is connected with the pull-up node, the first pull-down node and the third power supply and is used for writing a third power supply signal output by the third power supply into the pull-up node under the control of a second power supply signal output by the first pull-down node in a noise reduction stage so that the pull-up module does not work under the control of the third power supply signal output by the pull-up node in the noise reduction stage.
In some embodiments, the pre-charge module includes a first transistor having a first pole and a control pole both connected to the signal input, and a second pole connected to the pull-up node.
In some embodiments, the reset module includes a second transistor, a control electrode of the second transistor is connected to the reset signal terminal, a first electrode of the second transistor is connected to the pull-up node, and a second electrode of the second transistor is connected to the first power supply.
In some embodiments, the pull-up module includes a third transistor, a fifteenth transistor, and a capacitor;
a first pole of the third transistor is connected to the clock signal terminal, a second pole of the third transistor is connected to the second output terminal, and a control pole of the third transistor is connected to the pull-up node;
a first pole of the fifteenth transistor is connected to the clock signal terminal, a second pole of the fifteenth transistor is connected to the first output terminal, and a control pole of the fifteenth transistor is connected to the pull-up node;
the first end of the capacitor is connected to the pull-up node, and the second end of the capacitor is connected to the second output end.
In some embodiments, the noise reduction module includes a sixteenth transistor having a first pole connected to the third power source, a second pole connected to the pull-up node, and a control pole connected to the first pull-down node.
In some embodiments, the noise reduction module is further connected to the first power supply, the first output, the second output, and a fourth power supply;
and the noise reduction module is further configured to, in a noise reduction stage, write a first power signal output by the first power supply into the pull-up node and the first output terminal under control of a second power signal output by the first pull-down node, and write a fourth power signal output by the fourth power supply into the second output terminal.
In some embodiments, the noise reduction module further comprises a tenth transistor, a twelfth transistor, and a thirteenth transistor;
a first pole of the tenth transistor is connected to the pull-up node, a second pole of the tenth transistor is connected to the first power source, and a control pole of the tenth transistor is connected to the first pull-down node;
a first pole of the twelfth transistor is connected to the first output terminal, a second pole of the twelfth transistor is connected to the first power supply, and a control pole of the twelfth transistor is connected to the first pull-down node;
a first pole of the thirteenth transistor is connected to the second output terminal, a second pole of the thirteenth transistor is connected to the fourth power supply, and a control pole of the thirteenth transistor is connected to the first pull-down node.
In some embodiments, the shift register further comprises:
and the pull-down module is connected with the pull-up node, the first power supply, the first pull-down node and the second pull-down node, and is used for writing a first power supply signal output by the first power supply into the first pull-down node and the second pull-down node under the control of the voltage output by the pull-up node in an output stage.
In some embodiments, the pull-down module includes a sixth transistor and an eighth transistor;
a first pole of the sixth transistor is connected to the first pull-down node, a second pole of the sixth transistor is connected to the first power supply, and a control pole of the sixth transistor is connected to the pull-up node;
a first pole of the eighth transistor is connected to the second pull-down node, a second pole of the eighth transistor is connected to the first power source, and a control pole of the eighth transistor is connected to the pull-up node.
In some embodiments, the pull-down control module is further connected to a second pull-down node, the pull-down control module including a fifth transistor and a ninth transistor;
a first pole of the fifth transistor is connected to the first pull-down node, a second pole of the fifth transistor is connected to the second power supply, and a control pole of the fifth transistor is connected to the second pull-down node;
a first electrode and a control electrode of the ninth transistor are respectively connected to the second power source, and a second electrode of the ninth transistor is connected to the second pull-down node.
In a second aspect, embodiments of the present disclosure also provide a gate driving circuit, including: the signal input end of the nth stage shift register except the first three stages of shift registers is connected with the first output end of the (n-3) th stage shift register, wherein m is greater than or equal to 4, and n is greater than 3 and less than or equal to m.
In a third aspect, an embodiment of the present disclosure further provides a display device, which includes the gate driving circuit described above.
Drawings
Fig. 1 is a schematic structural diagram of a shift register according to an embodiment of the present disclosure;
fig. 2 is a schematic diagram of a specific implementation manner of a shift register provided in an embodiment of the present disclosure;
fig. 3 is a timing diagram illustrating an operation of the shift register of fig. 2.
Detailed Description
In order to make those skilled in the art better understand the technical solutions of the present disclosure, the shift register, the gate driving circuit and the display device provided in the present disclosure are described in detail below with reference to the accompanying drawings.
Fig. 1 is a schematic structural diagram of a shift register according to an embodiment of the present disclosure, and as shown in fig. 1, the shift register includes: the device comprises a pre-charging module 1, an upward-pulling module 2, a resetting module 3, a downward-pulling control module 4 and a noise reduction module 5.
The pre-charging module 1 is connected to the signal INPUT terminal INPUT and the pull-up node PU, and is configured to charge the pull-up node PU in a pre-charging phase under control of an INPUT signal output by the signal INPUT terminal INPUT.
The pull-up module 2 is connected to the pull-up node PU, the clock signal terminal CLK, the first OUTPUT terminal OC, and the second OUTPUT terminal OUTPUT, and is configured to transmit the clock signal OUTPUT by the clock signal terminal CLK to the first OUTPUT terminal OC and the second OUTPUT terminal OUTPUT under control of the voltage OUTPUT by the pull-up node PU at the OUTPUT stage.
The Reset module 3 is connected to the Reset signal terminal Reset, the first power supply G1 and the pull-up node PU, and is configured to communicate the first power supply G1 with the pull-up node PU under the control of a Reset signal output by the Reset signal terminal Reset in a Reset phase, so as to Reset the pull-up node PU.
The pull-down control module 4 is connected to the second power supply G2 and the first pull-down node PD, and is used for outputting the second power signal V from the second power supply G2 during the noise reduction stageGHUnder the control of (3), the second power supply signal V is appliedGHThe first pull-down node PD is written.
The noise reduction module 5 is connected to the pull-up node PU, the first pull-down node PD, and the third power supply G3, and configured to, in a noise reduction stage, control the second power supply signal output by the first pull-down node PD to output a third power supply signal V3GNWriting the pull-up node PU to enable the pull-up module 2 to output a third power supply signal V at the pull-up node PU in the noise reduction stageGNDoes not work under the control of (2).
In the embodiment of the present disclosure, the first output terminal is used for cascading signal input terminals of other shift registers to form a gate driving circuit, and the second output terminal is used for being connected to a gate scan line of the display device to transmit a gate driving signal. By arranging the first output end and the second output end, the pixel is separated from the grid driving circuit, the load corresponding to each output end of the grid driving circuit is reduced, the size of a related transistor can be further reduced, and the power consumption of the grid driving circuit is reduced.
On the other hand, in the noise reduction stage of the current frame, due to external or internal reasons, if the pull-up node generates noise (lifting of the potential irregularity), the clock signal output by the clock signal terminal through the pull-up module cannot be completely output to the first output terminal in the normal output stage of the next frame, so that the charging difference between pixel rows results in poor display horizontal stripes, or the pixel rows are mistakenly charged, resulting in poor display horizontal black lines. Therefore, in the embodiment of the present disclosure, in the noise reduction stage, under the control of the second power signal output by the first pull-down node, the noise reduction module writes the third power signal output by the third power source into the pull-up node, so that the pull-up module does not operate under the control of the third power signal output by the pull-up node in the noise reduction stage, thereby effectively avoiding a problem that the clock signal output by the clock signal terminal in the normal output stage of the next frame cannot be completely output to the first output terminal due to noise (irregular rise of potential) generated by the pull-up node in the noise reduction stage of the current frame, and avoiding poor display horizontal stripes caused by charging differences between pixel rows or poor display horizontal black lines caused by mis-charging between pixel rows.
In the embodiment of the disclosure, in the pre-charge stage, the pre-charge module 1 charges the pull-up node PU under the control of the INPUT signal output from the signal INPUT terminal INPUT to pull up the potential of the pull-up node PU to the first voltage V1.
In the embodiment of the present disclosure, the pull-up module 2 is specifically configured to, in the OUTPUT stage, transmit the clock signal OUTPUT by the clock signal terminal CLK to the first OUTPUT terminal OC and the second OUTPUT terminal OUTPUT under the control of the first voltage OUTPUT by the pull-up node PU, and at the same time, further pull up the potential of the pull-up node PU to a second voltage V2, where the second voltage is greater than the first voltage.
In some embodiments, as shown in fig. 1, the shift register further includes a pull-down module 6, the pull-down module 6 is connected to the pull-up node PU, the first power supply G1, the first pull-down node PD and the second pull-down node PD _ CN, and is configured to output the first power signal V1 outputted by the first power supply G1 under the control of the voltage outputted by the pull-up node PU during the output phaseGL1And writing the first pull-down node PD and the second pull-down node PD _ CN. In this case, the voltage output by the pull-up node PU is the second voltage V2.
In some embodiments, as shown in fig. 1, the pull-down control module 4 is further connected to the second pull-down node PD _ CN, and the pull-down control module 4 is further configured to output the second power signal V at the second power supply G2 during the noise reduction phaseGHUnder the control of (3), the second power supply signal V is appliedGHWrite second Pull-Down node PD _ CN。
In some embodiments, as shown in fig. 1, the noise reduction module 5 is further connected to a first power supply G1, a first OUTPUT terminal OC, a second OUTPUT terminal OUTPUT, and a fourth power supply G4. The noise reduction module 5 is further configured to output the second power signal V at the first pull-down node PD during the noise reduction phaseGHUnder the control of (3), a first power supply signal V output by a first power supply G1GL1Writing the pull-up node PU and the first output terminal OC, and outputting a fourth power supply signal V from a fourth power supply G4GL2And writing the second OUTPUT end OUTPUT to reduce noise of the pull-up node PU, the first OUTPUT end OC and the second OUTPUT end OUTPUT.
Fig. 2 is a schematic diagram of a specific implementation manner of the shift register provided in the embodiment of the present disclosure, in some embodiments, as shown in fig. 2, the pre-charge module 1 includes a first transistor M1, a first pole and a control pole of the first transistor M1 are both connected to the signal INPUT terminal INPUT, and a second pole of the first transistor M1 is connected to the pull-up node PU.
In some embodiments, as shown in fig. 2, the Reset module 3 includes a second transistor M2, a control electrode of the second transistor M2 is connected to the Reset signal terminal Reset, a first electrode of the second transistor M2 is connected to the pull-up node PU, and a second electrode of the second transistor M2 is connected to the first power supply G1.
In some embodiments, as shown in fig. 2, the pull-up module 2 includes a third transistor M3, a fifteenth transistor M15, and a capacitor C1.
A first pole of the third transistor M3 is connected to the clock signal terminal CLK, a second pole of the third transistor M3 is connected to the second OUTPUT terminal OUTPUT, and a control pole of the third transistor M3 is connected to the pull-up node PU; a first pole of the fifteenth transistor M15 is connected to the clock signal terminal CLK, a second pole of the fifteenth transistor M15 is connected to the first output terminal OC, and a control pole of the fifteenth transistor M15 is connected to the pull-up node PU; a first terminal of the capacitor C1 is connected to the pull-up node PU, and a second terminal of the capacitor C1 is connected to the second OUTPUT terminal OUTPUT.
In some embodiments, as shown in FIG. 2, the noise reduction module 5 includes a sixteenth transistor M16, a first pole of the sixteenth transistor M16 is connected to the third power source G3, a second pole of the sixteenth transistor M16 is connected to the pull-up node PU, and a control pole of the sixteenth transistor M16 is connected to the first pull-down node PD. It will be understood that the second pole of the sixteenth transistor M16 is connected to the control pole of the fifteenth transistor M15 in the pull-up module 2.
In some embodiments, as shown in FIG. 2, the noise reduction module 5 further includes a tenth transistor M10, a twelfth transistor M12, and a thirteenth transistor M13.
Wherein a first pole of the tenth transistor M10 is connected to the pull-up node PU, a second pole of the tenth transistor M10 is connected to the first power supply G1, and a control pole of the tenth transistor M10 is connected to the first pull-down node PD; a first pole of the twelfth transistor M12 is connected to the first output terminal OC, a second pole of the twelfth transistor M12 is connected to the first power supply G1, and a control pole of the twelfth transistor M12 is connected to the first pull-down node PD; a first pole of the thirteenth transistor M13 is connected to the second OUTPUT terminal OUTPUT, a second pole of the thirteenth transistor M13 is connected to the fourth power supply G4, and a control pole of the thirteenth transistor M13 is connected to the first pull-down node PD.
In some embodiments, as shown in fig. 2, the pull-down module 6 includes a sixth transistor M6 and an eighth transistor M8.
Wherein a first pole of the sixth transistor M6 is connected to the first pull-down node PD, a second pole of the sixth transistor M6 is connected to the first power supply G1, and a control pole of the sixth transistor M6 is connected to the pull-up node PU; a first electrode of the eighth transistor M8 is connected to the second pull-down node PD _ CN, a second electrode of the eighth transistor M8 is connected to the first power supply G1, and a control electrode of the eighth transistor M8 is connected to the pull-up node PU.
In some embodiments, as shown in FIG. 2, the pull-down control module 4 includes a fifth transistor M5 and a ninth transistor M9.
Wherein a first pole of the fifth transistor M5 is connected to the first pull-down node PD, a second pole of the fifth transistor M5 is connected to the second power supply G2, and a control pole of the fifth transistor M5 is connected to the second pull-down node PD _ CN; a first pole and a control pole of the ninth transistor M9 are connected to the second power supply G2, respectively, and a second pole of the ninth transistor M9 is connected to the second pull-down node PD _ CN.
Fig. 3 is an operation timing diagram of the shift register in fig. 2, and the operation principle of the shift register provided by the embodiment of the present disclosure is described in detail below with reference to fig. 2 and fig. 3.
In practical applications, the shift register in the embodiments of the present disclosure may form the gate driving circuit in a cascade manner. In some embodiments, the gate driving circuit is formed by cascading m shift registers, except for the previous three stages of shift registers, a signal input end of the nth stage shift register is connected with a first output end of the (n-3) th stage shift register, where m and n are positive integers, m is greater than or equal to 4, and n is greater than or equal to 3 and less than or equal to m. The grid driving circuit is applied to a display device and used for scanning grid scanning lines of the display device line by line so as to write data signals into pixels to realize display.
The working principle of the shift register provided by the embodiment of the present disclosure is described in detail by taking the shift register as the nth stage shift register as an example.
For the nth stage shift register, as shown in fig. 2 and 3, in the precharge phase T1, the first transistor M1 is turned on under the control of the INPUT signal output from the signal INPUT terminal INPUT, which is a high level signal. In some embodiments, the INPUT signal output by the signal INPUT terminal INPUT is an output signal output by the first output terminal OC (n-3) of the shift register of the (n-3) th stage, and the output signal output by the first output terminal OC (n-3) of the shift register of the (n-3) th stage is a high level signal.
At this time, the INPUT signal output from the signal INPUT terminal INPUT is written into the pull-up node PU through the turned-on first transistor M1, so that the potential of the pull-up node PU is pulled up to the first voltage V1 to charge the capacitor C1. Meanwhile, in the precharge phase T1, since the voltage of the pull-up node PU is pulled high, so that the sixth transistor M6 and the eighth transistor M8 are turned on under the control of the voltage (the first voltage V1) output by the pull-up node, the first power signal V output by the first power supply G1GL1The first power signal V outputted from the first power supply G1 is written into the first pull-down node PD through the turned-on sixth transistor M6GL1Through the turned-on eighth transistorM8 is written into the second pull-down node PD _ CN, wherein the first power supply signal V outputted by the first power supply G1GL1Is a low level signal, for example, -8V, to pull down the potential of the first pull-down node PD and the potential of the second pull-down node PD _ CN.
On the other hand, in the precharge period T1, the third transistor M3 and the fifteenth transistor M15 are turned on under the control of the voltage (the first voltage V1) OUTPUT from the pull-up node PU, but since the clock signal OUTPUT from the clock signal terminal CLK is a low level signal, both the first OUTPUT terminal OC and the second OUTPUT terminal OUTPUT a low level signal.
In the OUTPUT stage T2, the INPUT signal OUTPUT by the signal INPUT terminal INPUT is a low level signal, the first transistor M1 is turned off, the third transistor M3 is turned on under the control of the voltage (the first voltage V1) OUTPUT by the pull-up node PU, the fifteenth transistor M15 is turned on under the control of the voltage (the first voltage V1) OUTPUT by the pull-up node PU, the clock signal OUTPUT by the clock signal terminal CLK is transmitted to the first OUTPUT terminal OC through the turned-on fifteenth transistor M15, and the clock signal OUTPUT by the clock signal terminal CLK is transmitted to the second OUTPUT terminal OUTPUT through the turned-on third transistor M3, wherein the first voltage V1 is a high level signal and the clock signal OUTPUT by the clock signal terminal CLK is a high level signal. At this time, the first OUTPUT terminal OC OUTPUTs the clock signal (high level signal) to the signal input terminal of the cascaded shift register, and the second OUTPUT terminal OUTPUT OUTPUTs the clock signal (high level signal) to the gate scan line connected thereto, thereby realizing the cascade OUTPUT of the gate driving circuit and the display OUTPUT of the pixel region.
Meanwhile, in the OUTPUT stage T2, since the clock signal (high level signal) outputted from the clock signal terminal CLK is written into the second terminal (second OUTPUT terminal OUTPUT) of the capacitor C1 through the turned-on third transistor M3, the potential of the first terminal (pull-up node PU) of the capacitor C1 is further pulled up under the effect of the bootstrap effect of the capacitor C1, and at this time, the potential of the pull-up node PU is pulled up to the second voltage V2, where the second voltage V2 is a high level signal. Meanwhile, in the output stage T2, since the potential of the pull-up node PU continues to be raised, the sixth transistor M6 and the eighth transistor M8 are kept in a conducting state under the control of the voltage (the second voltage V2) output by the pull-up node PU, so that the first power VGL1 continuously writes the first power signal (low level signal) to the first pull-down node PD, that is, the first pull-down node PD keeps in a low level signal output state.
In the Reset period T3, the second transistor M2 is turned on under the control of a Reset signal output from the Reset signal terminal Reset, wherein the Reset signal is a high level signal. At this time, the pull-up node PU is connected to the first power supply G1 through the turned-on second transistor M2, and the first power supply G1 outputs the first power signal VGL1(Low level signal) is written into the pull-up node PU, and the potential of the pull-up node PU is pulled down to the first power supply signal VGL1Thereby, the reset of the pull-up node PU is realized. At this time, the sixth transistor M6 and the eighth transistor M8 are turned off.
In the noise reduction stage, the ninth transistor M9 outputs the second power signal V from the second power supply G2GHIs turned on under the control of (b), wherein the second power signal VGHIs a high level signal. At this time, the second power signal V output by the second power supply G2GH(high level signal) is written into the second pull-down node PD _ CN through the turned-on ninth transistor M9, the potential of the second pull-down node PD _ CN is pulled high, and the voltage (the second power supply signal V) output at the second pull-down node PD _ CN by the fifth transistor M5GH) Is turned on, and the second power signal V output by the second power supply G2GHThe (high level signal) is written into the first pull-down node PD through the turned-on fifth transistor M5, and at this time, the potential of the first pull-down node PD is pulled high, and the first pull-down node PD outputs a high level signal.
Meanwhile, the tenth transistor M10 is turned on under the control of the voltage (high level signal) output from the first pull-down node PD, the pull-up node PU is connected to the first power supply G1 through the turned-on tenth transistor M10, and the first power supply signal V output from the first power supply G1GL1Writing the pull-up node PU into the write-in unit, so as to reduce noise of the pull-up node PU; meanwhile, the twelfth transistor M12 is turned on under the control of the voltage (high level signal) output from the first pull-down node PD, the first output terminal OC and the first power supply G1 are connected through the turned-on twelfth transistor M12, and the first power supply signal V output from the first power supply G1 isGL1Writing inA first output terminal OC, thereby denoising the first output terminal OC; meanwhile, the thirteenth transistor M13 is turned on under the control of the voltage (high level signal) OUTPUT from the first pull-down node PD, the second OUTPUT terminal OUTPUT and the fourth power supply G4 are connected through the turned-on thirteenth transistor M13, and the fourth power supply G4 OUTPUTs the fourth power supply signal VGL2Writing the second OUTPUT terminal OUTPUT to reduce noise of the second OUTPUT terminal OUTPUT, wherein the fourth power signal VGL2Is a low level signal, a fourth power supply signal VGL2Is less than the first power supply signal VGL1E.g. VGL2＝-10V，VGL1-8V. At this time, the voltage V of the first output terminal OCOCFirst power supply signal V of first power supply outputGL1Voltage V of second OUTPUT terminal OUTPUTOUTPUTFourth power supply signal V equal to fourth power supply outputGL2。
Meanwhile, the sixteenth transistor M16 is turned on under the control of the voltage (high level signal) output from the first pull-down node PD, and the third power signal V output from the third power supply G3GNThe noise of the pull-up node PU is further reduced by writing the turned-on sixteenth transistor M16 into the gate (pull-up node PU) of the fifteenth transistor M15, and at this time, the voltage V of the gate of the fifteenth transistor M15g＝VGN＝VPU，VPUTo pull up the voltage of the node PU, the voltage V of the second pole of the fifteenth transistor M15s＝VOC＝VGL1Wherein the third power supply G3 outputs a third power supply signal VGNEqual to the fourth power supply signal V output by the fourth power supply G4GL2Therefore, the gate-source voltage V of the fifteenth transistor M15gs＝Vg-Vs＝VGN-VGL1＝VGL2-VGL1<Vth0, wherein VthIs the threshold voltage of the fifteenth transistor M15, at this time, the fifteenth transistor M15 is in an off state (not operating). Therefore, in the noise reduction period T4, the potential at the first pull-down node PD is in a high level signal state as long as the third power supply G3 continues to output the third power supply signal V through the turned-on sixteenth transistor M16GNTo the gate of the fifteenth transistor M15, the fifteenth crystalThe transistor M15 will be completely turned off, so that the leakage drift problem of the fifteenth transistor M15 during the noise reduction stage can be effectively solved.
In addition, if the sixteenth transistor M16 is not provided, in the noise reduction stage T4, the potential of the pull-up node PU is theoretically at a low level (V) due to the action of the tenth transistor M10GL1) However, due to the fact that the clock signal terminal CLK outputs a periodic square wave signal and continues to output, and the bootstrap effect of the capacitor formed between the control electrode and the first electrode (or between the control electrode and the second electrode) of the third transistor M3 is added, the pull-up node PU generates very small noise, that is, the potential of the pull-up node PU rises irregularly, which inevitably causes the gate-source voltage V of the fifteenth transistor M15 to rise irregularly during the noise reduction stage of the fifteenth transistor M15 due to the irregular rise of the potential of the pull-up node PUgs＝Vg-Vs＝VPU-VGL1＞0，VPUIn order to pull up the voltage at the node PU, the fifteenth transistor M15 in this state will have its threshold voltage VthThe drift occurs, the M15 has the problem of drift leakage, and the size of the fifteenth transistor M15 is generally small and the threshold voltage V is small due to the difference between the load sizes of the pixel region and the gate driving circuit region and the requirement of the narrow frame of the display devicethAfter the drift is generated, the voltage output by the clock signal end can not be completely output to the first output end OC at the normal output stage of the next frame, so that the charging difference between lines is easily caused, the display horizontal stripe is poor, or the wrong charging between lines is caused, and the display horizontal black line is poor.
Therefore, in the embodiment of the present disclosure, the sixteenth transistor M16 is disposed in the noise reduction module 5, and is configured to write the third power signal output by the third power supply into the gate of the fifteenth transistor M15 of the pull-up module 2 under the control of the voltage output by the first pull-down node PD during the noise reduction stage, and control the fifteenth transistor M15 not to operate (turn off), so as to effectively prevent the clock signal output by the clock signal terminal during the normal output stage of the next frame from being completely output to the first output terminal, and avoid the display horizontal stripe defect caused by the charging difference between pixel rows or the display horizontal black line defect caused by the pixel row mischarging.
In the embodiment of the present disclosure, the number of the pull-down control modules 4 is 1 or 2, and the number of the pull-down modules 6 is 1 or 2. Fig. 2 only shows the case where the number of the pull-down control modules 4 is 1 and the number of the pull-down modules 6 is 1, in which case, referring to fig. 3, the second power signal V outputted by the second power G2GHIs a periodic square wave signal, therefore, during the noise reduction period T4, the voltage of the pull-down node PD and the second power signal VGHThe same is a periodic square wave signal, that is, in the noise reduction stage, the pull-down node PD is in a high level state for half of the time.
When the number of the pull-down control modules 4 is 2 and the number of the pull-down modules 6 is 2, the second power signal V output by the second power G2 corresponding to one pull-down control module 4GHThe second power signal V output by the second power G2 corresponding to another pull-down control module 4 is the periodic square wave signal shown in fig. 3GHV as shown in FIG. 3GHThe signals of (1) are opposite. Therefore, through the control of the two pull-down control modules 4, the pull-down node PD can be always in the high state during the noise reduction period T4, i.e. the state shown in fig. 3.
In the embodiment of the present disclosure, the shift register repeats the noise reduction stage and continues the noise reduction process until the next frame of picture is displayed.
In the embodiment of the disclosure, as shown in fig. 2, the Reset module 3 further includes a seventh transistor M7, a first pole of the seventh transistor M7 is connected to the pull-up node PU, a second pole of the seventh transistor M7 is connected to the first power supply G1, a control pole of the seventh transistor M7 is connected to the initialization signal terminal TRST, the seventh transistor M7 is configured to implement a Total Reset function, when each frame is turned on (before the first row of pixels is scanned), the seventh transistor M7 is turned on under the control of the initialization signal output by the initialization signal terminal TRST, where the initialization signal is a high level signal, the first power supply G1 and the pull-up node PU are connected through the turned-on seventh transistor M7, and the first power supply signal V output by the first power supply G1GL1Writing in pull-up node PU to pull-up nodePU and output noise reduction.
In the embodiment of the present disclosure, the fourth power supply G4 is further configured to implement an XON function, wherein the fourth power supply signal V output by the fourth power supply G4 is used to repeatedly switch on and offGL2Set high, at the same time, the thirteenth transistor M13 is turned on, and the gate scan line of each row is turned on through the OUTPUT of the second OUTPUT terminal OUTPUT, thereby achieving the function of discharging noise (DC) and static electricity in the pixel.
In the shift register provided by the embodiment of the disclosure, the noise reduction module writes a third power signal output by a third power source into the pull-up node under the control of a second power signal output by a first pull-down node in the noise reduction stage, so that the pull-up module does not work under the control of the third power signal output by the pull-up node in the noise reduction stage, thereby effectively avoiding the problem that a clock signal output by a clock signal terminal in the normal output stage of a next frame cannot be completely output to a first output terminal due to noise (lifting of an irregular potential) generated by the pull-up node in the noise reduction stage of a current frame, and avoiding poor display horizontal stripes caused by charging differences among pixel rows or poor display horizontal black lines caused by mischarging among pixel rows.
Correspondingly, the embodiment of the present disclosure further provides a gate driving circuit, which includes m cascaded shift registers, and except for the shift registers of the first three stages, a signal input terminal of the shift register of the nth stage is connected to the first output terminal of the shift register of the (n-3) th stage, where m is greater than or equal to 4, and n is greater than 3 and less than or equal to m.
For example, if m is 7, then except for the first stage shift register, the second stage shift register and the third stage shift register, let n be 4, starting from the nth stage shift register, the signal input terminal of the nth stage shift register is connected to the first output terminal of the (n-3) th stage shift register, the signal input terminal of the (n + 1) th stage shift register is connected to the first output terminal of the (n-2) th stage shift register, the signal input terminal of the (n + 2) th stage shift register is connected to the first output terminal of the (n-1) th stage shift register, …, and so on.
In the embodiment of the present disclosure, the gate driving circuit is a GOA circuit.
In the gate driving circuit provided in the embodiment of the present disclosure, the shift register includes the shift register described above, and specific description may refer to the description of the shift register described above, which is not repeated herein.
Accordingly, an embodiment of the present disclosure further provides a display device, which includes a gate driving circuit, where the gate driving circuit includes the gate driving circuit, and specific description may refer to the description of the gate driving circuit, and details are not repeated here.
It will be understood that the above embodiments are merely exemplary embodiments taken to illustrate the principles of the present invention, which is not limited thereto. It will be apparent to those skilled in the art that various modifications and improvements can be made without departing from the spirit and substance of the invention, and these modifications and improvements are also considered to be within the scope of the invention.
Claims (8)
1. A shift register, comprising:
the pre-charging module is connected with the signal input end and the pull-up node and is used for charging the pull-up node under the control of an input signal output by the signal input end in a pre-charging stage;
a pull-up module, connected to the pull-up node, the clock signal terminal, the first output terminal and the second output terminal, for transmitting the clock signal output by the clock signal terminal to the first output terminal and the second output terminal under the control of the voltage output by the pull-up node in an output stage;
the reset module is connected with a reset signal end, a first power supply and the pull-up node and is used for communicating the first power supply with the pull-up node under the control of a reset signal output by the reset signal end in a reset stage so as to reset the pull-up node;
the pull-down control module is connected with a second power supply and a first pull-down node and is used for writing a second power supply signal into the first pull-down node under the control of the second power supply signal output by the second power supply in a noise reduction stage;
a noise reduction module connected to the pull-up node, the first pull-down node, a third power supply, the first output terminal, the second output terminal, and a fourth power supply, for: in a noise reduction stage, under the control of a second power supply signal output by the first pull-down node, writing a third power supply signal output by a third power supply into the pull-up node, so that the pull-up module does not work under the control of the third power supply signal output by the pull-up node in the noise reduction stage; in a noise reduction stage, under the control of a second power supply signal output by the first pull-down node, writing a first power supply signal output by the first power supply into the pull-up node and the first output terminal, and writing a fourth power supply signal output by the fourth power supply into the second output terminal;
the pull-up module comprises a third transistor, a fifteenth transistor and a capacitor; a first pole of the third transistor is connected to the clock signal terminal, a second pole of the third transistor is connected to the second output terminal, and a control pole of the third transistor is connected to the pull-up node; a first pole of the fifteenth transistor is connected to the clock signal terminal, a second pole of the fifteenth transistor is connected to the first output terminal, and a control pole of the fifteenth transistor is connected to the pull-up node; a first end of the capacitor is connected to the pull-up node, and a second end of the capacitor is connected to the second output end;
the noise reduction module comprises a sixteenth transistor, a tenth transistor, a twelfth transistor and a thirteenth transistor; a first pole of the sixteenth transistor is connected to the third power supply, a second pole of the sixteenth transistor is connected to the pull-up node, and a control pole of the sixteenth transistor is connected to the first pull-down node; a first pole of the tenth transistor is connected to the pull-up node, a second pole of the tenth transistor is connected to the first power source, and a control pole of the tenth transistor is connected to the first pull-down node; a first pole of the twelfth transistor is connected to the first output terminal, a second pole of the twelfth transistor is connected to the first power supply, and a control pole of the twelfth transistor is connected to the first pull-down node; a first pole of the thirteenth transistor is connected to the second output terminal, a second pole of the thirteenth transistor is connected to the fourth power supply, and a control pole of the thirteenth transistor is connected to the first pull-down node.
2. The shift register of claim 1, wherein the precharge module comprises a first transistor having a first pole and a control pole connected to the signal input, and a second pole connected to the pull-up node.
3. The shift register according to claim 1, wherein the reset module includes a second transistor, a control electrode of the second transistor is connected to the reset signal terminal, a first electrode of the second transistor is connected to the pull-up node, and a second electrode of the second transistor is connected to the first power supply.
4. The shift register of claim 1, further comprising:
and the pull-down module is connected with the pull-up node, the first power supply, the first pull-down node and the second pull-down node, and is used for writing a first power supply signal output by the first power supply into the first pull-down node and the second pull-down node under the control of the voltage output by the pull-up node in an output stage.
5. The shift register of claim 4, wherein the pull-down module comprises a sixth transistor and an eighth transistor;
a first pole of the sixth transistor is connected to the first pull-down node, a second pole of the sixth transistor is connected to the first power supply, and a control pole of the sixth transistor is connected to the pull-up node;
a first pole of the eighth transistor is connected to the second pull-down node, a second pole of the eighth transistor is connected to the first power source, and a control pole of the eighth transistor is connected to the pull-up node.
6. The shift register of claim 1, wherein the pull-down control module is further connected to a second pull-down node, the pull-down control module comprising a fifth transistor and a ninth transistor;
a first pole of the fifth transistor is connected to the first pull-down node, a second pole of the fifth transistor is connected to the second power supply, and a control pole of the fifth transistor is connected to the second pull-down node;
a first electrode and a control electrode of the ninth transistor are respectively connected to the second power source, and a second electrode of the ninth transistor is connected to the second pull-down node.
7. A gate drive circuit, comprising: the m cascaded shift registers of any one of claims 1 to 6, wherein except the shift registers of the first three stages, a signal input terminal of the shift register of the nth stage is connected to a first output terminal of the shift register of the (n-3) th stage, wherein m is greater than or equal to 4, and n is greater than 3 and less than or equal to m.
8. A display device comprising the gate driver circuit according to claim 7.
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| CN110264971B (en) * | 2019-06-26 | 2022-01-04 | 京东方科技集团股份有限公司 | Anti-flash screen circuit and method, driving circuit and display device |
| CN110415664B (en) * | 2019-08-01 | 2021-10-08 | 京东方科技集团股份有限公司 | Shift register and driving method thereof, gate drive circuit and display device |
| CN110534052B (en) * | 2019-09-27 | 2023-04-18 | 京东方科技集团股份有限公司 | Shift register and driving method thereof, grid driving circuit and display device |
| CN110910850B (en) * | 2019-12-17 | 2022-06-07 | 京东方科技集团股份有限公司 | Shift register and driving method thereof, grid driving circuit and display device |
| US11961442B2 (en) | 2020-10-21 | 2024-04-16 | Boe Technology Group Co., Ltd. | Shift register unit, driving method, drive circuit, and display apparatus |
| US20220406244A1 (en) * | 2020-12-23 | 2022-12-22 | Boe Technology Group Co., Ltd. | Shift register and driving method thereof, gate driver and display device |
| CN113053446B (en) * | 2021-03-15 | 2024-08-20 | 京东方科技集团股份有限公司 | Shift register, driving circuit and display device |
| CN115019741B (en) * | 2022-04-19 | 2024-07-02 | 京东方科技集团股份有限公司 | Array grid driving unit, circuit, driving method and display device |
| CN115512672B (en) * | 2022-10-25 | 2023-10-27 | 业成科技（成都）有限公司 | Scan driving circuit and operation method thereof |
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| CN105810251A (en) * | 2016-04-08 | 2016-07-27 | 京东方科技集团股份有限公司 | Shift register, display substrate and display device |
| CN106057147B (en) * | 2016-06-28 | 2018-09-11 | 京东方科技集团股份有限公司 | Shift register cell and its driving method, gate driving circuit, display device |
| US10403382B2 (en) * | 2016-08-05 | 2019-09-03 | Hannstar Display Corporation | Gate driving circuit and display apparatus |
| CN106531052A (en) * | 2017-01-03 | 2017-03-22 | 京东方科技集团股份有限公司 | Shift register, gate drive circuit and display device |
| CN109952606A (en) * | 2017-05-08 | 2019-06-28 | 京东方科技集团股份有限公司 | The driving method of gate driving circuit, display device and gate driving circuit |
| CN108932933B (en) * | 2017-05-27 | 2020-01-21 | 京东方科技集团股份有限公司 | Shift register, grid drive circuit and display device |
| KR102348667B1 (en) * | 2017-06-15 | 2022-01-06 | 엘지디스플레이 주식회사 | Shift register and display apparatus comprising the same |
| CN107068106B (en) * | 2017-06-21 | 2019-06-07 | 京东方科技集团股份有限公司 | Shift register cell, driving method, gate driving circuit and display device |
| CN107123389B (en) * | 2017-07-03 | 2020-11-03 | 京东方科技集团股份有限公司 | Shift register, grid drive circuit and display device |
| CN107331418B (en) * | 2017-07-31 | 2020-06-19 | 京东方科技集团股份有限公司 | Shift register and driving method thereof, grid driving circuit and display device |
| CN107657983B (en) * | 2017-11-09 | 2024-03-26 | 京东方科技集团股份有限公司 | Shift register unit, driving method, grid driving circuit and display device |
| CN207409262U (en) * | 2017-11-09 | 2018-05-25 | 京东方科技集团股份有限公司 | Shift register cell, gate driving circuit and display device |
| CN107833552B (en) * | 2017-11-17 | 2020-09-25 | 合肥鑫晟光电科技有限公司 | Gate driving unit, gate driving circuit, driving method of gate driving circuit and display device |
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