CN109871059A - A kind of ultra low voltage LDO circuit - Google Patents
A kind of ultra low voltage LDO circuit Download PDFInfo
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- CN109871059A CN109871059A CN201910139295.3A CN201910139295A CN109871059A CN 109871059 A CN109871059 A CN 109871059A CN 201910139295 A CN201910139295 A CN 201910139295A CN 109871059 A CN109871059 A CN 109871059A
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Abstract
The present invention relates to a kind of ultra low voltage LDO circuits, including LDO circuit and power circuit；Power circuit external input power boosts to input voltage when input voltage is lower than the first predetermined reference voltage, obtains target voltage for receiving the input voltage of input power；When input voltage be higher than the first predetermined reference voltage when input voltage is successively carried out pressure stabilizing, boosting obtain target voltage, target voltage is finally input to LDO circuit；LDO circuit external input power and load obtain required voltage and are input to load for receiving and based on input voltage and target voltage.The present invention introduces lightweight in LDO circuit and locally generates power supply, it boosts when input supply voltage is lower to supply voltage, when input supply voltage is higher to supply voltage pressure stabilizing, realizing LDO circuit can work under ultralow or wide-voltage range working environment, ensure that low ripple and high PSRR while improving energy conversion efficiency.
Description
Technical field
The present invention relates to LDO technical fields, more particularly to a kind of ultra low voltage LDO circuit.
Background technique
With the high speed development of electronic equipment for consumption and Internet of Things, the power supply of higher efficiency, more small area, more low-power consumption
Managing chip has very big demand.Due to that circuit work can be made close the lower supply voltage of power management chip
Threshold voltage and subthreshold voltage area, a large amount of design is it can be proved that when lower than 0.5V power supply, dynamic power consumption and quiescent dissipation
It will all reduce, so that circuit obtains maximum energy conversion efficiency.Therefore, this means that the power supply for reducing these chips
The output voltage of voltage, i.e. LDO (low dropout regulator, low pressure difference linear voltage regulator), become very it is necessary to.
The output voltage for reducing LDO is the inexorable trend of integrated circuit technology processing procedure continuous development.According to international semiconductor
The report of industrial technology route (ITRS), when specified system on chip (SOC) designs supply voltage to 6nm technique, it will drop to
0.6V.The energy conversion efficiency for guaranteeing LDO reduces LDO while reducing chip supply voltage (output voltage of LDO)
Input supply voltage be very necessary.
In conventional power source management system, LDO from DC-DC there is different characteristics to play different roles.LDO is opposite
For DC-DC, there is smaller ripple and higher power supply rejection ratio, be more applicable for the module of level-sensitive, such as simulates
Module, radio-frequency module, digital analog converter, analog-digital converter, particularly, digit chip can also become when supply voltage is lower than 0.5V
It obtains to level-sensitive.And traditional simulation LDO, in error amplifier be difficult to work under lower input supply voltage,
If continuing to reduce output voltage when using the input supply voltage for meeting performance, energy conversion efficiency will be greatly reduced in this.
Recent domestic has a large amount of number LDO designs, proposes for this problem with comparator and shift register
Replace the design of error amplifier, this measure solves the problems, such as input supply voltage, but brings ripple increase, electricity again simultaneously
Source inhibits than reduced new problem, this is incongruent with the original intention for using LDO to power to chip.How LDO input is being reduced
Guarantee small ripple and high power supply rejection ratio while voltage, is a problem for needing to study at present.
Summary of the invention
The present invention provides a kind of ultra low voltage LDO circuit, cannot be compatible with to solve existing LDO circuit in low pressure output
The problem of low ripple, high PSRR and energy conversion efficiency.
The technical scheme to solve the above technical problems is that a kind of ultra low voltage LDO circuit, which is characterized in that
It include: LDO circuit and power circuit；The first input end of the input terminal of the power circuit and the LDO circuit is used to outer
Input power is connect, the output end of the power circuit is connect with the second input terminal of the LDO circuit；
The power circuit is for judging its received input voltage whether less than the first predetermined reference voltage, if so, right
The input voltage carries out more times of boosting processing, obtains first target voltage and is input to the LDO circuit；If it is not, to described
Input voltage successively carries out pressure stabilizing, more times of boosting processing, obtains the second target voltage and is input to the LDO circuit, wherein institute
It states first target voltage and second target voltage is used to as LDO circuit power supply；
The LDO circuit is used to be based on the second predetermined reference voltage, the input voltage received to its first input end
Processing obtains required voltage and is input to load.
The beneficial effects of the present invention are: the present invention introduces lightweight in LDO circuit locally generates power supply, supplied using two-way
Electricity, be all the way directly to LDO input voltage, another way be input voltage after lightweight locally generates power supply pressure stabilizing, boosting to
LDO power supply boosts to supply voltage that is, when the voltage of input power is lower, when input supply voltage is higher, to power supply electricity
Pressure stabilizing is pressed, realizing LDO circuit can work under ultralow or wide-voltage range working environment, even if in the load of LDO circuit
For ultra low voltage digital module or other modules sensitive to power supply electrical level, (such as ultra low voltage analog module, ultra low voltage are penetrated
Frequency module, ultra low voltage DAC/ADC etc.), can also work normally, ensure that while improving energy conversion efficiency low ripple with
High PSRR.
Based on the above technical solution, the present invention can also be improved as follows.
Further, the power circuit includes: steady voltage regulator circuit and booster circuit；
The steady voltage regulator circuit, input terminal is the input terminal of the power circuit, for judging its received input
Whether voltage is less than the first predetermined reference voltage, if so, the input voltage is input to the booster circuit；If it is not, to institute
The value pressure stabilizing of input voltage is stated to the value of first predetermined reference voltage, new input voltage is obtained and is input to the boosting
Circuit；
The booster circuit, output end is the output end of the power circuit, for defeated to the steady voltage regulator circuit
The input voltage entered carries out more times of boostings, obtains the first target voltage or second target voltage and is input to institute
State LDO circuit.
Further, the steady voltage regulator circuit includes: first error amplifier, the first power tube and the first feedback electricity
Hinder network；
The first error amplifier is used for the external input power, the grid company of output end and first power tube
It connects；The cathode of the first error amplifier connects first feedback resistive network or is used for external first preset reference
The power supply of voltage, power supply or connection first feedback resistive network of the anode for external first predetermined reference voltage；
The source electrode of first power tube or drain electrode are used for the external input power, and drain electrode or source electrode connect first feedback resistance
Network and the booster circuit；First feedback resistive network is also connected with the booster circuit.
Further, first power tube is weak output power pipe.
Further beneficial effect of the invention is: since the control section operating current requirement in LDO is smaller, and weak output
The electric current that power tube may make power circuit to be output to LDO circuit is smaller, guarantees that LDO electric current is stablized.
Further, when first power tube is PMOS tube, the cathode of the first error amplifier external described the
The power supply of two predetermined reference voltages, anode connect first feedback resistive network；The source electrode of first power tube is for outer
The input power is connect, drain electrode connects first feedback resistive network and is used for the external booster circuit；Described first is anti-
Feedback resistor network is also connected with the booster circuit；
When first power tube is NMOS tube, the cathode connection of the first error amplifier the first feedback electricity
Network is hindered, anode is used for the power supply of external first predetermined reference voltage；The drain electrode of first power tube is used for external institute
Input power is stated, source electrode connects first feedback resistive network and the booster circuit；First feedback resistive network is also
Connect the booster circuit.
Further, the booster circuit is specifically used for carrying out two to the input voltage of the steady voltage regulator circuit input
It boosts again, obtains the first target voltage or second target voltage and be input to the LDO circuit.
Further beneficial effect of the invention is: voltage regulator circuit can control booster circuit according to the first predetermined reference voltage
Input prevents target voltage to be higher than circuit caused by the rated operational voltage of LDO circuit to control the target voltage of output
Breakdown.The value of first predetermined reference voltage is related with rated operational voltage.In addition, boosting using two times, energy conversion can be improved
Efficiency.
Further, the booster circuit includes: the sharp charge pump of twice flesh side gram, and respectively with twice of flesh side gram benefit
The first storage capacitor, the second storage capacitor and the filter capacitor of charge pump connection；
The first input end of the sharp charge pump of twice of flesh side gram adjusts circuit connection with the pressure stabilizing, the second input terminal is
The output end of the power circuit is obtained for carrying out two times of boostings to the input voltage of the steady voltage regulator circuit input
To the first target voltage or second target voltage and it is input to the LDO circuit；
First storage capacitor and second storage capacitor are also used to external asynchronous square-wave pulse modulation circuit,
To store the square wave information of two asynchronous pulse square waves of the asynchronous square-wave pulse modulation circuit input, twice of skin is assisted
Li Keli charge pump carries out boost operations；
The filter capacitor is also connect with the LDO circuit, for eliminating the first target voltage and second mesh
Mark the burr and ripple of voltage.
Further beneficial effect of the invention is: using the sharp charge pump of flesh side gram, minimum input voltage standard can be reduced,
Improve operating voltage range.
Further, the peak value of described two asynchronous pulse square waves is equal with the value of the input voltage of the input power.
Further, the LDO circuit includes: the second error amplifier, the second power tube and the second feedback resistance net
Network；
The input terminal of second error amplifier is the second input terminal of the LDO circuit, output end and described second
The grid of power tube connects；The cathode of second error amplifier connects second feedback resistive network and for external the
The power supply of two predetermined reference voltages, power supply or connection first feedback resistance of the anode for external second predetermined reference voltage
Network；The source electrode of second power tube or drain electrode are the first input end of the LDO circuit, drain electrode or source electrode connection described the
Two feedback resistive networks are simultaneously used for the external load；Second feedback resistive network is also used to the external load.
Further, when second power tube is PMOS tube, the cathode of second error amplifier is used for external institute
The power supply of the second predetermined reference voltage is stated, anode connects second feedback resistive network；The source electrode of second power tube is
The first input end of the LDO circuit, drain electrode connect second feedback resistive network and are used for the external load；Described
Two feedback resistive networks are also used to the external load；
When second power tube is NMOS tube, the cathode connection of second error amplifier the second feedback electricity
Network is hindered, anode is used for the power supply of external second predetermined reference voltage；The drain electrode of second power tube is the LDO electricity
The first input end on road, source electrode connect second feedback resistive network and are used for the external load；The second feedback electricity
Resistance network is also used to the external load.
Detailed description of the invention
Fig. 1 is ultra low voltage LDO circuit structural block diagram provided by one embodiment of the present invention；
Fig. 2 is the ultra low voltage LDO circuit structural block diagram that another embodiment of the present invention provides；
Fig. 3 is a kind of power circuit diagram that another embodiment of the present invention provides.
Fig. 4 is a kind of LDO circuit figure that another embodiment of the present invention provides；
Fig. 5 is a kind of LDO circuit figure that another embodiment of the present invention provides.
Specific embodiment
The principle and features of the present invention will be described below with reference to the accompanying drawings, and the given examples are served only to explain the present invention, and
It is non-to be used to limit the scope of the invention.
Embodiment one
A kind of ultra low voltage LDO circuit 100, as shown in Figure 1, comprising: LDO circuit and power circuit interconnected.Electricity
Source circuit is also used to external input power, for receiving the input voltage of the input power, and when input voltage is lower than first
When predetermined reference voltage, more times of boosting processing are carried out to input voltage, first target voltage is obtained and is input to LDO circuit；When
When input voltage is higher than the first predetermined reference voltage, pressure stabilizing, more times of boosting processing are successively carried out to input voltage, obtains the second mesh
Mark voltage is simultaneously input to LDO circuit, wherein first target voltage and the second target voltage are used to as LDO circuit power supply；LDO
Circuit is also used to external input power and load, for receiving input voltage, and is based on the second predetermined reference voltage, to input electricity
Pressure handles to obtain required voltage and is input to load.
It should be noted that LDO circuit is directly connected to by input power or front stage circuits, so that the energy of LDO circuit
Amount transfer efficiency is guaranteed.In addition, powering by power circuit to LDO circuit, allow LDO circuit in ultra low voltage
Continue to keep high-performance in the case where input.It by power circuit part, boosts when input voltage is lower, guarantees circuit
Can, pressure stabilizing when input voltage is higher prevents circuit from puncturing.In addition, two target voltages are inconsistent, such as the first predetermined reference voltage
For 0.6V, input voltage is respectively 0.4,0.8,1.2, then the voltage (required voltage) exported is respectively 0.8,1.2,1.2.LDO
Control section be mainly error amplifier part, when supply voltage (being provided by input power) is too high, will lead to circuit quilt
Breakdown, thrashing, if the maximum operating voltage of circuit is 1.2V, the effect of pressure stabilizing is exactly that target voltage is allowed to be no more than 1.2V.
It is input voltage all the way that the present embodiment, which introduces lightweight in LDO circuit and locally generates power supply using duplex feeding,
It powers directly to LDO, another way is that input voltage is powered after lightweight locally generates power supply pressure stabilizing, boosting to LDO, i.e., when defeated
Enter supply voltage it is lower when boost to supply voltage, when input supply voltage is higher to boosting after supply voltage pressure stabilizing, realize
LDO circuit can work under ultralow or wide-voltage range working environment, even if the load in LDO circuit is ultra low voltage
Digital module or other modules sensitive to power supply electrical level (such as it is ultra low voltage analog module, ultra low voltage radio-frequency module, ultralow
Voltage DAC/ADC etc.), it can also work normally, ensure that low ripple and high power supply inhibit while improving energy conversion efficiency
Than.
Embodiment two
On the basis of example 1, as shown in Fig. 2, power circuit includes: steady voltage regulator circuit and booster circuit.Pressure stabilizing
Adjusting circuit, external input power, for receiving input voltage, and when input voltage is lower than the first predetermined reference voltage,
Input voltage is input to booster circuit；Value pressure stabilizing when input voltage is higher than the first predetermined reference voltage, to input voltage
To the value of the first predetermined reference voltage, obtains new input voltage and be input to booster circuit；Booster circuit, with LDO circuit
Connection, the input voltage for inputting to steady voltage regulator circuit carry out more times of boostings, obtain first target voltage or the second target
Voltage is simultaneously input to LDO circuit.
Preferably, as shown in figure 3, steady voltage regulator circuit includes: first error amplifier, the first power tube and first
Feedback resistive network.The input terminal of first error amplifier is connect with input power is stated, the grid of output end and the first power tube
Connection；The cathode of first error amplifier connects the power supply of the first feedback resistive network or external first predetermined reference voltage, just
The first feedback resistive network of power supply or connection of extremely external first predetermined reference voltage；The source electrode of first power tube or drain electrode are external
Input power, drain electrode or source electrode connect the first feedback resistive network and booster circuit；First feedback resistive network is also connected with boosting
Circuit.
Preferably, the first power tube is weak output power pipe.
It should be noted that in weak output power pipe and the second power tube and design other MOS transistors for using without
Essential distinction, because it acts on power conversion, so referred to as power tube.Weak output power pipe and the second power tube most very much not
It is same to be that the demand of output power is of different sizes, so the size of weak output power pipe is much smaller than the second power tube.
Preferably, when the first power tube is PMOS tube, the external first preset reference electricity of the cathode of first error amplifier
The power supply of pressure, anode the first feedback resistive network of connection；The source electrode external input power of first power tube, drain electrode connection first are anti-
Present resistor network and external load；First feedback resistive network also external load；When the first power tube is NMOS tube, first is missed
The cathode of poor amplifier connects the first feedback resistive network, the power supply of external first predetermined reference voltage of anode；First power tube
Drain electrode external input power, source electrode connects the first feedback resistive network and booster circuit；First feedback resistive network is also connected with
Booster circuit.
Preferential, booster circuit is specifically used for the input voltage inputted to steady voltage regulator circuit and carries out two times of boostings, obtains
First target voltage or the second target voltage are simultaneously input to LDO circuit.It is boosted using two times, energy conversion efficiency can be improved.
Preferably, as shown in figure 3, booster circuit includes: the sharp charge pump of twice flesh side gram, and respectively with twice of skin
The first storage capacitor, the second storage capacitor and the filter capacitor of Li Keli charge pump connection.The sharp charge pump of twice of flesh side gram is also divided
Not with steady voltage regulator circuit and LDO circuit connection, the input voltage for inputting to steady voltage regulator circuit carries out two times of boostings,
It obtains first target voltage or the second target voltage and is input to LDO circuit；First storage capacitor and the second storage capacitor also divide
Not external asynchronous square-wave pulse modulation circuit, for storing two asynchronous pulse square waves of asynchronous square-wave pulse modulation circuit input
Square wave information, with the input voltage progress boost operations for assisting twice flesh side gram sharp charge pump input steady voltage regulator circuit；
Filter capacitor is also connect with LDO circuit and external ground, for eliminating the burr and line of first target voltage and the second target voltage
Wave.
Preferably, the peak value of two asynchronous pulse square waves is equal with the value of the input voltage of input power.
For example, Fig. 3 gives a specific embodiment of a power circuit, including error amplifier 201, weak output work
Rate pipe 202 and divider resistance R21 and R22 constitute the low pressure difference linear voltage regulator of a weak output, the main function of this part
It is that input voltage VDD to VDD.R by reference to voltage, is adjusted according to the demand used；Asynchronous square-wave pulse modulation 204 is by two
A phase inverter INV1 and INV2 composition, the effect of this part is the peak-to-peak value of the square-wave pulse of modulation input, to reach control
The purpose of output voltage；Flesh side gram benefit charge pump and filter capacitor 203, the effect of this part is to modulated voltage VDD.R
And two times of boostings are carried out to the pulse square wave that peak-to-peak value is VDD.R, suitable voltage VS is finally exported to the mistake of main body circuit
Poor amplifier 102 is powered.The joint detail of the circuit is as schemed, and details are not described herein again.
To sum up, power circuit needs a reference voltage and two asynchronous pulse square waves as inputting, this three input
Signal internal can be generated and can also be input from the outside.Steady voltage regulator circuit can be the low pressure difference linear voltage regulator of weak output.
The first predetermined reference voltage of one end that steady voltage regulator circuit can be given, when input voltage is lower than this value, input
Voltage carries out voltage-doubling boost by booster circuit, exports to the supply voltage of first error amplifier, is at this time twice of input
Voltage；When input voltage is higher than the first predetermined reference voltage, steady voltage regulator circuit is started to work, so that two times of charge pumps
The peak value of input is equal with reference voltage, and being exported at this time to the supply voltage of first error amplifier is twice of reference voltage.It is logical
Cross the value appropriate for choosing the first predetermined reference voltage, it is ensured that the first error amplifier normal work when compared with low input
Make, it is not breakdown in high-line input voltage.
Embodiment three
On the basis of embodiment one or embodiment two, as shown in Figure 4 and Figure 5, LDO circuit includes: the amplification of the second error
Device, the second power tube and the second feedback resistive network.The input terminal of second error amplifier is connect with power circuit, output
End is connect with the grid of the second power tube；The cathode of second error amplifier connects the second feedback resistive network or external second in advance
If the power supply of reference voltage, the first feedback resistive network of power supply or connection of external second predetermined reference voltage of anode；Second function
The source electrode or drain electrode external input power of rate pipe, drain electrode or source electrode connect the second feedback resistive network and external load；Second is anti-
Present resistor network also external load.
Preferably, as shown in figure 4, when the second power tube is PMOS tube, the cathode of the second error amplifier external second
The power supply of predetermined reference voltage, anode the second feedback resistive network of connection；The source electrode external input power of second power tube, drain electrode
Connect the second feedback resistive network and external load；Second feedback resistive network also external load.
As shown in figure 5, the cathode of the second error amplifier connects the second feedback resistance when the second power tube is NMOS tube
Network, the power supply of external second predetermined reference voltage of anode；The drain electrode external input power of second power tube, source electrode connection second
Feedback resistive network and external load；Second feedback resistive network also external load.
It should be noted that it is directly connected to the second power tube by input power or front stage circuits, so that LDO circuit
Energy conversion efficiency is guaranteed；It is powered by power circuit to the second error amplifier, allows LDO circuit in ultralow electricity
Continue to keep high-performance in the case where pressure input.
Power circuit possesses an input terminal and an output end, and wherein input terminal connects the input voltage of LDO (as
Input power), output end connects the supply voltage end of the second error amplifier.Power circuit is used for the second error amplifier
Power supply, even if so that the second error amplifier in LDO can also be worked normally in ultralow input voltage.
When load current changes, the output voltage (voltage needed for i.e.) of LDO circuit changes, and passes through the first feedback
Variation is linearly transmitted to first error amplifier by resistor network, and first error amplifier is by the variation and predetermined reference voltage
Compare, which is acted on to the grid voltage of the first power tube, then pressure stabilizing is achieved the purpose that by the first power tube.
Fig. 5 modifies on the basis of fig. 4, and the second power tube assembly therein is changed to NMOS by PMOS, and by
The exchange of two error amplifier positive-negative input end signals.Due to the special nature of NMOS, it is desirable that the power supply electricity of the second error amplifier
Pressure is higher than the supply voltage of the second power tube to guarantee the conduction voltage drop of reduction NMOS power tube.In still further aspect, due to
NMOS possesses biggish mobility, higher intrinsic gain, when the case where exporting an equal amount of load current, NMOS power
The area of pipe can substantially reduce compared to PMOS.Simultaneously because the difference of the supply voltage of output voltage and the second error amplifier
Greater than 300mV, resistance-feedback network can be cancelled at this time, directly inputted with the negative terminal of the second error amplifier by output end
It is connected directly.
In an embodiment of the present invention, the second error amplifier is for adjusting the output of the second power tube, the amplification of the second error
Device can use existing two-stage cmos operational amplifier structure, the compensating electric capacity of system not drawn in the figure,
It should be noted that the output electric current due to power circuit is small, thus output power is small, and power circuit volume
Small, the smaller thus of the invention power circuit of area for accounting for ultra low voltage LDO circuit is lightweight power circuit.In addition, electric
Source circuit is integrated on the chip of LDO circuit, does not need additional external power supply input, thus power circuit is local production
Power circuit.To sum up, the power circuit in ultra low voltage LDO circuit of the present invention can be referred to as " lightweight local generation power supply electricity
Road ".
LDO circuit of the invention is made using the 130nm technique of TaiWan, China United Microelectronics company, is joined when taking first to preset
Examine voltage VREF be 0.6V when, may make whole LDO circuit that can export in input voltage 0.5V-1.2V with superior performance
Voltage 0.4V-1.1V can be accomplished lower with more advanced technologies.The LDO circuit thus haveing excellent performance for other, can be with
The method of the reduction input voltage range proposed through the invention, acquisition can be in the ability of operating on low voltage, while retaining other
Excellent performance, therefore the input voltage minimum zone of ultra low voltage LDO of the invention is 0.5V-1.2V.
The foregoing is merely presently preferred embodiments of the present invention, is not intended to limit the invention, it is all in spirit of the invention and
Within principle, any modification, equivalent replacement, improvement and so on be should all be included in the protection scope of the present invention.
Claims (10)
1. a kind of ultra low voltage LDO circuit characterized by comprising LDO circuit and power circuit；The power circuit it is defeated
The first input end for entering end and the LDO circuit is used to external input power, the output end of the power circuit and the LDO
Second input terminal of circuit connects；
The power circuit is for judging its received input voltage whether less than the first predetermined reference voltage, if so, to described
Input voltage carries out more times of boosting processing, obtains first target voltage and is input to the LDO circuit；If it is not, to the input
Voltage successively carries out pressure stabilizing, more times of boostings processing, obtains the second target voltage and is input to the LDO circuit, wherein described the
One target voltage and second target voltage are used to as LDO circuit power supply；
The LDO circuit is used to be based on the second predetermined reference voltage, the input voltage processing received to its first input end
It obtains required voltage and exports.
2. a kind of ultra low voltage LDO circuit according to claim 1, which is characterized in that the power circuit includes: pressure stabilizing
Adjust circuit and booster circuit；
The steady voltage regulator circuit, input terminal is the input terminal of the power circuit, for judging its received input voltage
Whether less than the first predetermined reference voltage, if so, the input voltage is input to the booster circuit；If it is not, to described defeated
Enter the value pressure stabilizing of voltage to the value of first predetermined reference voltage, obtains new input voltage and be input to the boosting electricity
Road；
The booster circuit, output end are the output end of the power circuit, for the steady voltage regulator circuit input
The input voltage carries out more times of boostings, obtains the first target voltage or second target voltage and is input to described
LDO circuit.
3. a kind of ultra low voltage LDO circuit according to claim 2, which is characterized in that the steady voltage regulator circuit includes:
First error amplifier, the first power tube and the first feedback resistive network；
The first error amplifier is used for the external input power, and output end is connect with the grid of first power tube；
The cathode of the first error amplifier connects first feedback resistive network or for the external first preset reference electricity
The power supply of pressure, power supply or connection first feedback resistive network of the anode for external first predetermined reference voltage；Institute
The source electrode for stating the first power tube or drain electrode are for the external input power, drain electrode or source electrode connection the first feedback resistance net
Network and the booster circuit；First feedback resistive network is also connected with the booster circuit.
4. a kind of ultra low voltage LDO circuit according to claim 3, which is characterized in that first power tube is weak defeated
Power tube out.
5. a kind of ultra low voltage LDO circuit according to claim 3, which is characterized in that when first power tube is
When PMOS tube, the power supply of external second predetermined reference voltage of the cathode of the first error amplifier, anode connection described in
First feedback resistive network；The source electrode of first power tube is used for the external input power, and drain electrode connection described first is anti-
It presents resistor network and is used for the external booster circuit；First feedback resistive network is also connected with the booster circuit；
When first power tube is NMOS tube, the cathode of the first error amplifier connects the first feedback resistance net
Network, anode are used for the power supply of external first predetermined reference voltage；The drain electrode of first power tube is for external described defeated
Enter power supply, source electrode connects first feedback resistive network and the booster circuit；First feedback resistive network is also connected with
The booster circuit.
6. a kind of ultra low voltage LDO circuit according to claim 2, which is characterized in that the booster circuit is specifically used for
Two times of boostings are carried out to the input voltage of the steady voltage regulator circuit input, obtain the first target voltage or described the
Two target voltages are simultaneously input to the LDO circuit.
7. a kind of ultra low voltage LDO circuit according to claim 6, which is characterized in that the booster circuit includes: twice
Flesh side gram benefit charge pump, and the first storage capacitor, the second energy storage electricity that are connect respectively with the sharp charge pump of twice of flesh side gram
Appearance and filter capacitor；
The first input end and pressure stabilizing adjusting circuit connection, the second input terminal of the sharp charge pump of twice of flesh side gram are described
The output end of power circuit obtains institute for carrying out two times of boostings to the input voltage of the steady voltage regulator circuit input
It states first target voltage or second target voltage and is input to the LDO circuit；
First storage capacitor and second storage capacitor are also used to external asynchronous square-wave pulse modulation circuit, to deposit
The square wave information for storing up two asynchronous pulse square waves of the asynchronous square-wave pulse modulation circuit input, assists twice of flesh side gram
Sharp charge pump carries out boost operations；
The filter capacitor is also connect with the LDO circuit, for eliminating the first target voltage and second target electricity
The burr and ripple of pressure.
8. a kind of ultra low voltage LDO circuit according to claim 7, which is characterized in that described two asynchronous pulse square waves
Peak value it is equal with the value of the input voltage of the input power.
9. a kind of ultra low voltage LDO circuit according to any one of claims 1 to 8, which is characterized in that the LDO circuit
It include: the second error amplifier, the second power tube and the second feedback resistive network；
The input terminal of second error amplifier is the second input terminal of the LDO circuit, output end and second power
The grid of pipe connects；The cathode of second error amplifier connects second feedback resistive network and is used for external second in advance
If the power supply of reference voltage, power supply or the connection first feedback resistance net of the anode for external second predetermined reference voltage
Network；The source electrode of second power tube or drain electrode are the first input end of the LDO circuit, drain electrode or source electrode connection described second
Feedback resistive network is simultaneously used for the external load；Second feedback resistive network is also used to the external load.
10. a kind of ultra low voltage LDO circuit according to claim 9, which is characterized in that when second power tube is
When PMOS tube, the cathode of second error amplifier is used for the power supply of external second predetermined reference voltage, anode connection
Second feedback resistive network；The source electrode of second power tube is the first input end of the LDO circuit, drain electrode connection institute
State the second feedback resistive network and for the external load；Second feedback resistive network is also used to the external load；
When second power tube is NMOS tube, the cathode of second error amplifier connects the second feedback resistance net
Network, anode are used for the power supply of external second predetermined reference voltage；The drain electrode of second power tube is the LDO circuit
First input end, source electrode connect second feedback resistive network and are used for the external load；The second feedback resistance net
Network is also used to the external load.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910139295.3A CN109871059B (en) | 2019-02-25 | 2019-02-25 | Ultralow voltage L DO circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
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| CN201910139295.3A CN109871059B (en) | 2019-02-25 | 2019-02-25 | Ultralow voltage L DO circuit |
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| CN110262610A (en) * | 2019-07-10 | 2019-09-20 | 上海艾为电子技术股份有限公司 | A kind of linear voltage regulator of power tube |
| CN111399578A (en) * | 2020-04-22 | 2020-07-10 | 安徽华夏显示技术股份有限公司 | Airborne low-voltage stabilization control circuit |
| CN114003081A (en) * | 2021-10-29 | 2022-02-01 | 华中科技大学 | Digital LDO circuit with low-voltage ripple output |
| CN115016582A (en) * | 2022-06-13 | 2022-09-06 | 成都芯源系统有限公司 | Low dropout linear regulator circuit and method thereof |
| CN115237193A (en) * | 2022-09-22 | 2022-10-25 | 香港中文大学（深圳） | LDO system suitable for low-voltage input and large-current output |
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| CN110262610A (en) * | 2019-07-10 | 2019-09-20 | 上海艾为电子技术股份有限公司 | A kind of linear voltage regulator of power tube |
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| CN114003081A (en) * | 2021-10-29 | 2022-02-01 | 华中科技大学 | Digital LDO circuit with low-voltage ripple output |
| CN114003081B (en) * | 2021-10-29 | 2022-07-05 | 华中科技大学 | Digital LDO circuit with low-voltage ripple output |
| CN115016582A (en) * | 2022-06-13 | 2022-09-06 | 成都芯源系统有限公司 | Low dropout linear regulator circuit and method thereof |
| CN115237193A (en) * | 2022-09-22 | 2022-10-25 | 香港中文大学（深圳） | LDO system suitable for low-voltage input and large-current output |
| CN115237193B (en) * | 2022-09-22 | 2022-12-09 | 香港中文大学（深圳） | LDO system suitable for low-voltage input and large-current output |
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