CN109728813B

CN109728813B - Sample-and-hold amplifier capable of flexibly switching candidate capacitor

Info

Publication number: CN109728813B
Application number: CN201711022810.7A
Authority: CN
Inventors: 黄诗雄; 陈志龙; 赖杰帆; 吴健铭
Original assignee: Realtek Semiconductor Corp
Current assignee: Realtek Semiconductor Corp
Priority date: 2017-10-27
Filing date: 2017-10-27
Publication date: 2022-10-14
Anticipated expiration: 2037-10-27
Also published as: CN109728813A

Abstract

The present invention provides a sample and hold amplifier, comprising: a switched capacitor network configured to sample and hold an input signal to generate a first signal; and the operational amplifier is coupled to the switched capacitor network and comprises a plurality of candidate capacitors, and the operational amplifier is configured to generate an output signal according to the first signal and switch the coupling mode of the candidate capacitors according to the magnitude of the input signal, so that only a part of the candidate capacitors can be used for participating in the generation operation of the output signal at the same time. The sample-and-hold amplifier provided by the invention can effectively improve the response speed of the operational amplifier.

Description

Sample-and-hold amplifier capable of flexibly switching candidate capacitor

Technical Field

The present invention relates to a sample-and-hold amplifier, and more particularly, to a sample-and-hold amplifier with flexibly switchable candidate capacitors.

Background

In a conventional sample-and-hold amplifier, an operational amplifier is required, but the overall performance or operation speed of the sample-and-hold amplifier is limited by the response speed of the operational amplifier. It is known that the length of time required for charging or discharging a feedback capacitor inside an operational amplifier has a great influence on the response speed of the operational amplifier. If the response speed of the operational amplifier is not improved effectively, it is difficult to increase the overall performance or operation speed of the sample-and-hold amplifier.

Disclosure of Invention

Therefore, how to effectively improve the response speed of the operational amplifier in the sample-and-hold amplifier is a problem to be solved.

The present specification provides an embodiment of a sample and hold amplifier comprising: a switched capacitor network configured to sample and hold an input signal to generate a first signal; and the operational amplifier is coupled to the switched capacitor network and comprises a plurality of candidate capacitors, and the operational amplifier is configured to generate an output signal according to the first signal and switch the coupling mode of the candidate capacitors according to the magnitude of the input signal, so that only a part of the candidate capacitors can be used for participating in the generation operation of the output signal at the same time.

The present specification further provides an embodiment of a sample and hold amplifier, comprising: a switched capacitor network configured to sample and hold an input signal to generate a first signal; and an operational amplifier coupled to the switched capacitor network and including a plurality of candidate capacitors, wherein the operational amplifier is configured to generate an output signal according to the first signal and switch the coupling manner of the candidate capacitors according to the magnitude of the input signal, so that only a part of the candidate capacitors can be used to participate in the generation operation of the output signal at the same time; the plurality of candidate capacitors are divided into a first capacitor bank and a second capacitor bank, and when part of the candidate capacitors in the first capacitor bank participate in the generation and operation of the output signal, all the candidate capacitors in the second capacitor bank are respectively charged to have different voltage values.

One advantage of the above embodiment is that before the selection of the candidate capacitor by the operational amplifier, a plurality of candidate capacitors in the operational amplifier can be pre-charged to have different voltage levels, thereby reducing the charging or discharging time required for the selected capacitor.

Another advantage of the above embodiments is that the dynamic selection mechanism of the candidate capacitors can equivalently shorten the charging or discharging time required by the feedback capacitor of the operational amplifier, thereby effectively improving the response speed of the operational amplifier.

Other advantages of the present invention will be explained in more detail in conjunction with the following description and the accompanying drawings.

Drawings

Fig. 1 is a simplified functional block diagram of an operational amplifier according to an embodiment of the present invention.

Fig. 2 is a simplified schematic diagram of an embodiment of the capacitance selection circuit in fig. 1.

Fig. 3 is a simplified functional block diagram of a pipelined adc according to a first embodiment of the present invention.

Fig. 4 is a simplified, partial functional block diagram of an embodiment of the pipelined adc of fig. 3.

Fig. 5 is a simplified functional block diagram of a pipelined adc according to a second embodiment of the present invention.

Fig. 6 is a simplified partial functional block diagram of an embodiment of the pipelined adc of fig. 5.

FIG. 7 is a simplified functional block diagram of a sample-and-hold amplifier according to an embodiment of the present invention.

Description of reference numerals:

100. operational amplifier

102. Preceding stage circuit

110. 120 gain stage

131. 133, 135, 151, 153, 155 candidate capacitance

141-146, 161-166, 425-429, 445-449 and 645-649 switches

170. Capacitance selection circuit

210-230 comparator

240. Selection logic

300. Single-channel pipeline type analog-digital converter

301-304, 501-504 circuit stage

305. 505 back-end analog-to-digital converter

306. 506 timing adjustment and error correction circuit

310. 330, 530 analog-to-digital converter

320. 340, 540 multiplying digital-to-analog converter

322. 342, 542 sample and hold circuit

324. 344, 544 digital to analog converter

326. 346, 546 subtracter

328. 348, 548 operational amplifier

420. 440, 640 switched capacitor network

421. 423, 441, 443, 641 and 643 capacitors

480. Output switch

490. Input switch

500. Double-channel assembly line type analog-digital converter

700. Sample-and-hold amplifier

702. Switched capacitor network

710. Sampling capacitor

720. 730 sampling switch

740. Sequential control circuit

Detailed Description

Embodiments of the present invention will be described below with reference to the accompanying drawings. In the drawings, the same reference numbers indicate the same or similar elements or process flows.

Fig. 1 is a simplified functional block diagram of an operational amplifier 100 according to an embodiment of the invention. Operational amplifier 100 comprises a first gain stage 110, a second gain stage 120, a plurality of candidate capacitors, a plurality of switches, and a capacitor selection circuit 170.

For convenience of explanation, the candidate capacitances 131, 133, and 135 (hereinafter referred to as first to third candidate capacitances, respectively), the candidate capacitances 151, 153, and 155 (hereinafter referred to as fourth to sixth candidate capacitances, respectively), the switches 141 to 146 (hereinafter referred to as first to sixth switches, respectively), and the switches 161 to 166 (hereinafter referred to as seventh to twelfth switches, respectively) are shown in fig. 1 as exemplary elements.

In the operational amplifier 100, the first gain stage 110 is configured to generate a second signal N2 according to a first signal N1 transmitted from the front-stage circuit 102 of the operational amplifier 100. The preceding stage circuit 102 may be implemented with various suitable circuits including one or more switched capacitor networks.

The second gain stage 120 is coupled to the first gain stage 110, and configured to generate the output signal Vout of the operational amplifier 100 according to the second signal N2.

As shown, the first switch 141 is coupled to the first end of the first candidate capacitor 131 for selectively coupling the first candidate capacitor 131 to the first predetermined voltage Vcm or the input end of the second gain stage 120.

The second switch 142 is coupled to the second end of the first candidate capacitor 131 for selectively coupling the first candidate capacitor 131 to the first voltage V1 or the output end of the second gain stage 120.

The third switch 143 is coupled to the first terminal of the second candidate capacitor 133 for selectively coupling the second candidate capacitor 133 to the first predetermined voltage Vcm or the input terminal of the second gain stage 120.

The fourth switch 144 is coupled to the second terminal of the second candidate capacitor 133 for selectively coupling the second candidate capacitor 133 to the second voltage V2 or the output terminal of the second gain stage 120.

The fifth switch 145 is coupled to the first terminal of the third candidate capacitor 135 for selectively coupling the third candidate capacitor 135 to the first predetermined voltage Vcm or the input terminal of the second gain stage 120.

The sixth switch 146 is coupled to the second terminal of the third candidate capacitor 135 for selectively coupling the third candidate capacitor 135 to the third voltage V3 or the output terminal of the second gain stage 120.

The seventh switch 161 is coupled to the first terminal of the fourth candidate capacitor 151 for selectively coupling the fourth candidate capacitor 151 to the first predetermined voltage Vcm or the input terminal of the second gain stage 120.

The eighth switch 162 is coupled to the second end of the fourth candidate capacitor 151 for selectively coupling the fourth candidate capacitor 151 to the first voltage V1 or the output end of the second gain stage 120.

The ninth switch 163 is coupled to the first terminal of the fifth candidate capacitor 153, and is used for selectively coupling the fifth candidate capacitor 153 to the first predetermined voltage Vcm or the input terminal of the second gain stage 120.

The tenth switch 164 is coupled to the second terminal of the fifth candidate capacitor 153, for selectively coupling the fifth candidate capacitor 153 to the second voltage V2 or the output terminal of the second gain stage 120.

The eleventh switch 165 is coupled to the first terminal of the sixth candidate capacitor 155 for selectively coupling the sixth candidate capacitor 155 to the first predetermined voltage Vcm or the input terminal of the second gainstage 120.

The twelfth switch 166 is coupled to the second end of the sixth candidate capacitor 155 for selectively coupling the sixth candidate capacitor 155 to the third voltage V3 or the output end of the second gainstage 120.

The capacitor selection circuit 170 is coupled to the pre-stage 102 and the first to twelfth switches 141-146 and 161-166, and is configured to control the first to twelfth switches 141-146 and 161-166 according to a magnitude of an input signal Vin of the pre-stage 102, such that only a portion of the first to sixth candidate capacitors 131-135 and 151-155 are coupled to the second gain stage 120 at the same time.

As can be seen from the foregoing description, the input signal Vin is the input signal of the front-stage circuit 102, and the input signal of the operational amplifier 100 is the first signal N1. The magnitude relationship between the input signal Vin of the pre-stage 102 and the output signal Vout of the operational amplifier 100 is related to the design of the gain values of the first gain stage 110 and the second gain stage 120.

In practice, the first to third voltages V1 to V3 may be voltages of different magnitudes, and the first predetermined voltage Vcm may be a fixed voltage or a common mode voltage (common mode voltage) of the second gain stage 120.

It should be noted that the first gain stage 110 and the second gain stage 120 are illustrated as single-ended circuit architectures in fig. 1, only for simplifying the complexity of the drawing, and are not limited to the practical implementation of the present invention. In practice, the first gain stage 110 and the second gain stage 120 of the operational amplifier 100 can be implemented by using a differential circuit architecture.

In operation, the capacitor selection circuit 170 may synchronously switch the switches across a particular candidate capacitor to couple the particular candidate capacitor to the second gainstage 120 to participate in the generation of the output signal Vout, or to couple the particular candidate capacitor to a corresponding charging voltage for charging.

For example, when the capacitor selection circuit 170 controls the first switch 141 to couple the first end of the first candidate capacitor 131 to the input end of the second gain stage 120, the capacitor selection circuit 170 controls the second switch 142 to couple the second end of the first candidate capacitor 131 to the output end of the second gain stage 120. At this time, the first candidate capacitor 131 may participate in the generation operation of the output signal Vout. On the other hand, when the capacitor selection circuit 170 controls the first switch 141 to couple the first terminal of the first candidate capacitor 131 to the first predetermined voltage Vcm, the capacitor selection circuit 170 controls the second switch 142 to couple the second terminal of the first candidate capacitor 131 to the first voltage V1. At this time, the first capacitor candidate 131 is switched to the charging mode and charged to have a predetermined voltage (in this case, the voltage difference between the first voltage V1 and the first predetermined voltage Vcm).

For another example, when the capacitor selection circuit 170 controls the third switch 143 to couple the first terminal of the second candidate capacitor 133 to the input terminal of the second gain stage 120, the capacitor selection circuit 170 controls the fourth switch 144 to couple the second terminal of the second candidate capacitor 133 to the output terminal of the second gain stage 120. At this time, the second candidate capacitor 133 may participate in the generation operation of the output signal Vout. On the other hand, when the capacitor selection circuit 170 controls the third switch 143 to couple the first terminal of the second candidate capacitor 133 to the first predetermined voltage Vcm, the capacitor selection circuit 170 controls the fourth switch 144 to couple the second terminal of the second candidate capacitor 133 to the second voltage V2. At this time, the second capacitor candidate 133 is switched to the charging mode and charged to have a predetermined voltage (in this case, the voltage difference between the second voltage V2 and the first predetermined voltage Vcm).

For another example, when the capacitor selection circuit 170 controls the eleventh switch 165 to couple the first terminal of the sixth candidate capacitor 155 to the input terminal of the second gain stage 120, the capacitor selection circuit 170 controls the twelfth switch 166 to couple the second terminal of the sixth candidate capacitor 155 to the output terminal of the second gain stage 120. At this time, the sixth candidate capacitor 155 may participate in the generation operation of the output signal Vout. On the other hand, when the capacitor selection circuit 170 controls the eleventh switch 165 to couple the first terminal of the sixth candidate capacitor 155 to the first predetermined voltage Vcm, the capacitor selection circuit 170 controls the twelfth switch 166 to couple the second terminal of the sixth candidate capacitor 155 to the third voltage V3. At this time, the sixth capacitor candidate 155 is switched to the charging mode and charged to have a predetermined voltage (in this case, the voltage difference between the third voltage V3 and the first predetermined voltage Vcm).

The manner in which the capacitor selection circuit 170 controls the switches at the two ends of the other candidate capacitors is the same as the previous example, and for brevity, the description is omitted here.

In practice, the first voltage V1, the second voltage V2, and the third voltage V3 are different, that is, different candidate capacitors have different voltage steps after being charged.

Each candidate capacitor in the operational amplifier 100 may be implemented by a single capacitor device, or may be implemented by a combination of two or more capacitor devices connected in parallel. In addition, the first to twelfth switches 141 to 146 and 161 to 166 can be implemented by a combination of a plurality of transistors, or a combination of a plurality of transistors and an appropriate logic gate.

In some embodiments, the candidate capacitors 131-135 and 151-155 in the operational amplifier 100 may be alternately charged by dividing the candidate capacitors into two capacitor sets, and the capacitor selection circuit 170 may alternately select a selected capacitor from the two capacitor sets to participate in the generation operation of the output signal Vout and couple the selected capacitor to the second gain stage 120.

For example, in one embodiment, the first to third candidate capacitors 131-135 of fig. 1 may be set as a first capacitor bank and the fourth to sixth candidate capacitors 151-155 may be set as a second capacitor bank. In operation, when the capacitor selection circuit 170 selects a part of the candidate capacitors in one of the capacitor banks as the selected capacitors to participate in the generation operation of the output signal Vout, the capacitor selection circuit 170 may control the corresponding switches of the other capacitor bank, so that all the candidate capacitors in the other capacitor bank are switched to the charging mode together and are respectively charged to have different voltage values.

For example, when the capacitor selection circuit 170 controls the relevant switches to couple the local candidate capacitors of the first capacitor bank (in this case, the first to third candidate capacitors 131 to 135) to the second gain stage 120, the capacitor selection circuit 170 may control the corresponding switches 161 to 166 of the second capacitor bank (in this case, the fourth to sixth candidate capacitors 151 to 155) to switch the fourth to sixth candidate capacitors 151 to 155 to the charging mode, so that the fourth to sixth candidate capacitors 151 to 155 are charged together and respectively charged to have different voltage steps.

For another example, when the capacitor selection circuit 170 controls the related switches to couple the local candidate capacitors in the second capacitor bank (in this case, the fourth to sixth candidate capacitors 151-155) to the second gain stage 120, the capacitor selection circuit 170 may control the corresponding switches 141-146 of the first capacitor bank (in this case, the first to third candidate capacitors 131-135) to switch the first to third candidate capacitors 131-135 to the charging mode, so that the first to third candidate capacitors 131-135 are charged together and are respectively charged to have different voltage steps.

Therefore, the capacitor selection circuit 170 may select a portion of the candidate capacitors from the first capacitor set as the selected capacitors to be coupled to the second gainstage 120 in a first operation period T1, and switch all the candidate capacitors (i.e., the fourth to sixth candidate capacitors 151-155) in the second capacitor set to the charging mode together for charging in the first operation period T1.

In a second operation period T2 after the first operation period T1, the capacitor selection circuit 170 may select a part of the candidate capacitors from the second capacitor set that has been charged as the selected capacitors to be coupled to the second gain stage 120, and switch all the candidate capacitors (i.e., the first to third candidate capacitors 131-135) in the first capacitor set to the charging mode for charging in the second operation period T2.

Next, in a third operation period T3 after the second operation period T2, the capacitance selection circuit 170 may select a part of the first to third candidate capacitances 131 to 135 that have been charged as the selected capacitances to be coupled to the second gain stage 120, and switch the fourth to sixth candidate capacitances 151 to 155 to the charging mode for charging together in the third operation period T3.

In subsequent operation periods, the capacitor selection circuit 170 may repeat the aforementioned operation mode of grouping and alternately charging a plurality of candidate capacitors and selecting an appropriate selected capacitor from the charged capacitor group.

In practice, the capacitor selection circuit 170 may select, as the selected capacitor, a part of the candidate capacitors having an appropriate voltage that can reduce the charging or discharging time required after being coupled to the second gain stage 120 from the pre-charged capacitor bank (pre-charged capacitor group) in each operation period, and switch the related switches such that only the selected capacitor is coupled to the second gain stage 120 in the same time period as the first to sixth candidate capacitors 131-135 and 151-155.

For example, fig. 2 is a simplified schematic diagram of an embodiment of the capacitance selection circuit 170. In the embodiment of fig. 2, capacitance selection circuit 170 includes a plurality of comparators (e.g.,

exemplary comparators

210, 220, and 230 are shown), and selection logic 240.

In capacitance selection circuit 170, each comparator is arranged to compare an input signal Vin of preceding stage circuit 102 with a corresponding reference signal. For example, the first comparator 210 is configured to compare the input signal Vin with the first reference signal Vref _1 to generate a first comparison signal C1. The second comparator 220 is configured to compare the input signal Vin with the second reference signal Vref _2 to generate a second comparison signal C2. The third comparator 230 is arranged to compare the input signal Vin with a third reference signal Vref _ n to generate a third comparison signal Cn, and so on. In one embodiment, the signal value of the third reference signal Vref _ n is greater than the signal value of the second reference signal Vref _2, and the signal value of the second reference signal Vref _2 is greater than the signal value of the first reference signal Vref _ 1.

The selection logic 240 is coupled to the plurality of comparators 210-230, and configured to select a portion of the candidate capacitors having the appropriate voltage as the selected capacitor from the pre-charged capacitor set according to the comparison result of the comparators 210-230. The selection logic 240 generates a plurality of control signals for controlling the first to sixth switches 141-146 to set the coupling of all the candidate capacitors such that only the selected capacitor is coupled to the second gain stage 120 and none of the other candidate capacitors are coupled to the second gain stage 120 at the same time for the first to sixth candidate capacitors 131-135 and 151-155. In other words, only the selected capacitor will participate in the next generation operation of the second gain stage 120, and none of the other candidate capacitors will participate in the next generation operation of the output signal Vout.

As long as the signal values of the reference signals Vref _1-Vref _ n are properly set, the selection logic 240 can determine the magnitude range of the input signal Vin according to the comparison signals C1-Cn outputted from the comparators 210-230.

For example, if the first comparison signal C1 indicates that the signal value of the input signal Vin is greater than the signal value of the first reference signal Vref _1, the second comparison signal C2 indicates that the signal value of the input signal Vin is less than the signal value of the second reference signal Vref _2, and the third comparison signal Cn indicates that the signal value of the input signal Vin is less than the signal value of the third reference signal Vref _ n, the selection logic 240 may determine the magnitude of the input signal Vin between the first reference signal Vref _1 and the second reference signal Vref _2.

For another example, if the first comparison signal C1 indicates that the signal value of the input signal Vin is greater than the signal value of the first reference signal Vref _1, the second comparison signal C2 indicates that the signal value of the input signal Vin is greater than the signal value of the second reference signal Vref _2, and the third comparison signal Cn indicates that the signal value of the input signal Vin is less than the signal value of the third reference signal Vref _ n, the selection logic 240 can determine the magnitude of the input signal Vin between the second reference signal Vref _2 and the third reference signal Vref _ n.

Since the magnitudes of the first voltage V1, the second voltage V2, the third voltage V3, and the first predetermined voltage Vcm are given values (given values) in circuit design, the voltage across each candidate capacitor after being charged in advance is also given values.

As mentioned above, the magnitude relationship between the input signal Vin and the output signal Vout mainly depends on the gain values of the first gain stage 110 and the second gain stage 120. Therefore, during circuit design, the mapping relationship between the magnitude of the input signal Vin and the optimum voltage value of the candidate capacitor can be derived according to the matching relationship between the ideal magnitude of the output signal Vout and the optimum voltage value of the candidate capacitor. In practice, the selection logic 240 may be implemented by various combinations of logic gates, and the actual implementation of the selection logic 240 may be designed appropriately according to the mapping relationship between the magnitude of the input signal Vin and the ideal voltage-drop value of the candidate capacitors, so that the selection logic 240 can select a selected capacitor with an appropriate voltage-drop value from a plurality of candidate capacitors to reduce the charging or discharging time required after the selected capacitor is coupled to the second gain stage 120.

For example, in one embodiment, the operation logic of the selection logic 240 may be designed to select a candidate capacitor having a voltage difference between the first voltage V1 and the first predetermined voltage Vcm, as the selected capacitor when the input signal Vin is less than the first reference signal Vref _ 1; when the input signal Vin is between the first reference signal Vref _1 and the second reference signal Vref _2, a candidate capacitor with a voltage difference between the second voltage V2 and the first predetermined voltage Vcm, which is close to the cross voltage, is selected as a selected capacitor; and when the input signal Vin is between the second reference signal Vref _2 and the third reference signal Vref _ n, the candidate capacitor with the voltage difference between the third voltage V3 and the first predetermined voltage Vcm is selected as the selected capacitor.

For another example, in another embodiment, the operation logic of the selection logic 240 may be designed to select a candidate capacitor having a voltage difference between the first voltage V1 and the first predetermined voltage Vcm, as the selected capacitor, when the input signal Vin is between the first reference signal Vref _1 and the second reference signal Vref _ 2; when the input signal Vin is between the second reference signal Vref _2 and the third reference signal Vref _ n, a candidate capacitor with a voltage across close to a voltage difference between the second voltage V2 and the first predetermined voltage Vcm is selected as a selected capacitor; and when the input signal Vin is greater than the third reference signal Vref _ n, the candidate capacitor with the voltage difference between the third voltage V3 and the first predetermined voltage Vcm is selected as the selected capacitor.

As mentioned above, the first capacitor set and the second capacitor set can be charged in turn. The selection logic 240 may select a candidate capacitor with an appropriate voltage as the selected capacitor to be coupled to the second gain stage 120 from the charged capacitor set according to the selection principle.

For example, in the first operation period T1, the selection logic 240 selects a portion of the capacitors from the first capacitor bank (in this case, the first to third capacitors 131 to 135) having an appropriate voltage step-over value capable of reducing the charging or discharging time required subsequently as the selected capacitors to be coupled to the second gain stage 120 according to the comparison result of the comparators 210 to 230 at that time, and generates a plurality of control signals for controlling the first to sixth switches 141 to 146 to couple the selected capacitors to the second gain stage 120. During the first operation period T1, the selection logic 240 also generates a plurality of control signals for controlling the seventh to twelfth switches 161-166 to switch all the candidate capacitors of the second capacitor bank (in this case, the fourth to sixth candidate capacitors 151-155) to the charging mode without being coupled to the second gainstage 120.

In the following second operation period T2, the selection logic 240 selects a part of the candidate capacitors having an appropriate voltage across the group of second capacitors that has been charged according to the comparison result of the comparators 210-230 at the time, as the selected capacitors to be coupled to the second gain stage 120, and generates a plurality of control signals for controlling the seventh to twelfth switches 161-166 to couple the selected capacitors to the second gain stage 120. During the second operation period T2, the selection logic 240 also generates a plurality of control signals for controlling the first to sixth switches 141-146 to switch all the candidate capacitors in the first capacitor bank to the charging mode without being coupled to the second gain stage 120.

During subsequent operation periods, selection logic 240 may re-select an appropriate candidate capacitor from the charged capacitor bank as the selected capacitor based on the comparison of comparators 210-230 at that time.

Therefore, before the capacitor selection circuit 170 selects an appropriate capacitor from the first capacitor bank (in this case, the first to third capacitor candidates 131 to 135) to be coupled to the second gainstage 120, the first to third capacitor candidates 131 to 135 are pre-charged to have different voltage levels, respectively. Similarly, the fourth to sixth candidate capacitors 151-155 are pre-charged to have different voltage levels before the capacitor selection circuit 170 selects the appropriate candidate capacitor to be coupled to the second gain stage 120 from the second capacitor bank (in this case, the fourth to sixth candidate capacitors 151-155).

As can be seen from the foregoing description, the selected capacitor coupled to the second gain stage 120 by the capacitor selection circuit 170 has been pre-charged to have an appropriate voltage level during each operation period. Therefore, the charging or discharging time required after the selected capacitor is coupled to the second gain stage 120 can be greatly reduced. Thus, the response speed of the operational amplifier 100 can be effectively increased, and the overall performance or operation speed of the circuit using the operational amplifier 100 can be improved.

In addition, the aforementioned mechanism of alternately charging the candidate capacitors 131-135 and 151-155 in groups and alternately providing the feedback capacitors to be coupled to the second gainstage 120 can further shorten the charging or discharging time required after the selected capacitors are coupled to the second gainstage 120, thereby further increasing the response speed of the operational amplifier 100 and further increasing the overall performance or operation speed of the circuit using the operational amplifier 100.

In practical applications, the operational amplifier 100 may alternatively be configured to operate with two different circuits, so that the same operational amplifier 100 can be shared by the two different circuits, thereby reducing the area of the whole circuit.

For example, the operational amplifier 100 may be applied to various types of pipelined analog-to-digital converters (pipelined ADCs) and shared by two different circuit stages.

Referring to fig. 3, a simplified functional block diagram of a pipeline adc 300 according to a first embodiment of the invention is shown. Fig. 4 is a simplified, partial functional block diagram of an embodiment of a pipelined adc 300.

The pipelined adc 300 is used for converting an analog input signal Sin into a digital output signal Dout, and includes a plurality of successive circuit stages (e.g., the exemplary circuit stages 301-304 shown in fig. 3), a back-end adc 305, and a timing adjustment and error correction circuit 306. In the embodiment of fig. 3, the pipelined analog-to-digital converter 300 belongs to a single-channel pipelined analog-to-digital converter.

The circuit stages 301-304 in the pipelined analog-to-digital converter 300 all have a similar circuit architecture. For convenience of explanation, only the circuit stage 302 belonging to the nth stage and the circuit stage 303 belonging to the N +1 st stage are used as examples in the following.

As shown in fig. 3, the circuit stage 302 includes a first adc 310 and a first multiplying dac 320. The first analog-to-digital converter 310 is used for performing an analog-to-digital conversion process on the input signal (referred to as the first input signal Vin _ 1) of the circuit stage 302. The first multiplying digital-to-analog converter 320 is configured to perform a digital-to-analog conversion process on the first input signal Vin _1 according to a digital value generated by the first analog-to-digital converter 310 to generate and transmit an analog signal Vin _2 to the next circuit stage 303.

The first multiplying digital-to-analog converter 320 includes a first sample-and-hold circuit 322, a first digital-to-analog converter 324, a first subtractor 326, and a first operational amplifier 328.

The first sample and hold circuit 322 is configured to sample and hold the first input signal Vin _ 1. The first digital-to-analog converter 324 is configured to perform a digital-to-analog conversion process on the digital value generated by the first analog-to-digital converter 310 to generate a first analog signal corresponding to the first input signal Vin _ 1. The outputs of the first sample-and-hold circuit 322 and the first digital-to-analog converter 324 are processed by a first subtractor 326 to form a first subtraction signal S1. The first operational amplifier 328 amplifies the first subtracted signal S1 to generate the analog signal Vin _2.

Similarly, the circuit stage 303 includes a second adc 330 and a second multiplying dac 340. The second adc 330 is used for performing an analog-to-digital conversion process on the input signal (i.e., the aforementioned analog signal Vin _2, referred to as the second input signal Vin _ 2) of the circuit stage 303. The second adc 340 is configured to perform a digital-to-analog conversion process on the second input signal Vin _2 according to a digital value generated by the second adc 330, so as to generate and transmit an analog signal to the next circuit stage.

The second multiplying digital-to-analog converter 340 includes a second sample-and-hold circuit 342, a second digital-to-analog converter 344, a second subtractor 346, and a second operational amplifier 348.

The second sample and hold circuit 342 is configured to sample and hold the second input signal Vin _2. The second digital-to-analog converter 344 is configured to perform a digital-to-analog conversion process on the digital value generated by the second analog-to-digital converter 330 to generate a second analog signal corresponding to the second input signal Vin _2. The outputs of the second sample-and-hold circuit 342 and the second digital-to-analog converter 344 are processed by the second subtractor 346 to form a second subtracted signal S2. The second operational amplifier 348 amplifies the second subtracted signal S2 to generate an analog signal to be transmitted to the next circuit stage.

The circuit structure and operation of the other circuit stages 301 and 304 in the pipeline adc 300 are the same as those of the circuit stages 302 and 303, and therefore, the description of the circuit structures of the circuit stages 302 and 303 is also applicable to the other circuit stages 301 and 304.

The digital values generated by each stage are sent to the timing adjustment and error correction circuit 306. In addition, the back-end adc 305 converts the analog signal from the previous stage 304 into a digital value, and sends the digital value to the timing adjustment and error correction circuit 306.

The timing adjustment and error correction circuit 306 performs a timing adjustment stage error correction operation according to a plurality of digital values from all the circuit stages and the back-end adc 305 to generate a digital output signal Dout corresponding to the analog input signal Sin.

As can be seen from the foregoing description, each circuit stage of the pipelined adc 300 requires an operational amplifier to amplify the relevant signal.

In operation, the operational amplifiers in each circuit stage do not need to be in signal amplification operation at all times. For example, when the first operational amplifier 328 of the nth stage 302 is performing signal amplification operation, the second operational amplifier 348 of the (N + 1) th stage 303 is not performing signal amplification operation because the second sample and hold circuit 342 is performing sampling operation. For another example, when the second operational amplifier 348 in the N +1 th stage 303 performs the signal amplifying operation, the first operational amplifier 328 in the nth stage 302 does not need to perform the signal amplifying operation because the first sample and hold circuit 322 performs the sampling operation.

Therefore, in the pipelined adc 300, a circuit stage of an odd-numbered stage may share the same operational amplifier 100 as a circuit stage of another even-numbered stage.

For example, fig. 4 is a simplified partial functional block diagram of an embodiment of the pipelined adc 300 of fig. 3.

The first switched capacitor network 420 of fig. 4 is configured to perform a sample and hold operation on the first input signal Vin _1, and can be used to implement the function of the first sample and hold circuit 322 of the circuit stage 302. The second switched capacitor network 440 of fig. 4 is configured to sample and hold the second input signal Vin _2, and can be used to implement the function of the second sample-and-hold circuit 342 of the circuit stage 303.

In the embodiment of fig. 4, the first switched capacitor network 420 includes a first capacitor 421, a second capacitor 423, a thirteenth switch 425, a fourteenth switch 427, and a fifteenth switch 429. The second switched capacitor network 440 includes a third capacitor 441, a fourth capacitor 443, a sixteenth switch 445, a seventeenth switch 447, and an eighteenth switch 449. The aforementioned switching operations of the thirteenth switch 425, the fourteenth switch 427, the fifteenth switch 429, the sixteenth switch 445, the seventeenth switch 447 and the eighteenth switch 449 may be controlled by the timing adjustment and error correction circuit 306 or other timing control circuits (not shown) in the pipelined adc 300.

In the first switched capacitor network 420, a thirteenth switch 425 is coupled to the first end of the first capacitor 421 for selectively coupling the first capacitor 421 to the input signal (in this case, the first input signal Vin _ 1) of the circuit stage 302 or the output signal Vout of the operational amplifier 100. The fourteenth switch 427 is coupled to the first end of the second capacitor 423 for selectively coupling the second capacitor 423 to the first input signal Vin _1 or a predetermined voltage Vr1. The fifteenth switch 429 is coupled to the second end of the first capacitor 421 and the second end of the second capacitor 423 for selectively coupling the first capacitor 421 and the second capacitor 423 together to the first subtractor 326 or another predetermined voltage Vcmi. In practice, the predetermined voltage Vr1 may be a fixed voltage, or a common mode voltage of the first digital-to-analog converter 324, and the predetermined voltage Vcmi may be a fixed voltage, or a common mode voltage of the first switched capacitor network 420.

In the second switched capacitor network 440, the sixteenth switch 445 is coupled to the first end of the third capacitor 441 for selectively coupling the third capacitor 441 to the input signal (in this case, the second input signal Vin _ 2) of the circuit stage 303 or the output signal Vout of the operational amplifier 100. The seventeenth switch 447 is coupled to the first end of the fourth capacitor 443 for selectively coupling the fourth capacitor 443 to the second input signal Vin _2 or a predetermined voltage Vr2. The eighteenth switch 449 is coupled to the second terminal of the third capacitor 441 and the second terminal of the fourth capacitor 443 for selectively coupling the third capacitor 441 and the fourth capacitor 443 together to the second subtractor 346 or the predetermined voltage Vcmi. In practice, the predetermined voltage Vr2 may be a fixed voltage or a common mode voltage of the second digital-to-analog converter 344.

In practice, the

aforementioned switches

425, 427, 429, 445, 447, 449 can be implemented by a combination of transistors, or by a combination of transistors and appropriate logic gates.

The

functional blocks

324, 326, 344 and 346 of fig. 4 operate in the same manner as the corresponding functional blocks of fig. 3, respectively.

Please note that, in the pipelined adc 300 of fig. 4, the functions of the first operational amplifier 328 and the second operational amplifier 348 of fig. 3 are implemented by the same operational amplifier 100. Specifically, the operational amplifier 100 plays the role of both the first operational amplifier 328 and the second operational amplifier 348 in fig. 3 during different operation periods.

For example, when the operational amplifier 100 in fig. 4 is to realize the function of the first operational amplifier 328 in fig. 3, the operational amplifier 100 can use the first subtraction signal S1 as the first signal N1 and use the first input signal Vin _1 as the input signal Vin. Similarly, when the operational amplifier 100 in fig. 4 is to realize the function of the second operational amplifier 348 in fig. 3, the operational amplifier 100 can use the second subtraction signal S2 as the first signal N1 and use the second input signal Vin _2 as the input signal Vin.

In one embodiment, as shown in fig. 4, an output switch 480 coupled to the first subtractor 326, the second subtractor 346, and the first gain stage 110, and an input switch 490 coupled to the capacitance selection circuit 170 may be disposed in the pipelined adc 300. The output switch 480 may be configured to selectively output the first subtraction signal S1 or the second subtraction signal S2 to the first gain stage 110 as the first signal N1. The input switch 490 may be configured to selectively output the first input signal Vin _1 or the second input signal Vin _2 to the capacitance selection circuit 170 as the aforementioned input signal Vin.

Similar to the embodiment of fig. 1, the operational amplifier 100 generates the output signal Vout according to the first signal N1, and switches the coupling manner of the candidate capacitors 131-135 and 151-155 according to the magnitude of the input signal Vin, so that only a portion of the candidate capacitors 131-135 and 151-155 are used to participate in the generation operation of the output signal Vout at the same time.

In operation, the operational amplifier 100 may alternately play the role of both the first operational amplifier 328 and the second operational amplifier 348 of fig. 3. For example, the operational amplifier 100 may play the role of the first operational amplifier 328 in fig. 3 in a specific operation period (e.g., the aforementioned first operation period T1) in which the circuit stage 302 needs to amplify the first subtraction signal S1. Thereafter, in the next operation period (e.g., the aforementioned second operation period T2) in which the circuit stage 303 needs to perform the amplification operation on the second subtraction signal S2, the operational amplifier 100 may play the role of the second operational amplifier 348 in fig. 3 again.

In the first operation period T1 of the operational amplifier 100 requiring the amplification operation of the first subtraction signal S1 in the circuit stage 302, the timing adjustment and error correction circuit 306 (or other timing control circuit) can control the thirteenth switch 425 to couple the first terminal of the first capacitor 421 to the output signal Vout of the operational amplifier 100, synchronously control the fourteenth switch 427 to couple the first terminal of the second capacitor 423 to the predetermined voltage Vr1, and synchronously control the fifteenth switch 429 to couple the second terminal of the first capacitor 421 and the second terminal of the second capacitor 423 together to the first subtractor 326. In the first operation period T1, the timing adjustment and error correction circuit 306 (or other timing control circuit) may control the sixteenth switch 445 to couple the first terminal of the third capacitor 441 to the second input signal Vin _2, synchronously control the seventeenth switch 447 to couple the first terminal of the fourth capacitor 443 to the second input signal Vin _2, and synchronously control the eighteenth switch 449 to couple the second terminal of the third capacitor 441 and the second terminal of the fourth capacitor 443 together to the predetermined voltage Vcmi. At this time, the timing adjustment and error correction circuit 306 (or other timing control circuit) can control the output switch 480 to output the first subtraction signal S1 to the first gain stage 110, and control the input switch 490 to output the first input signal Vin _1 to the capacitance selection circuit 170.

Thereafter, in the second operation period T2 in which the operational amplifier 100 needs to amplify the second subtraction signal S2 in the circuit stage 303, the timing adjustment and error correction circuit 306 (or other timing control circuit) may control the thirteenth switch 425 to couple the first end of the first capacitor 421 to the first input signal Vin _1, synchronously control the fourteenth switch 427 to couple the first end of the second capacitor 423 to the first input signal Vin _1, and synchronously control the fifteenth switch 429 to couple the second end of the first capacitor 421 and the second end of the second capacitor 423 together to the predetermined voltage Vcmi. In the second operation period T2, the timing adjustment and error correction circuit 306 (or other timing control circuit) may control the sixteenth switch 445 to couple the first terminal of the third capacitor 441 to the output signal Vout of the operational amplifier 100, synchronously control the seventeenth switch 447 to couple the first terminal of the fourth capacitor 443 to the predetermined voltage Vr2, and synchronously control the eighteenth switch 449 to couple the second terminal of the third capacitor 441 and the second terminal of the fourth capacitor 443 together to the second subtractor 346. At this time, the timing adjustment and error correction circuit 306 (or other timing control circuit) can control the output switch 480 to output the second subtraction signal S2 to the first gain stage 110, and control the input switch 490 to output the second input signal Vin _2 to the capacitance selection circuit 170.

As a result, the operational amplifier 100 only amplifies the first subtraction signal S1 in the circuit stage 302 during the first operation period T1, and only amplifies the second subtraction signal S2 in the circuit stage 303 during the second operation period T2.

As long as the timing adjustment and error correction circuit 306 (or other timing control circuit) properly sets the switching timings of the

aforementioned switches

425, 427, 429, 445, 447, 449, 480, and 490, the operational amplifier 100 can alternately operate with other circuits in different circuit stages of the pipelined adc 300, so that different circuit stages can share the same operational amplifier 100.

As can be seen from the above description, the combination of the

functional blocks

420, 440, 324, 326, 344, and 346 in fig. 4 is equivalent to one of the embodiments of the previous stage circuit 102 in fig. 1.

The selected capacitor, which is coupled to the second gain stage 120 during each operation period, has been precharged to the appropriate voltage level. Therefore, the charging or discharging time required after the selected capacitor is coupled to the second gainstage 120 is greatly reduced. As a result, the response speed of the operational amplifier 100 can be effectively increased, and the overall performance or operation speed of the pipelined adc 300 can be improved.

In addition, the aforementioned mechanism of alternately charging the candidate capacitors 131-135 and 151-155 in groups and alternately providing the feedback capacitors to be coupled to the second gainstage 120 can further shorten the charging or discharging time required after the selected capacitors are coupled to the second gainstage 120, thereby further increasing the response speed of the operational amplifier 100 and further increasing the overall performance or operation speed of the pipelined adc 300.

The above descriptions regarding the connection relationship, implementation, operation, and related advantages of the components of the operational amplifier 100 in fig. 1 also apply to the embodiment of fig. 4. For the sake of brevity, the description is not repeated here.

Since the same operational amplifier 100 can alternatively operate with other circuit elements in two different circuit stages 302 and 303, the two different circuit stages 302 and 303 only need to share the same operational amplifier 100 during operation. As a result, the number of operational amplifiers required to be disposed in the pipelined adc 300 can be greatly reduced, thereby reducing the overall circuit area of the pipelined adc 300.

It should be noted that in the foregoing embodiment, the circuit stages 302 and 303 sharing the same operational amplifier 100 are two adjacent circuit stages in the same channel, which is an exemplary embodiment and not a limitation to the practical implementation of the present invention. In practice, two circuit stages sharing the same operational amplifier 100 are not limited to two adjacent circuit stages.

Referring to fig. 5, a simplified functional block diagram of a pipelined adc 500 according to a second embodiment of the invention is shown. Fig. 6 is a simplified, partial functional block diagram of an embodiment of a pipelined adc 500.

The pipelined adc 500 is a dual-channel pipelined adc that converts an analog input signal Sin into two digital output signals Dout1 and Dout2.

The pipelined adc 500 comprises, in addition to the aforementioned plurality of circuit stages 301-304 belonging to the same channel, the back-end adc 305, and the timing adjustment and error correction circuit 306, a plurality of successive circuit stages belonging to another channel (e.g., the exemplary circuit stages 501-504 shown in fig. 5), a back-end adc 505, and a timing adjustment and error correction circuit 506.

The circuit architectures of the two channels of the pipelined adc 500 are the same, except that the timing of the operations of the circuits in the two channels are different. The circuit stages 301-304 and 501-504 in the pipelined adc 500 have the same circuit structure and operation as the circuit stages 302 and 303 described above. For example, the nth stage (i.e., the circuit stage 502) of the second channel includes a second adc 530 and a second multiplying dac 540. The second analog-to-digital converter 530 is used for performing an analog-to-digital conversion process on the input signal (referred to as the second input signal Vin _ 2) of the circuit stage 502. The second adc 540 is used for performing a digital-to-analog conversion process on the second input signal Vin _2 according to a digital value generated by the second adc 530 to generate and transmit an analog signal to the next circuit stage.

Similar to the second multiplying digital-to-analog converter 340, the second multiplying digital-to-analog converter 540 includes a second sample-and-hold circuit 542, a second digital-to-analog converter 544, a second subtractor 546, and a second operational amplifier 548. The second sample and hold circuit 542 is arranged to sample and hold the second input signal Vin _2. The second digital-to-analog converter 544 is configured to perform a digital-to-analog conversion process on the digital value generated by the second analog-to-digital converter 530 to generate a second analog signal. The outputs of the second sample and hold circuit 542 and the second digital-to-analog converter 544 are processed by a second subtractor 546 to form a second subtracted signal S2. The second operational amplifier 548 amplifies the second subtracted signal S2 to generate an analog signal to be passed to the next circuit stage.

The circuit configuration description of the circuit stages 302 and 303 also applies to the circuit stages 301-304 and 501-504 in fig. 5.

As in the previous embodiment of fig. 3, each circuit stage of the pipelined analog-to-digital converter 500 requires an operational amplifier to amplify the relevant signal, but the operational amplifier in each circuit stage does not need to operate for signal amplification all the time.

For example, when the first operational amplifier 328 in the nth stage (i.e., the circuit stage 302) of the first channel is performing signal amplification operation, the second operational amplifier 548 in the nth stage (i.e., the circuit stage 502) of the second channel does not need to perform signal amplification operation because the second sample and hold circuit 542 is performing sampling operation. For another example, when the second operational amplifier 548 in the circuit stage 502 is performing signal amplification operation, the first operational amplifier 328 in the circuit stage 302 does not need to perform signal amplification operation because the first sample and hold circuit 322 is performing sampling operation.

Therefore, in the pipelined adc 500, an odd-numbered stage in the first channel can share the same operational amplifier 100 as an odd-numbered stage in the second channel. Similarly, an even-numbered stage in the first channel may share the same operational amplifier 100 with an even-numbered stage in the second channel.

For example, fig. 6 is a simplified partial functional block diagram of an embodiment of the pipelined adc 500 of fig. 5.

The second switched capacitor network 640 of fig. 6 is configured to perform a sample-and-hold operation on the second input signal Vin _2, and can be used to implement the function of the second sample-and-hold circuit 542 of the circuit stage 502.

In the second switched capacitor network 640, the sixteenth switch 645 is coupled to the first end of the third capacitor 641 for selectively coupling the third capacitor 641 to the input signal (in this case, the second input signal Vin _ 2) of the circuit stage 502 or the output signal Vout of the operational amplifier 100. The seventeenth switch 647 is coupled to the first end of the fourth capacitor 643, for selectively coupling the fourth capacitor 643 to the second input signal Vin _2 or the predetermined voltage Vr2. An eighteenth switch 649 is coupled to the second terminal of the third capacitor 641 and the second terminal of the fourth capacitor 643 for selectively coupling the third capacitor 641 and the fourth capacitor 643 together to the second subtractor 546 or the predetermined voltage Vcmi. The switching operations of the sixteenth switch 645, the seventeenth switch 647 and the eighteenth switch 649 can be controlled by the timing adjustment and error correction circuit 506 or other timing control circuits (not shown) in the pipeline adc 500. In practice, the predetermined voltage Vr2 may be a fixed voltage or a common mode voltage of the second digital-to-analog converter 544.

In practice, the

switches

645, 647, and 649 can be implemented by a combination of transistors, or a combination of transistors with appropriate logic gates.

Please note that in the pipelined adc 500 of fig. 6, the functions of the first operational amplifier 328 and the second operational amplifier 548 of fig. 5 are implemented by the same operational amplifier 100. Specifically, the operational amplifier 100 plays the role of both the first operational amplifier 328 and the second operational amplifier 548 in FIG. 5 during different operation periods.

For example, when the operational amplifier 100 in fig. 6 is to realize the function of the first operational amplifier 328 in fig. 5, the operational amplifier 100 can use the first subtraction signal S1 as the first signal N1 and use the first input signal Vin _1 as the input signal Vin. Similarly, when the operational amplifier 100 in fig. 6 is to realize the function of the second operational amplifier 548 in fig. 5, the operational amplifier 100 can use the second subtraction signal S2 as the first signal N1 and use the second input signal Vin _2 as the input signal Vin.

As in the embodiment of fig. 4, the output switch 480 may be configured to selectively output the first subtraction signal S1 or the second subtraction signal S2 to the first gain stage 110 as the first signal N1. The input switch 490 may be configured to selectively output the first input signal Vin _1 or the second input signal Vin _2 to the capacitance selection circuit 170 as the aforementioned input signal Vin. In the embodiment, when the output switch 480 outputs the first subtraction signal S1 to the first gain stage 110, the input switch 490 outputs the first input signal Vin _1 to the capacitance selection circuit 170, and when the output switch 480 outputs the second subtraction signal S2 to the first gain stage 110, the input switch 490 outputs the second input signal Vin _2 to the capacitance selection circuit 170.

The

functional blocks

420, 324, 326, 544 and 546 in FIG. 6 are all configured and operated in the same manner as the corresponding functional blocks in FIG. 4.

In operation, the operational amplifier 100 may alternately serve as both the first operational amplifier 328 and the second operational amplifier 548 of FIG. 5. For example, the operational amplifier 100 may play a role of the first operational amplifier 328 in fig. 5 in a specific operation period (e.g., the aforementioned first operation period T1) in which the circuit stage 302 needs to amplify the first subtraction signal S1. Thereafter, in the next operation period (for example, the aforementioned second operation period T2) in which the circuit stage 502 needs to amplify the second subtraction signal S2, the operational amplifier 100 may play the role of the second operational amplifier 548 in fig. 5.

In the first operation period T1 of the operational amplifier 100 requiring the amplification operation of the first subtraction signal S1 in the circuit stage 302, the timing adjustment and error correction circuit 306 (or other timing control circuit) can control the thirteenth switch 425 to couple the first terminal of the first capacitor 421 to the output signal Vout of the operational amplifier 100, synchronously control the fourteenth switch 427 to couple the first terminal of the second capacitor 423 to the predetermined voltage Vr1, and synchronously control the fifteenth switch 429 to couple the second terminal of the first capacitor 421 and the second terminal of the second capacitor 423 together to the first subtractor 326. In the first operation period T1, the timing adjustment and error correction circuit 506 (or other timing control circuit) may control the sixteenth switch 645 to couple the first terminal of the third capacitor 641 to the second input signal Vin _2, synchronously control the seventeenth switch 647 to couple the first terminal of the fourth capacitor 643 to the second input signal Vin _2, and synchronously control the eighteenth switch 649 to couple the second terminal of the third capacitor 641 and the second terminal of the fourth capacitor 643 together to the predetermined voltage Vcmi. At this time, the timing adjustment and

error correction circuits

306 and 506, or other timing control circuits, can control the output switch 480 to output the first subtraction signal S1 to the first gain stage 110, and control the input switch 490 to output the first input signal Vin _1 to the capacitance selection circuit 170.

Thereafter, in the second operation period T2 of the operational amplifier 100, during which the second subtraction signal S2 in the circuit stage 502 needs to be amplified, the timing adjustment and error correction circuit 306 (or other timing control circuit) can control the thirteenth switch 425 to couple the first terminal of the first capacitor 421 to the first input signal Vin _1, synchronously control the fourteenth switch 427 to couple the first terminal of the second capacitor 423 to the first input signal Vin _1, and synchronously control the fifteenth switch 429 to couple the second terminal of the first capacitor 421 and the second terminal of the second capacitor 423 together to the predetermined voltage Vcmi. In the second operation period T2, the timing adjustment and error correction circuit 506 (or other timing control circuit) may control the sixteenth switch 645 to couple the first end of the third capacitor 641 to the output signal Vout of the operational amplifier 100, synchronously control the seventeenth switch 647 to couple the first end of the fourth capacitor 643 to the predetermined voltage Vr2, and synchronously control the eighteenth switch 649 to couple the second end of the third capacitor 641 and the second end of the fourth capacitor 643 together to the second subtractor 546. At this time, the timing adjusting and

error correcting circuits

306, 506, or other timing control circuits can control the output switch 480 to output the second subtraction signal S2 to the first gain stage 110, and control the input switch 490 to output the second input signal Vin _2 to the capacitance selecting circuit 170.

As a result, the operational amplifier 100 only amplifies the first subtraction signal S1 in the circuit stage 302 during the first operation period T1, and only amplifies the second subtraction signal S2 in the circuit stage 502 during the second operation period T2.

As long as the timing adjustment and

error correction circuits

306, 506, or other timing control circuits appropriately set the switching timings of the

aforementioned switches

425, 427, 429, 645, 647, 649, 480, and 490, the operational amplifier 100 can alternately operate with other circuits in different circuit stages of the pipelined adc 500, so that different circuit stages can share the same operational amplifier 100.

As can be seen from the above description, the combination of

functional blocks

420, 640, 324, 326, 544 and 546 in fig. 6 corresponds to another embodiment of previous stage circuit 102 in fig. 1.

The selected capacitor, which is coupled to the second gain stage 120 during each operation period, has been precharged to the appropriate voltage level. Therefore, the charging or discharging time required after the selected capacitor is coupled to the second gainstage 120 is greatly reduced. As a result, the response speed of the operational amplifier 100 can be effectively increased, and the overall performance or operation speed of the pipeline adc 500 can be improved.

In addition, the aforementioned mechanism of alternately charging the candidate capacitors 131-135 and 151-155 in groups and alternately providing the feedback capacitors to be coupled to the second gainstage 120 can further shorten the charging or discharging time required after the selected capacitors are coupled to the second gainstage 120, thereby further increasing the response speed of the operational amplifier 100 and further increasing the overall performance or operation speed of the pipelined adc 500.

The above descriptions regarding the connection relationship, implementation, operation, and related advantages of the components of the operational amplifier 100 in fig. 1 also apply to the embodiment in fig. 6. For the sake of brevity, the description is not repeated here.

Since the same operational amplifier 100 can alternatively operate with other circuit elements in the circuit stages 302 and 502 belonging to different channels, the circuit stages 302 and 502 only need to share the same operational amplifier 100 during operation. As a result, the number of operational amplifiers required to be disposed in the pipelined adc 500 can be greatly reduced, thereby reducing the overall circuit area of the pipelined adc 500.

In practice, the operational amplifier 100 can also be applied to the architecture of a sample-and-hold amplifier. For example, fig. 7 is a simplified functional block diagram of a sample-and-hold amplifier 700 according to an embodiment of the present invention.

The sample-and-hold amplifier 700 comprises a switched capacitor network 702 and the operational amplifier 100, wherein the switched capacitor network 702 is configured to perform a sample-and-hold operation on an input signal Vin to generate a sampled signal, and to use the sampled signal as a first signal N1 to be input to the operational amplifier 100.

In the present embodiment, the switched capacitor network 702 includes a sampling capacitor 710, a first sampling switch 720, a second sampling switch 730, and a timing control circuit 740.

The first sampling switch 720 is coupled to a first end of the sampling capacitor 710 for selectively coupling the sampling capacitor 710 to the input signal Vin or the output signal Vout.

The second sampling switch 730 is coupled to a second terminal of the sampling capacitor 710 for selectively coupling the sampling capacitor 710 to a predetermined voltage Vcmi or an input terminal of the first gain stage 110. In practice, the predetermined voltage Vcmi may be a fixed voltage or a common mode voltage of the switched capacitor network 702.

In practice, the

switches

720 and 730 can be implemented by a combination of transistors, or by a combination of transistors and appropriate logic gates.

The timing control circuit 740 is coupled to the first sampling switch 720 and the second sampling switch 730, and configured to control the switching timing of the first sampling switch 720 and the second sampling switch 730.

For example, when the timing control circuit 740 controls the first sampling switch 720 to couple the sampling capacitor 710 to the input signal Vin, the timing control circuit 740 controls the second sampling switch 730 to couple the sampling capacitor 710 to the predetermined voltage Vcmi. When the timing control circuit 740 controls the first sampling switch 720 to couple the sampling capacitor 710 to the output signal Vout, the timing control circuit 740 controls the second sampling switch 730 to couple the sampling capacitor 710 to the input terminal of the first gain stage 110.

The operational amplifier 100 is coupled to the switched capacitor network 702, and configured to generate an output signal Vout according to a first signal N1 output by the switched capacitor network 702, and switch the coupling manner of the candidate capacitors 131-135 and 151-155 according to a magnitude of an input signal Vin of the switched capacitor network 702, such that only a portion of the candidate capacitors 131-135 and 151-155 are used to participate in the generation operation of the output signal Vout at the same time.

As can be seen from the foregoing description, the switched capacitor network 702 in fig. 7 corresponds to another embodiment of the previous stage circuit 102 in fig. 1.

Each time the selected capacitor coupled to the second gain stage 120 has been precharged to the appropriate voltage level. Therefore, the charging or discharging time required after the selected capacitor is coupled to the second gain stage 120 can be greatly reduced. As a result, the response speed of the operational amplifier 100 can be effectively increased, and the overall performance or operation speed of the sample-and-hold amplifier 700 can be improved.

In addition, the aforementioned mechanism for alternately charging the candidate capacitors 131-135 and 151-155 in groups and for alternately providing the feedback capacitors to be coupled to the second gain stage 120 can further shorten the charging or discharging time required after the selected capacitors are coupled to the second gain stage 120, thereby further increasing the response speed of the operational amplifier 100 and further increasing the overall performance or operation speed of the sample-and-hold amplifier 700.

The above descriptions regarding the connection relationship, implementation, operation, and related advantages of the components of the operational amplifier 100 in fig. 1 also apply to the embodiment of fig. 7. For the sake of brevity, the description is not repeated here.

It should be noted that the number of elements in the foregoing embodiments is only an exemplary embodiment, and is not intended to limit the actual implementation manner of the present invention. For example, in some embodiments, the number of comparators in the capacitor selection circuit 170 may be increased, so that the selection logic 240 can more accurately control the magnitude range of the input signal Vin. For example, in some embodiments, the number of comparators in the capacitance selection circuit 170 may be reduced to two to reduce the circuit complexity of the selection logic 240.

In some embodiments requiring a slightly lower response speed of the operational amplifier 100, the second capacitor bank and the associated switches may be omitted, and the second gain stage 120 may be operated with a single capacitor bank including at least three candidate capacitors.

In some embodiments, the output terminal of the first digital-to-analog converter 324 in the embodiment of fig. 4 or fig. 6 may also be connected to the fourteenth switch 427 to provide the predetermined voltage Vr1. Under this structure, when the thirteenth switch 425 couples the first terminal of the first capacitor 421 to the output signal Vout of the operational amplifier 100 and the fourteenth switch 427 couples the first terminal of the second capacitor 423 to the predetermined voltage Vr1, the first subtraction signal S1 is formed at the coupling point of the second terminal of the first capacitor 421 and the second terminal of the second capacitor 423. In this case, when the first gain stage 110 needs to be coupled to the first subtraction signal S1, the fifteenth switch 429 may couple the second terminal of the first capacitor 421 and the second terminal of the second capacitor 423 to the input terminal of the first gain stage 110 together, and the first subtractor 326 is omitted.

Similarly, the output terminal of the second digital-to-analog converter 344 (or 544) in the embodiment of fig. 4 or 6 may also be connected to the seventeenth switch 447 (or 647) to provide the predetermined voltage Vr2. Under this structure, when the sixteenth switch 445 (or 645) couples the first terminal of the third capacitor 441 (or 641) to the output signal Vout of the operational amplifier 100 and the seventeenth switch 447 (or 647) couples the first terminal of the fourth capacitor 443 (or 643) to the predetermined voltage Vr2, the second subtraction signal S2 is formed at the coupling point of the second terminal of the third capacitor 441 (or 641) and the second terminal of the fourth capacitor 443 (or 643). In this case, when the first gain stage 110 needs to be coupled with the second subtraction signal S2, the eighteenth switch 449 (or 649) may couple the second terminal of the third capacitor 441 (or 641) to the input terminal of the first gain stage 110 together with the second terminal of the fourth capacitor 443 (or 643), and the second subtractor 346 (or 546) is omitted.

In some embodiments, the output switch 480 and the input switch 490 shown in fig. 4 and 6 may be omitted. At this time, during the period when the operational amplifier 100 is going to amplify the signal of one circuit stage, the digital-to-analog converter in the multiplying digital-to-analog converter of another circuit stage may be suspended from operating, so as to avoid the first gain stage 110 receiving the erroneous subtraction signal.

Certain terms are used throughout the description and claims to refer to particular elements, and those skilled in the art may refer to like elements by different names. In the present specification and claims, the difference in name is not used as a means for distinguishing elements, but a difference in function of the elements is used as a reference for distinguishing. In the following description and in the claims, the terms "include" and "comprise" are used in an open-ended fashion, and thus should be interpreted to mean "include, but not limited to. Also, the term "coupled" is intended to include any direct or indirect connection. Therefore, if a first element is coupled to a second element, the first element can be directly connected to the second element through an electrical connection or a signal connection such as wireless transmission or optical transmission, or indirectly connected to the second element through another element or a connection means.

The description of "and/or" as used in this specification is inclusive of any combination of one or more of the listed items. In addition, any reference to singular is intended to include the plural unless the specification specifically states otherwise.

The "voltage signal" in the specification and the claims can be realized in a voltage form or a current form. The "current signal" in the specification and claims may be implemented in a voltage form or a current form.

The above are only preferred embodiments of the present invention, and all equivalent changes and modifications made by the claims of the present invention should be covered by the present invention.

Claims

1. A sample-and-hold amplifier comprising:

a switched capacitor network configured to sample and hold an input signal to generate a first signal; and

an operational amplifier coupled to the switched capacitor network and including a plurality of candidate capacitors, the operational amplifier configured to generate an output signal according to the first signal and switch a coupling manner of the candidate capacitors according to a magnitude of the input signal, such that only a portion of the candidate capacitors may be used to participate in generating the output signal at a time, wherein the operational amplifier includes:

a first gain stage, coupled to the switched capacitor network, configured to generate a second signal according to the first signal;

a second gain stage, coupled to the first gain stage, configured to generate an output signal according to the second signal;

a first candidate capacitor;

a second candidate capacitor;

a third candidate capacitor;

a first switch, coupled to a first terminal of the first candidate capacitor, for selectively coupling the first candidate capacitor to a first predetermined voltage or an input terminal of the second gain stage;

a second switch coupled to a second terminal of the first candidate capacitor for selectively coupling the first candidate capacitor to a first voltage or an output terminal of the second gain stage;

a third switch, coupled to a first end of the second candidate capacitor, for selectively coupling the second candidate capacitor to the first predetermined voltage or the input end of the second gain stage;

a fourth switch, coupled to a second terminal of the second candidate capacitor, for selectively coupling the second candidate capacitor to a second voltage or the output terminal of the second gain stage;

a fifth switch, coupled to a first end of the third candidate capacitor, for selectively coupling the third candidate capacitor to the first predetermined voltage or the input end of the second gain stage;

a sixth switch, coupled to a second terminal of the third candidate capacitor, for selectively coupling the third candidate capacitor to a third voltage or the output terminal of the second gain stage; and

and the capacitor selection circuit is coupled with a preceding stage circuit and the first switch to the sixth switch and is arranged to control the first switch to the sixth switch according to the magnitude of the input signal, so that only a part of candidate capacitors from the first candidate capacitor to the third candidate capacitor can be coupled to the second gain stage in the same time.

2. The sample-and-hold amplifier of claim 1 wherein the first through third candidate capacitors are charged to different voltage levels before a portion of the first through third candidate capacitors are coupled to the second gain stage.

3. The sample-and-hold amplifier of claim 1 wherein the switched capacitor network comprises:

a sampling capacitor;

a first sampling switch coupled to a first end of the sampling capacitor for selectively coupling the sampling capacitor to the input signal or the output signal;

a second sampling switch coupled to a second end of the sampling capacitor for selectively coupling the sampling capacitor to a second predetermined voltage or an input terminal of the first gain stage; and

a timing control circuit, coupled to the first sampling switch and the second sampling switch, configured to control a switching timing of the first sampling switch and the second sampling switch;

wherein, when the first sampling switch couples the sampling capacitor to the input signal, the second sampling switch couples the sampling capacitor to the second predetermined voltage, and when the first sampling switch couples the sampling capacitor to the output signal, the second sampling switch couples the sampling capacitor to the input terminal of the first gain stage.

4. A sample-and-hold amplifier as claimed in any one of claims 1 to 3, wherein the capacitance selection circuit comprises:

a plurality of comparators arranged to compare the input signal with a plurality of corresponding reference signals, respectively; and

and a selection logic, coupled to the comparators, configured to select a portion of the first to third candidate capacitors as a selected capacitor according to comparison results of the comparators, and generate control signals for controlling the first to sixth switches to couple the selected capacitor to the second gain stage.

5. A sample-and-hold amplifier comprising:

an operational amplifier coupled to the switched capacitor network and including a plurality of candidate capacitors, wherein the operational amplifier is configured to generate an output signal according to the first signal and switch the coupling manner of the candidate capacitors according to the magnitude of the input signal, such that only a portion of the candidate capacitors can be used to participate in the generation operation of the output signal at the same time;

wherein the plurality of candidate capacitors are divided into a first capacitor bank and a second capacitor bank, and when a part of the candidate capacitors in the first capacitor bank participate in the generation and operation of the output signal, all the candidate capacitors in the second capacitor bank are respectively charged to have different voltage values, wherein the operational amplifier comprises:

a first gain stage configured to generate a second signal according to the first signal;

a second gain stage, coupled to the first gain stage, configured to generate the output signal according to the second signal;

a first candidate capacitor;

a second candidate capacitor;

a third candidate capacitor;

a first switch coupled to a first end of the first candidate capacitor for selectively coupling the first candidate capacitor to a first predetermined voltage or an input end of the second gain stage;

a second switch, coupled to a second terminal of the first candidate capacitor, for selectively coupling the first candidate capacitor to a first voltage or an output terminal of the second gain stage;

a sixth switch, coupled to a second terminal of the third candidate capacitor, for selectively coupling the third candidate capacitor to a third voltage or the output terminal of the second gain stage;

a fourth candidate capacitor;

a fifth candidate capacitor;

a sixth candidate capacitor;

a seventh switch, coupled to a first end of the fourth candidate capacitor, for selectively coupling the fourth candidate capacitor to the first predetermined voltage or the input end of the second gain stage;

an eighth switch, coupled to a second end of the fourth candidate capacitor, for selectively coupling the fourth candidate capacitor to the first voltage or the output terminal of the second gain stage;

a ninth switch, coupled to a first end of the fifth candidate capacitor, for selectively coupling the fifth candidate capacitor to the first predetermined voltage or the input end of the second gain stage;

a tenth switch, coupled to a second terminal of the fifth candidate capacitor, for selectively coupling the fifth candidate capacitor to the second voltage or the output terminal of the second gain stage;

an eleventh switch, coupled to a first end of the sixth candidate capacitor, for selectively coupling the sixth candidate capacitor to the first predetermined voltage or the input end of the second gain stage;

a twelfth switch, coupled to a second end of the sixth candidate capacitor, for selectively coupling the sixth candidate capacitor to the third voltage or the output terminal of the second gain stage; and

a capacitor selection circuit, coupled to a preceding stage circuit and the first to twelfth switches, configured to control the first to twelfth switches according to a magnitude of the input signal, such that only a portion of the first to sixth candidate capacitors are coupled to the second gain stage at a time;

wherein, when one part of the first to third candidate capacitors is coupled to the second gain stage, the fourth to sixth candidate capacitors are respectively charged to have different voltage steps, and when one part of the fourth to sixth candidate capacitors is coupled to the second gain stage, the first to third candidate capacitors are respectively charged to have different voltage steps.

6. The sample-and-hold amplifier of claim 5 wherein the capacitance selection circuit is further configured to couple the local candidate capacitance of the first capacitance bank to the second gain stage during a first period of operation and to couple the local candidate capacitance of the second capacitance bank to the second gain stage during a second period of operation subsequent to the first period of operation.

7. The sample-and-hold amplifier of claim 5 wherein the switched capacitor network comprises:

a sampling capacitor;

8. The sample-and-hold amplifier of claim 6, wherein the capacitance selection circuit comprises:

and a selection logic, coupled to the comparators, configured to select a portion of the first to third candidate capacitors as a selected capacitor according to comparison results of the comparators during the first operation period, and generate control signals for controlling the first to sixth switches to couple the selected capacitor to the second gain stage.