CN109712990A - A kind of three-dimensional storage and preparation method thereof - Google Patents
A kind of three-dimensional storage and preparation method thereof Download PDFInfo
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- CN109712990A CN109712990A CN201910001102.8A CN201910001102A CN109712990A CN 109712990 A CN109712990 A CN 109712990A CN 201910001102 A CN201910001102 A CN 201910001102A CN 109712990 A CN109712990 A CN 109712990A
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- 238000003860 storage Methods 0.000 title claims abstract description 37
- 238000002360 preparation method Methods 0.000 title claims abstract description 16
- 238000005530 etching Methods 0.000 claims abstract description 69
- 239000004065 semiconductor Substances 0.000 claims abstract description 60
- 239000000758 substrate Substances 0.000 claims abstract description 59
- 230000004888 barrier function Effects 0.000 claims abstract description 9
- 239000000463 material Substances 0.000 claims description 35
- 238000010276 construction Methods 0.000 claims description 31
- 238000000034 method Methods 0.000 claims description 28
- PNEYBMLMFCGWSK-UHFFFAOYSA-N Alumina Chemical compound [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 claims description 16
- 238000005516 engineering process Methods 0.000 claims description 10
- 230000008569 process Effects 0.000 claims description 9
- 238000001039 wet etching Methods 0.000 claims description 6
- 239000004020 conductor Substances 0.000 claims 1
- 230000014759 maintenance of location Effects 0.000 abstract description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 6
- 239000011800 void material Substances 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- 239000000377 silicon dioxide Substances 0.000 description 3
- 229910052814 silicon oxide Inorganic materials 0.000 description 3
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- QAOWNCQODCNURD-UHFFFAOYSA-N Sulfuric acid Chemical compound OS(O)(=O)=O QAOWNCQODCNURD-UHFFFAOYSA-N 0.000 description 2
- 230000003321 amplification Effects 0.000 description 2
- 238000000231 atomic layer deposition Methods 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 238000004140 cleaning Methods 0.000 description 2
- 229910052681 coesite Inorganic materials 0.000 description 2
- 150000001875 compounds Chemical class 0.000 description 2
- 229910052906 cristobalite Inorganic materials 0.000 description 2
- 230000006870 function Effects 0.000 description 2
- 230000006872 improvement Effects 0.000 description 2
- 239000007788 liquid Substances 0.000 description 2
- 238000003199 nucleic acid amplification method Methods 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- 229910052682 stishovite Inorganic materials 0.000 description 2
- 229910052905 tridymite Inorganic materials 0.000 description 2
- 208000027418 Wounds and injury Diseases 0.000 description 1
- OBNDGIHQAIXEAO-UHFFFAOYSA-N [O].[Si] Chemical compound [O].[Si] OBNDGIHQAIXEAO-UHFFFAOYSA-N 0.000 description 1
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 1
- NCMAYWHYXSWFGB-UHFFFAOYSA-N [Si].[N+][O-] Chemical class [Si].[N+][O-] NCMAYWHYXSWFGB-UHFFFAOYSA-N 0.000 description 1
- 230000002411 adverse Effects 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 238000013500 data storage Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000002708 enhancing effect Effects 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- 208000014674 injury Diseases 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 238000003475 lamination Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 239000005416 organic matter Substances 0.000 description 1
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 1
- 229910010271 silicon carbide Inorganic materials 0.000 description 1
- 238000003325 tomography Methods 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
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Abstract
The invention discloses a kind of three-dimensional storages and preparation method thereof.Wherein, the memory includes: semiconductor substrate；Insulating layer is located in the semiconductor substrate；Stacked structure is located on the insulating layer；Channel through-hole runs through the stacked structure and the insulating layer, the upper surface of the exposure semiconductor substrate；Wherein, the insulating layer is used for the etching barrier layer when etching the channel through-hole described through the part of the stacked structure using the first etching technics as first etching technics.
Description
Technical field
The present invention relates to memory device technical fields more particularly to a kind of three-dimensional storage and preparation method thereof.
Background technique
Memory (Memory) is in modern information technologies for protecting stored memory device.With each class of electronic devices
The continuous improvement of demand to integrated level and the density of data storage, common two-dimensional storage device are increasingly difficult to meet the requirements,
In this case, three-dimensional (3D) memory comes into being.
In the internal structure of three-dimensional storage, the memory layer of electric charge store function is controlled, and as memory block ditch
The channel layer in road is respectively positioned in channel through-hole (Chanel Hole, CH)；Moreover, also have in channel through-hole and be used as lower choosing
Select the epitaxial layer (SEG) in pipe trench road；After channel through-hole is formed, before memory layer and channel layer are formed, the SEG passes through outer
Growth process is formed on the surface of the semiconductor substrate in channel through-hole.
The channel through-hole generallys use etching technics and is formed, and semiconductor lining is directly exposed in a step process
Bottom.However, in channel through-hole, especially on the surface of exposed semiconductor substrate, often being produced after forming channel through-hole
Raw a large amount of etch residues, even if these etch residues are still difficult to remove clean by cleaning；To partly led to subsequent
The SEG of the surface growth of body substrate has an adverse effect, and final influence three-dimensional storage writes resistance value and other workabilities
Energy.
Summary of the invention
In view of this, the main purpose of the present invention is to provide a kind of three-dimensional storages and preparation method thereof.
In order to achieve the above objectives, the technical scheme of the present invention is realized as follows:
The embodiment of the invention provides a kind of three-dimensional storages, comprising:
Semiconductor substrate；
Insulating layer is located in the semiconductor substrate；
Stacked structure is located on the insulating layer；
Channel through-hole runs through the stacked structure and the insulating layer, the upper surface of the exposure semiconductor substrate；
Wherein, the insulating layer is used to etch using the first etching technics through described in the part of the stacked structure
Etching barrier layer when channel through-hole as first etching technics.
In above scheme, the material of the insulating layer includes aluminium oxide.
In above scheme, the stacked structure includes the grid layer and dielectric layer being alternately stacked.
It further include epitaxial layer in above scheme,
The epitaxial layer is located in the semiconductor substrate in the channel through-hole, the lower surface of the epitaxial layer and institute
The upper surface for stating semiconductor substrate is coplanar.
The embodiment of the invention also provides a kind of preparation methods of three-dimensional storage, which comprises
Semiconductor substrate is provided, sequentially forms insulating layer and laminated construction on the semiconductor substrate；
The laminated construction is etched using the first etching technics, wherein the insulating layer is as first etching technics
Etching barrier layer so that first etching technics stops at the insulating layer；
The insulating layer is etched using the second etching technics, the upper surface of the exposure semiconductor substrate forms and runs through institute
State the channel through-hole of laminated construction and the insulating layer.
In above scheme, the material of the insulating layer includes aluminium oxide.
In above scheme, the laminated construction includes sacrificial layer and dielectric layer.
In above scheme, first etching technics is dry etch process；Second etching technics is wet etching
Technique.
In above scheme, the method also includes: after the laminated construction using the first etching technics etching,
Remove the residue of the first etching technics etching.
In above scheme, the method also includes: after forming the channel through-hole,
Form epitaxial layer in the semiconductor substrate in the channel through-hole, the lower surface of the epitaxial layer with it is described
The upper surface of semiconductor substrate is coplanar.
Three-dimensional storage and preparation method thereof provided by the embodiment of the present invention, comprising: semiconductor substrate；Insulating layer, position
In in the semiconductor substrate；Stacked structure is located on the insulating layer；Channel through-hole runs through the stacked structure and institute
State insulating layer, the upper surface of the exposure semiconductor substrate；Wherein, the insulating layer is used to etch using the first etching technics
Etching barrier layer when the channel through-hole described through the part of the stacked structure as first etching technics out.In this way,
Due to the presence of the insulating layer, so that first etching technics stops at the insulating layer, the semiconductor substrate exists
It is not exposed in first etching technics, to will not finally make in the residue of the remained on surface etching technics of semiconductor substrate
It is clean to obtain exposed semiconductor substrate surface, is conducive to the formation of subsequent structural, has ensured the working performance of three-dimensional storage.
Detailed description of the invention
Fig. 1 is the structural profile illustration of three-dimensional storage channel through-hole in the related technology；
Fig. 2 is that the partial structurtes amplification profile of the formation SEG process in three-dimensional storage channel through-hole in the related technology shows
It is intended to；
Fig. 3 is the flow diagram of the preparation method of three-dimensional storage provided in an embodiment of the present invention；
Fig. 4 to Fig. 7 is the device architecture section signal in the preparation process of three-dimensional storage provided in an embodiment of the present invention
Figure；
Fig. 8 is the structural profile illustration of three-dimensional storage provided in an embodiment of the present invention.
Description of symbols:
10,20- semiconductor substrate；
11,21- insulating layer；
12,22- laminated construction；121,221- first material layer/sacrificial layer；122,222- second material layer/dielectric layer；
223- exhaustion layer；
23- channel structure；
22'- stacked structure；
24- grid layer.
Specific embodiment
Disclosed illustrative embodiments that the present invention will be described in more detail below with reference to accompanying drawings.Although being shown in attached drawing
Exemplary embodiments of the present invention, it being understood, however, that may be realized in various forms the present invention, without that should be illustrated here
Specific embodiment limited.It is to be able to thoroughly understand the present invention, and energy on the contrary, providing these embodiments
It is enough to be fully disclosed to those skilled in the art range disclosed by the invention.
In the following description, a large amount of concrete details are given so as to provide a more thorough understanding of the present invention.So
And it is obvious to the skilled person that the present invention may not need one or more of these details and be able to
Implement.In other examples, in order to avoid confusion with the present invention, for some technical characteristics well known in the art not into
Row description；That is, not describing whole features of practical embodiments here, it is not described in detail well known function and structure.
In the accompanying drawings, for clarity, floor, area, the size of element and its relative size may be exaggerated.Phase from beginning to end
Identical element is indicated with appended drawing reference.
It should be understood that when element or layer be referred to " ... on ", " with ... it is adjacent ", " being connected to " or " being coupled to " its
When its element or layer, can directly on other elements or layer, it is adjacent thereto, be connected or coupled to other elements or layer,
Or there may be elements or layer between two parties.On the contrary, when element is referred to as " on directly existing ... ", " with ... direct neighbor ",
When " being directly connected to " or " being directly coupled to " other elements or layer, then there is no elements or layer between two parties.Although should be understood that
Can be used term first, second, third, etc. various component, assembly units, area, floor and/or part are described, these component, assembly units, area,
Layer and/or part should not be limited by these terms.These terms are used merely to distinguish a component, assembly unit, area, floor or part
With another component, assembly unit, area, floor or part.Therefore, do not depart from present invention teach that under, first element discussed below,
Component, area, floor or part are represented by second element, component, area, floor or part.And when discuss second element, component, area,
When layer or part, do not indicate that the present invention certainly exists first element, component, area, floor or part.
Spatial relation term for example " ... under ", " ... below ", " below ", " ... under ", " ...
On ", " above " etc., herein can for convenience description and be used to describe an elements or features shown in figure
With the relationship of other elements or features.It should be understood that other than orientation shown in figure, spatial relation term intention further includes
The different orientation of device in using and operating.For example, then, being described as " in other elements if the device in attached drawing is overturn
Below " or " under it " or " under it " elements or features will be oriented in other elements or features "upper".Therefore, exemplary
Term " ... below " and " ... under " it may include upper and lower two orientations.Device can additionally be orientated and (be rotated by 90 °
Or other orientations) and spatial description language as used herein correspondingly explained.
The purpose of term as used herein is only that description specific embodiment and not as limitation of the invention.Make herein
Used time, " one " of singular, "one" and " described/should " be also intended to include plural form, unless the context clearly indicates separately
Outer mode.It is also to be understood that term " composition " and/or " comprising ", when being used in this specification, determines the feature, whole
The presence of number, step, operations, elements, and/or components, but be not excluded for one or more other features, integer, step, operation,
The presence or addition of component, assembly unit and/or group.Herein in use, term "and/or" includes any of related listed item and institute
There is combination.
In order to thoroughly understand the present invention, detailed step and detailed structure will be proposed in following description, so as to
Illustrate technical solution of the present invention.Presently preferred embodiments of the present invention is described in detail as follows, however other than these detailed descriptions, this
Invention can also have other embodiments.
Fig. 1 shows the structural profile illustration of three-dimensional storage channel through-hole CH in the related technology.Wherein, the structure
It may include: semiconductor substrate 10；Insulating layer 11 is formed in the semiconductor substrate 10；Laminated construction 12 is formed in described
On insulating layer 11；Channel through-hole CH is formed by etching the laminated construction 12 and the insulating layer 11；The channel is logical
Hole CH run through the laminated construction 12 and the insulating layer 11, and extend to the upper surface of the semiconductor substrate 10 with
Under.The laminated construction 12 for example, NO lamination, i.e., be the sacrificial layer 121 of silicon nitride including material and material is silica
Dielectric layer 122；The insulating layer 11 is, for example, silicon oxide layer；At this point, due to the material that the material of insulating layer is the laminated construction
One of material, in etching process, the etch rate of the insulating layer is close with the etch rate of the laminated construction；Cause
This can directly run through laminated construction and insulation during etching forms channel through-hole CH usually in a step process
Layer.
Fig. 2 shows the partial structurtes amplifications for forming SEG process in three-dimensional storage channel through-hole in the related technology to cut open
Face schematic diagram.Wherein, as shown in the left diagram, after etching forms the channel through-hole CH, in channel through-hole CH, especially in exposure
Semiconductor substrate 10 surface on, often generate a large amount of etch residues.Next, please referring to middle figure, gone by cleaning
Except the residue, but still there is residue not to be cleaned, is attached to the surface of semiconductor substrate 10.Finally, please referring to
Right figure forms epitaxial layer SEG by epitaxial growth technology on the surface of the semiconductor substrate 10 in channel through-hole CH.It can manage
Xie Di, at the position existing for residue, due to 10 surface of semiconductor substrate can not epitaxial growth so that being produced inside SEG
Raw cavity (Void).In Fig. 2, figure (a) is shown the case where the unilateral inner wall surface of semiconductor substrate 10 forms Void, at this time will
Influence SEG resistance value；Even more serious situation is as shown in figure (b), and since residue is more, the Void of generation is larger, so that in SEG
Portion produces tomography, and may cause three-dimensional storage at this time can not work normally.
Based on this, the embodiment of the invention provides a kind of preparation methods of three-dimensional storage；Specifically refer to attached drawing 3.Institute
The method of stating includes:
Step 101 provides semiconductor substrate, sequentially forms insulating layer and laminated construction on the semiconductor substrate；
Step 102 etches the laminated construction using the first etching technics, wherein the insulating layer is as described first
The etching barrier layer of etching technics, so that first etching technics stops at the insulating layer；
Step 103 etches the insulating layer, the upper surface of the exposure semiconductor substrate, shape using the second etching technics
At the channel through-hole through the laminated construction and the insulating layer.
Below with reference to device architecture diagrammatic cross-section of the Fig. 4 into Fig. 7 in the preparation process of three-dimensional storage, to the present invention
It is further described in more detail.
Firstly, please referring to Fig. 4.In a step 101, semiconductor substrate 20 is provided, in the semiconductor substrate 20 successively
Form insulating layer 21 and laminated construction 22.
In one embodiment, the semiconductor substrate 20 may include at least one element semiconductor material (for example, silicon
(Si) substrate, germanium (Ge) substrate), at least one III-V compound semiconductor material, at least one II-VI compound semiconductor
Material, at least one organic semiconducting materials or other semiconductor materials being known in the art.
In one embodiment, the laminated construction 22 can be alternately stacked by first material layer 221 and second material layer 222
And it is formed.Here, the first material layer 221 can be sacrificial layer, such as can be by oxide skin(coating), nitride layer, silicon carbide
One of layer, silicon layer and germanium-silicon layer are formed.Second material layer 222 can be dielectric layer, and material includes but is not limited to silicon oxygen
Compound, silicon-nitride layer, silicon nitrogen oxides and other high dielectric constant (high k) dielectric layers.In the present embodiment, first material layer
221 can be formed by SiN, and second material layer 222 can be by SiO2It is formed, so that the laminated construction 22 formed includes silicon nitride-
Silicon oxide stack.First material layer and second material layer can use chemical vapor deposition (CVD) technique, plasma enhancing
It learns vapor deposition (PECVD) technique or atomic layer deposition (ALD) technique is formed；Wherein, first material layer and second material layer can
With mutually the same thickness, it is possible to have thickness different from each other.In another embodiment, the laminated construction 22 is gone back
It may include exhaustion layer 223, the exhaustion layer 223 is located at the top area of the laminated construction 22.The exhaustion layer 223 is used for
It is subsequent processing is performed etching to laminated construction 22 when, protect first material layer 221 and second material layer 222 it is injury-free；Institute
The material for stating exhaustion layer 223 may include SiON or SiO2。
Next, please referring to Fig. 5.Step 102 is executed, the laminated construction 22 is etched using the first etching technics, wherein
Etching barrier layer of the insulating layer 21 as first etching technics so that first etching technics stop at it is described absolutely
At edge layer 21.
It is to be appreciated that the material of the insulating layer 21, which is selected from, to be had under the first etching technics with the laminated construction 22
The material of larger etching selection ratio.In one embodiment, the material of the insulating layer 21 includes aluminium oxide；Alternatively, described
Insulating layer 21 is alumina layer.
In one embodiment, first etching technics can be dry etch process.After first etching technics,
Etch residue in the CH in the semiconductor substrate 20 may include organic matter.
In one embodiment, the method also includes: the laminated construction 22 is etched using the first etching technics described
Afterwards, the residue of the first etching technics etching is removed.
Next, please referring to Fig. 6.Step 103 is executed, the insulating layer 21, exposure institute are etched using the second etching technics
The upper surface of semiconductor substrate 20 is stated, the channel through-hole CH through the laminated construction 22 and the insulating layer 21 is formed.
In one embodiment, second etching technics can be wet-etching technology.It can be with by wet-etching technology
Insulating layer material is relatively easily removed, also, wet etching liquid can easily clean removal from CH.
In one embodiment, etching liquid used in the wet-etching technology includes sulfuric acid.
It is worth noting that, can select can etch absolutely when etching the insulating layer 21 using the second etching technics
Edge layer material, and the etching technics of 20 material of semiconductor substrate will not be damaged；To which the second etching technics etching can stop
In the upper surface of the semiconductor substrate 20.
Next, please referring to Fig. 7.In one embodiment, the method also includes: after forming the channel through-hole CH,
Epitaxial layer SEG, the lower surface of the epitaxial layer SEG and institute are formed in the semiconductor substrate 20 in the channel through-hole CH
The upper surface for stating semiconductor substrate 20 is coplanar.
It is to be appreciated that the upper surface due to semiconductor substrate 20 is clean, it is described outer when being formed on epitaxial layer SEG
Prolonging layer SEG can grow well, avoid the generation of void in epitaxial layer SEG, ensure the working performance of three-dimensional storage.
The method can also include: the formation channel structure 23 in the channel through-hole CH；The channel structure 23 can
To include the structures such as memory layer and channel layer.In addition, the preparation method of three-dimensional storage provided in an embodiment of the present invention is also
It may include: that the sacrificial layer 221 in laminated construction 22 is replaced into grid layer 24, form by grid layer 24 and dielectric layer 222
The stacked structure 22' of alternate group layer.In this way, the device architecture formed is as shown in Figure 8.
The embodiment of the invention also provides a kind of three-dimensional storages；Specifically refer to Fig. 8.The three-dimensional storage, comprising:
Semiconductor substrate 20；
Insulating layer 21 is located in the semiconductor substrate 20；
Stacked structure 22' is located on the insulating layer 21；
Channel through-hole CH runs through the stacked structure 22' and the insulating layer 21, the exposure semiconductor substrate 20
Upper surface；
Wherein, the insulating layer 21 is used to etch using the first etching technics through the portion of the stacked structure 22'
Etching barrier layer when dividing the channel through-hole CH as first etching technics.
It should be noted that the preparation method embodiment of three-dimensional storage provided in an embodiment of the present invention and three-dimensional storage
Belong to same design；In technical solution documented by each embodiment between each technical characteristic, in the absence of conflict, Ke Yiren
Meaning combination, which is not described herein again.
But it should be further noted that three-dimensional storage provided in an embodiment of the present invention, each technical characteristic combination is
Through can solve the technical problems to be solved by the invention；Thus, three-dimensional storage provided by the embodiment of the present invention can not
It is limited by the preparation method of three-dimensional storage provided in an embodiment of the present invention, any embodiment of the present invention that is capable of forming is provided
Three-dimensional memory structure preparation method prepared by three-dimensional storage within the scope of protection of the invention.
The foregoing is only a preferred embodiment of the present invention, is not intended to limit the scope of the present invention, it is all
Made any modifications, equivalent replacements, and improvements etc. within the spirit and principles in the present invention, should be included in protection of the invention
Within the scope of.
Claims (10)
1. a kind of three-dimensional storage characterized by comprising
Semiconductor substrate；
Insulating layer is located in the semiconductor substrate；
Stacked structure is located on the insulating layer；
Channel through-hole runs through the stacked structure and the insulating layer, the upper surface of the exposure semiconductor substrate；
Wherein, the insulating layer is used to etch using the first etching technics through the part of the stacked structure channel
Etching barrier layer when through-hole as first etching technics.
2. three-dimensional storage according to claim 1, which is characterized in that the material of the insulating layer includes aluminium oxide.
3. three-dimensional storage according to claim 1, which is characterized in that the stacked structure include be alternately stacked it is described
Grid layer and dielectric layer.
4. three-dimensional storage according to claim 1, which is characterized in that it further include epitaxial layer,
The epitaxial layer is located in the semiconductor substrate in the channel through-hole, the lower surface of the epitaxial layer and described half
The upper surface of conductor substrate is coplanar.
5. a kind of preparation method of three-dimensional storage, which is characterized in that the described method includes:
Semiconductor substrate is provided, sequentially forms insulating layer and laminated construction on the semiconductor substrate；
The laminated construction is etched using the first etching technics, wherein quarter of the insulating layer as first etching technics
Barrier layer is lost, so that first etching technics stops at the insulating layer；
The insulating layer is etched using the second etching technics, the upper surface of the exposure semiconductor substrate is formed through described folded
The channel through-hole of layer structure and the insulating layer.
6. according to the method described in claim 5, it is characterized in that, the material of the insulating layer includes aluminium oxide.
7. according to the method described in claim 5, it is characterized in that, the laminated construction includes sacrificial layer and dielectric layer.
8. according to the method described in claim 5, it is characterized in that, first etching technics is dry etch process；It is described
Second etching technics is wet-etching technology.
9. according to the method described in claim 5, it is characterized in that, the method also includes: it is described using first etching work
After skill etches the laminated construction,
Remove the residue of the first etching technics etching.
10. according to the method described in claim 5, it is characterized in that, the method also includes: forming the channel through-hole
Afterwards,
Epitaxial layer is formed in the semiconductor substrate in the channel through-hole, the lower surface of the epitaxial layer is partly led with described
The upper surface of body substrate is coplanar.
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN110349967A (en) * | 2019-06-28 | 2019-10-18 | 长江存储科技有限责任公司 | A kind of forming method and three-dimensional storage of three-dimensional storage |
| CN111162079A (en) * | 2020-01-02 | 2020-05-15 | 长江存储科技有限责任公司 | Method for forming selective epitaxial structure and method for manufacturing 3D memory device |
| CN113517311A (en) * | 2021-04-12 | 2021-10-19 | 长江先进存储产业创新中心有限责任公司 | Preparation method of three-dimensional phase change memory and three-dimensional phase change memory |
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