CN109712550B - Grid driving circuit and area scanning method - Google Patents
Grid driving circuit and area scanning method Download PDFInfo
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Abstract
The purpose of the application is to provide a grid driving circuit and a region scanning method, wherein the grid region circuit comprises an N + 1-stage shift register unit; each shift register unit comprises a primary transistor, a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a reset tube and a pull-down tube; the grid electrode of the first transistor is used for receiving an output signal fed back by the next-stage shift register unit so as to control a control signal of the grid electrode; the source electrode of the primary transistor, the drain electrode of the first transistor, the drain electrode of the second transistor, the grid electrode of the third transistor and the grid electrode of the pull-down tube are intersected at a bootstrap point; the drain electrode of the reset tube is connected with an input signal, the grid electrode of the reset tube is controlled by the reset signal, and the source electrode of the reset tube, the grid electrode of the second transistor, the drain electrode of the pull-down tube and the grid electrode of the fifth transistor are intersected at a level pull-down control node. Therefore, overlapping of grid output signals is avoided, and the layout area can be reduced.
Description
Technical Field
The present disclosure relates to the field of fingerprint identification technologies, and in particular, to a gate driving circuit and a region scanning method.
Background
The Amorphous Silicon Gate Driver (ASG) technology is a technology in which an a-Silicon Thin Film Transistor (a-Silicon Thin Film Transistor) is used to form a shift register circuit and output a high-voltage or low-voltage Gate signal to drive or turn off a Thin Film Transistor (TFT). The shift register circuit comprises N +1 shift register units (SR for short), wherein each SR is an ASG unit, and N is a positive integer. Because each ASG circuit can be formed by the A-SiTFT in the display panel and the cost of the A-SiTFT is low, the ASG can be used for fingerprint identification to replace a gate IC as a driving circuit, thereby saving the area.
At present, a common ASG circuit is shown in fig. 1, but as the threshold of the TFT transistor changes and drifts with the change of temperature and time, the bootstrap point Q and the output signal Gn in all ASG modules need to be reset and pulled down before each power-on drive, and then used, and the layout area is increased due to the two reset transistors; and the gate output signals of the ASG are overlapped and mutually influenced due to the existing clock signal timing. Fig. 2 adopts a 9T2C structure, but in this structure, the reset operation cannot reset the Q point in the initial state, and belongs to a floating state, which may have an impact on the P pull-up process after the excitation signal is subsequently applied.
Disclosure of Invention
An object of the present application is to provide a gate driving circuit and a region scanning method, which solve the problems in the prior art that gate output signals are overlapped, the area of a domain is large due to an existing reset mode, and an internal node is in a suspended state in a reset state, which may have an impact on a bootstrap point pull-up process after a subsequent excitation signal is given.
According to an aspect of the present application, there is provided a gate driving circuit including N +1 stages of shift register units, where N is a positive integer;
each shift register unit comprises a primary transistor, a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a reset tube and a pull-down tube;
the grid of the primary transistor is used for receiving a driving signal;
the grid electrode of the first transistor is used for receiving an output signal fed back by the next-stage shift register unit so as to control a control signal of the grid electrode;
the source electrode of the primary transistor, the drain electrode of the first transistor, the drain electrode of the second transistor, the grid electrode of the third transistor and the grid electrode of the pull-down tube are intersected at a bootstrap point;
the source electrode of the third transistor, the drain electrode of the fourth transistor and the drain electrode of the fifth transistor are connected with the output signal of the shift register;
the drain electrode of the reset tube is used for receiving an input signal, the grid electrode of the reset tube is controlled by the reset signal, and the source electrode of the reset tube, the grid electrode of the second transistor, the drain electrode of the pull-down tube and the grid electrode of the fifth transistor are intersected at a level pull-down control node;
the drain of the first transistor is connected with a first level signal, the source of the first transistor is connected with a second level signal, and the potentials of the first level signal and the second level signal are opposite.
Furthermore, each shift register unit comprises a first capacitor and a second capacitor, two electrode plates of the first capacitor are respectively connected with the bootstrap point and the output signal of the shift register, and two electrode plates of the second capacitor are respectively connected with the first clock signal and the level pull-down control node.
Further, the source of the second transistor is connected to a low level signal, the source of the fourth transistor and the source of the fifth transistor are connected to a low level signal, and the source of the pull-down tube is connected to a low level signal.
Furthermore, the first clock signal and the second clock signal connected to the odd-numbered shift register units are opposite to and do not overlap with the first clock signal and the second clock signal connected to the even-numbered shift register units.
Further, the output signal of the shift register unit of the previous stage is used as the excitation signal of the shift register unit of the next stage, and the output signal of the shift register unit of the next stage is used as the control signal of the gate of the first transistor in the shift register unit of the previous stage.
Furthermore, the drain electrode of the reset tube is connected with an input signal, and the input signal is pulled high at the first moment of the clock signal and pulled low at the second moment.
According to yet another aspect of the present application, there is provided an area scanning method using the gate driving circuit described above, the method including:
selecting a designated area block from a plurality of blocks composed of gate driving circuits based on the detected fingerprint trigger information, wherein each block in the designated area block includes N +1 stages of shift register units;
the excitation signals of the shift register cells in the designated area are set to a high level, and the excitation signals of the shift register cells in the remaining blocks remain to receive a low level.
Compared with the prior art, the grid region circuit comprises an N + 1-stage shift register unit; each shift register unit comprises a primary transistor, a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a reset tube and a pull-down tube point; the grid of the primary transistor is used for receiving a driving signal; the grid electrode of the first transistor is used for receiving an output signal fed back by the next-stage shift register unit so as to control a grid electrode control signal; the source electrode of the primary transistor, the drain electrode of the first transistor, the drain electrode of the second transistor, the grid electrode of the third transistor and the grid electrode of the pull-down tube are intersected at a bootstrap point; the source electrode of the third transistor, the drain electrode of the fourth transistor and the drain electrode of the fifth transistor are connected with the output signal of the shift register; the drain electrode of the reset tube is connected with an input signal, the grid electrode of the reset tube is controlled by the reset signal, and the source electrode of the reset tube, the grid electrode of the second transistor, the drain electrode of the pull-down tube and the grid electrode of the fifth transistor are all intersected at a level pull-down control node; the drain of the third transistor receives a first clock signal, the gate of the fourth transistor receives a second clock signal, and the first clock signal and the second clock signal are opposite and are not overlapped. Therefore, overlapping of grid output signals is avoided, the area of the layout can be reduced, a new reset mode is provided by using one reset tube, the problem that the level pull-down control node is in a suspended state when initial state reset is carried out, and the opposite impact on the pull-up process of the bootstrap point possibly after excitation signals are given subsequently is avoided.
Further, the gate driving circuit of the present application may be applied to area scanning, and select a designated area block from a plurality of blocks composed of gate driving circuits based on detected fingerprint trigger information, wherein each of the designated area blocks includes N +1 stages of shift registers; the excitation signals of the shift register cells in the designated area are set to a high level, and the excitation signals of the shift register cells in the remaining blocks remain to receive a low level. Therefore, area scanning is realized, and power consumption and time are saved.
Drawings
Other features, objects and advantages of the present application will become more apparent upon reading of the following detailed description of non-limiting embodiments thereof, made with reference to the accompanying drawings in which:
FIG. 1 shows a schematic diagram of an ASG structure in the prior art;
FIG. 2 shows a schematic diagram of an ASG structure of a 9T2C structure employed in the prior art;
FIG. 3 illustrates a schematic diagram of a gate driver circuit structure provided in accordance with an aspect of the present application;
FIG. 4 is a block diagram of a gate driving circuit including a multi-stage shift register according to an embodiment of the present disclosure;
FIG. 5 shows an improved ASG timing diagram in an embodiment of the present application;
fig. 6 shows a schematic diagram of an area scan implemented using an ASG.
The same or similar reference numbers in the drawings identify the same or similar elements.
Detailed Description
The present application is described in further detail below with reference to the attached figures.
Fig. 3 is a schematic diagram illustrating a structure of a gate driving circuit provided in accordance with an aspect of the present application, the gate driving circuit including N +1 shift register units, where N is a positive integer; each shift register unit comprises a primary transistor T0, a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a reset tube T6 and a pull-down tube T7; the gate of the primary transistor T0 is for receiving a stimulus signal; the gate of the first transistor T1 is used for receiving the output signal fed back by the next stage of shift register unit to control the control signal of the gate; the source of the primary transistor T0 meets the drain of the first transistor T1, the drain of the second transistor T2, the gate of the third transistor T3 and the gate of the pull-down transistor T7 at a bootstrap point; the source of the third transistor T3, the drain of the fourth transistor T4 and the drain of the fifth transistor T5 are connected to the output signal of the shift register; the drain of the third transistor T3 receives a first clock signal (CKB), the gate of the fourth transistor T4 receives a second clock signal (CK), and the first clock signal CKB and the second clock signal CK are opposite and do not overlap; the drain electrode of the reset tube is used for receiving an input signal, and the grid electrode of the reset tube is controlled by the reset signal. The initial transistors, the first to fifth transistors, the reset tube and the pull-down tube are all TFTs, and the TFTs use Nmos tube mode, and the high-level end is the drain end and the low-level end is the source end of the TFT. Each shift register ASG cell includes T0, T1 … … T5, and T6, T7, and the source of the primary transistor T0 meets the drain of the second transistor T2, the gate of the third transistor T3, and the gate of the pull-down transistor T7 at a bootstrap point PU. The source of the reset transistor T6, the gate of the second transistor T2, the drain of the pull-down transistor T7, and the gate of the fifth transistor T5 meet at a level pull-down control node PD. The drain of the primary transistor T0 is used for receiving the first level signal DIR1, the source of the first transistor T1 is used for receiving the second level signal DIR2, and the first level signal DIR1 and the second level signal DIR2 are opposite in potential. The first level signal DIR1 can be a low level signal or a high level signal, DIR2 is a high level signal when DIR1 is a low level signal, and DIR2 is a low level signal when DIR1 is a high level signal. Therefore, overlapping of grid output signals is avoided, the area of the layout can be reduced, a new reset mode is provided by using one reset tube, the problem that the level pull-down control node is in a suspended state when initial state reset is carried out, and the opposite impact on the pull-up process of the bootstrap point possibly after excitation signals are given subsequently is avoided.
With continued reference to fig. 3, each shift register unit includes a first capacitor C1 and a second capacitor C2, two plates of the first capacitor C1 are respectively connected to the bootstrap point PU and the output signal Gn of the shift register, and two plates of the second capacitor C2 are respectively connected to the first clock signal CKB and the level pull-down control node PD. Herein, the capacitor C1 has two plates respectively connected to PU and Gn for bootstrap, and the capacitor C2 has two plates respectively connected to CKB and PD for a capacitive coupling to pull up PD when CKB is pulled up.
In one embodiment of the present application, for ASG cells, DIR1 is connected to the drain of T0, the gate is connected to the stimulus signal STP, and the source is PU; the drain of the T1 is PU, the next stage output signal Gn +1 is fed back to be used as the gate control signal of the T1, and the source is connected with DIR 2; t2 drain PU, gate PD, source low level (VGL); the drain of T3 is CKB, the grid is controlled by PU, the source is output signal Gn; the drain electrode of T4 is Gn, the grid electrode is controlled by clock signal CK, the source electrode is VGL; the drain electrode of T5 is Gn, the grid electrode is controlled by PD, and the source electrode is VGL; t6 is an initial state reset tube, the drain is input signal VGX, the grid is controlled by reset signal (reset), the source is PD; t7 is the pull-down tube, the drain is PD, the gate is PU, and the source is VGL.
In an embodiment of the present application, the first clock signal and the second clock signal connected to the odd-numbered stage shift register units are opposite to and do not overlap with the first clock signal and the second clock signal connected to the even-numbered stage shift register units. As shown in fig. 4, the output signal of the shift register unit of the previous stage is used as the excitation signal of the shift register unit of the next stage, and the output signal of the shift register unit of the next stage is used as the control signal of the gate of the first transistor in the shift register unit of the previous stage. The STP port of the first-stage ASG inputs the excitation signal STP of the whole system, CK inputs a system clock CK, CKB outputs a system clock CKB, Gn outputs a first-stage output signal G1, and Gn +1 is connected with a second-stage output signal G2; the STP port of the second-stage ASG inputs a first-stage output signal for excitation, CK inputs a system clock CKB, the CKB outputs the system clock CK, Gn outputs a first-stage output signal G2, and Gn +1 is connected with a third-stage output signal G3; in the same way, the clock signals CK and CKB of the odd-numbered stage and the even-numbered stage are opposite, the CK port of the odd-numbered stage is connected with the CK, and the CKB port is connected with the CKB; the even-level CK port is connected with the CKB, and the CKB port is connected with the CK. In addition, all the stage RESET ports input a RESET signal, and the VGX port inputs a VGX signal. The number of the total effective ASG units is N, the last additional ASG unit is dummy, the STP inputs a Gn signal, Gn +1 inputs a system STP signal, and the output of Gn +1 is invalid output. Normally, DIR1 is connected to high VGH, DIR2 is connected to low VGL; if the grid output signal is required to be reversely generated, DIR1 can be connected with a low level VGL, DIR2 is connected with a high level VGH, and since STP is connected with the grids of T0 of the first stage and T1 of the last dummy stage, the reverse output process from the dummy stage to the first stage similar to the output of the shift register from the first stage to the dummy stage can be completed.
In an embodiment of the present application, the drain of the reset transistor T6 is connected to an input signal, and the input signal is pulled high at a first time of the clock signal and pulled low at a second time. The source of the second transistor T2 is connected to a low signal, the source of the fourth transistor T4 and the source of the fifth transistor T5 are connected to a low signal, and the source of the pull-down transistor T7 is connected to a low signal. As shown in the improved ASG timing diagram of fig. 5, Reset is pulled high in the initial state, T6 is turned on, and the VGX level is transmitted to the PD point; at the time T1, the VGX is pulled high, the PD is also pulled high at the time, the PD level is pulled high to lead T2 and T5 to be conducted, PU and Gn are connected with the VGL, and resetting of the PU and Gn is completed; VGX is pulled down at time t2, Reset is kept in a pulled-up state, PD is pulled down at the time, Reset is pulled down at time t3, and the whole Reset process is completed. At the time of T4, a high-level STP is input for excitation, the PU is pulled high, the T3 tube is conducted, the grid of the T7 is set to be high, the PD is pulled down to VGL, and the high level of the PU is kept, so that the PD can not pull down the T2 and the T5, and the PU and the Gn cannot be influenced; the STP pulse ends at time T5, but the C1 capacitor is able to hold the PU high, causing T3 to continue conducting; at time T6, CKB is pulled high, and Gn is pulled high, because of the capacitance characteristic, C1 raises PU (bootstrap), PU is pulled high again, T3 is applied with higher gate voltage, and Gn can be pulled high rapidly. During time T6-T7, G1 is output to the second stage STP, the PU of the second stage ASG is pulled up by the second stage T0, and the high level potential can be maintained by C1 after G1 is pulled down. At time t7, CKB is pulled low, and Gn is at low level; using the skew clock, CK is pulled high at time t8, which has three effects: 1) t4 is turned on and G1 is pulled low in the first stage ASG; 2) the simultaneously pulled-up G2 feeds back to the first stage ASG, pulling the PU low through T1; 3) because the clock signals of the odd-numbered stages and the even-numbered stages are inverted, the drain terminal of the T3 transistor in the second-stage ASG is given with high level, G2 is pulled high, and the effect of shift register controlled by the clock signals is achieved. The pulse widths of the clock signals, t6-t7, t8-t9, t10-t11, can be adjusted but remain the same as the time required by the actual readout circuit. CK is pulled low at time t 9; at time T10, CKB is pulled high again, in the first stage ASG, as CKB is pulled high, PD point level is coupled and raised through a C2 capacitor, T2 and T5 are turned on to pull PU and Gn down to VGL; and then the Gn is always kept at a low level by the overlapped pull-up of CK and CKB. When the Nth stage generates GN signals, the GN signals are transmitted to a dummy stage, namely Gn +1 ASG, the STP end of an excitation signal inputs high level, the PU of the dummy stage is pulled high, and after a high level clock is input to the CKB port, Gn is pulled high and is fed back to the nth stage; however, because there is no way to pull down the PU, the dummy stage output Gn always has an output signal synchronized with the clock signal input from the CKB port, and the feedback to the previous stage Gn helps the stage Gn keep a pull-down state after being pulled down.
The staggered clock is arranged to ensure that the staggered grid outputs signals, and no overlapping is carried out to ensure that the grids are sequentially opened without mutual influence. In addition, only one transistor is used in the initial state reset process, the layout area is reduced, meanwhile, the PD can be pulled down at the initial state moment instead of in a suspended state, and the fact that the bootstrap point is pulled up after an excitation signal is given subsequently is guaranteed to be free of impact influence.
According to yet another aspect of the present application, there is provided an area scanning method using the gate driving circuit described above, the method including: step S11, selecting a designated area block from a plurality of blocks composed of gate driving circuits based on the detected fingerprint trigger information, wherein each of the designated area blocks includes N +1 stages of shift registers; in step S12, the activation signals of the shift register cells in the designated area are set to high level, and the activation signals of the remaining shift register cells remain to receive low level. Here, as shown in fig. 6, the gate driving circuit described above may be applied to area scanning, where a fingerprint is detected to select an ASG unit in a specified range, for example, a region from a 3 rd block to a 6 th block, where each block includes N +1 stage shift registers, an STP signal is given to the ASG unit in the specified region where the fingerprint is detected, the STP signal is pulled high after reset to output a gate driving level, the ASG units in other blocks are kept silent, and the STP signal is not triggered when the STP signal is received at a low level. Therefore, area scanning is realized, and power consumption and time are saved. In a preferred embodiment of the present application, for example, the detection area is first divided into a number of ASG blocks with sequence numbers 1,2,3 … … 100, and when detecting that the fingerprint is detected in the range of sequence numbers 3,4, and 5, the block corresponding to sequence number 3,4, and 5 is an ASG unit in the designated range, and the ASG unit corresponding to sequence number 3,4, and 5 is given high-level excitation, and the ASG units in the blocks corresponding to other sequence numbers are kept silent. It should be noted that the ASG units in the designated range selected in the above embodiments are only examples, and may be ASG units corresponding to sequence numbers 2,3, and 4 or ASG units corresponding to other sequence numbers.
It will be apparent to those skilled in the art that various changes and modifications may be made in the present application without departing from the spirit and scope of the application. Thus, if such modifications and variations of the present application fall within the scope of the claims of the present application and their equivalents, the present application is intended to include such modifications and variations as well.
It will be evident to those skilled in the art that the present application is not limited to the details of the foregoing illustrative embodiments, and that the present application may be embodied in other specific forms without departing from the spirit or essential attributes thereof. The present embodiments are therefore to be considered in all respects as illustrative and not restrictive, the scope of the application being indicated by the appended claims rather than by the foregoing description, and all changes which come within the meaning and range of equivalency of the claims are therefore intended to be embraced therein. Any reference sign in a claim should not be construed as limiting the claim concerned. Furthermore, it is obvious that the word "comprising" does not exclude other elements or steps, and the singular does not exclude the plural.
Claims (7)
1. The grid driving circuit is characterized by comprising an N + 1-stage shift register unit, wherein N is a positive integer;
each shift register unit comprises a primary transistor, a first transistor, a second transistor, a third transistor, a reset tube and a pull-down tube;
the grid of the primary transistor is used for receiving a driving signal;
the grid electrode of the first transistor is used for receiving an output signal fed back by the next-stage shift register unit so as to control a grid electrode control signal;
the source electrode of the primary transistor, the drain electrode of the first transistor, the drain electrode of the second transistor, the grid electrode of the third transistor and the grid electrode of the pull-down tube are intersected at a bootstrap point;
the drain electrode of the reset tube is connected with an input signal, the grid electrode of the reset tube is controlled by the reset signal, and the source electrode of the reset tube, the grid electrode of the second transistor, the drain electrode of the pull-down tube and the grid electrode of the fifth transistor are intersected at a level pull-down control node;
the drain electrode of the reset tube is connected with an input signal, and the input signal is pulled high at the first moment of the clock signal and pulled low at the second moment;
the source electrode of the third transistor, the drain electrode of the fourth transistor and the drain electrode of the fifth transistor are connected with the output signal of the shift register;
the drain of the third transistor receives a first clock signal, the gate of the fourth transistor receives a second clock signal, and the first clock signal and the second clock signal are opposite and are not overlapped.
2. A gate driving circuit as claimed in claim 1, wherein the drain of the primary transistor is connected to a first level signal, and the source of the first transistor is connected to a second level signal, the first level signal and the second level signal having opposite potentials.
3. The gate driving circuit of claim 1, wherein each shift register unit comprises a first capacitor and a second capacitor, two plates of the first capacitor are respectively connected to the bootstrap point and the output signal of the shift register, and two plates of the second capacitor are respectively connected to the first clock signal and the level down control node.
4. The gate driving circuit according to claim 1, wherein a source of the second transistor is connected to a low level signal, a source of the fourth transistor and a source of the fifth transistor are connected to a low level signal, and a source of the pull-down tube is connected to a low level signal.
5. The gate driving circuit of claim 1, wherein the first clock signal and the second clock signal connected to the odd-numbered stage of the shift register units are opposite to and non-overlapping with the first clock signal and the second clock signal connected to the even-numbered stage of the shift register units.
6. The gate driver circuit according to claim 1, wherein the output signal of the shift register unit of the previous stage is used as a driving signal of the shift register unit of the next stage, and the output signal of the shift register unit of the next stage is used as a control signal of the gate of the first transistor in the shift register unit of the previous stage.
7. An area scanning method using the gate driver circuit according to any one of claims 1 to 6, the method comprising:
selecting a designated area block from a plurality of blocks composed of gate driving circuits based on the detected fingerprint trigger information, wherein each block in the designated area block includes N +1 stages of shift registers;
connecting an input signal through a drain electrode of a reset tube, wherein the input signal is pulled high at the first moment of a clock signal and pulled low at the second moment so as to reset an excitation signal of the shift register unit in the designated area;
and setting the excitation signals of the shift register units in the designated area after reset to be at a high level, and keeping the excitation signals of the rest shift register units to receive a low level.
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| CN102930812B (en) * | 2012-10-09 | 2015-08-19 | 北京京东方光电科技有限公司 | Shift register, grid line integrated drive electronics, array base palte and display |
| CN106683617B (en) * | 2017-03-22 | 2021-01-01 | 京东方科技集团股份有限公司 | Shifting register unit, array substrate and display device |
| JP6845821B2 (en) * | 2018-03-02 | 2021-03-24 | 株式会社半導体エネルギー研究所 | Display device |
| CN108428468B (en) * | 2018-03-15 | 2021-01-29 | 京东方科技集团股份有限公司 | Shift register and driving method thereof, grid driving circuit and display device |
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| CN103268757A (en) * | 2012-06-29 | 2013-08-28 | 上海天马微电子有限公司 | Grid driving module of liquid crystal display panel and liquid crystal display panel |
| CN103985363A (en) * | 2013-12-05 | 2014-08-13 | 上海中航光电子有限公司 | Grid driving circuit, TTF array substrate, display panel and display apparatus |
| CN103943053A (en) * | 2013-12-30 | 2014-07-23 | 上海中航光电子有限公司 | Grid electrode drive circuit and shifting register thereof |
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