CN109678102A - MEMS structure and its manufacturing method - Google Patents
MEMS structure and its manufacturing method Download PDFInfo
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- CN109678102A CN109678102A CN201811625593.5A CN201811625593A CN109678102A CN 109678102 A CN109678102 A CN 109678102A CN 201811625593 A CN201811625593 A CN 201811625593A CN 109678102 A CN109678102 A CN 109678102A
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- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical group [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 5
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- 239000000463 material Substances 0.000 claims description 4
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- 239000012528 membrane Substances 0.000 claims description 2
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- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 6
- 230000015572 biosynthetic process Effects 0.000 description 6
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- WGTYBPLFGIVFAS-UHFFFAOYSA-M tetramethylammonium hydroxide Chemical compound [OH-].C[N+](C)(C)C WGTYBPLFGIVFAS-UHFFFAOYSA-M 0.000 description 4
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- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
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Classifications
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B81—MICROSTRUCTURAL TECHNOLOGY
- B81B—MICROSTRUCTURAL DEVICES OR SYSTEMS, e.g. MICROMECHANICAL DEVICES
- B81B7/00—Microstructural systems; Auxiliary parts of microstructural devices or systems
- B81B7/02—Microstructural systems; Auxiliary parts of microstructural devices or systems containing distinct electrical or optical devices of particular relevance for their function, e.g. microelectro-mechanical systems [MEMS]
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B81—MICROSTRUCTURAL TECHNOLOGY
- B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
- B81C1/00—Manufacture or treatment of devices or systems in or on a substrate
- B81C1/00015—Manufacture or treatment of devices or systems in or on a substrate for manufacturing microsystems
- B81C1/00134—Manufacture or treatment of devices or systems in or on a substrate for manufacturing microsystems comprising flexible or deformable structures
- B81C1/00158—Diaphragms, membranes
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B81—MICROSTRUCTURAL TECHNOLOGY
- B81B—MICROSTRUCTURAL DEVICES OR SYSTEMS, e.g. MICROMECHANICAL DEVICES
- B81B2201/00—Specific applications of microelectromechanical systems
- B81B2201/02—Sensors
- B81B2201/0264—Pressure sensors
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- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Pressure Sensors (AREA)
Abstract
This application discloses MEMS structure and its manufacturing methods.The described method includes: forming cavity in the semiconductor substrate；Sensitive diaphragm is formed on the cavity；And multiple sensitive resistances are formed in the sensitive diaphragm；Wherein, the sensitive diaphragm includes island portion and the interconnecting piece around the island portion, and the thickness in the island portion is greater than the thickness of the interconnecting piece, and the multiple sensitive resistance is located at the interconnecting piece.This method uses the sensitive diaphragm of uneven gauge, so that pressure concentrates on interconnecting piece to improve sensitivity.
Description
Technical field
The present invention relates to microelectronic fields, more particularly, to MEMS structure and its manufacturing method.
Background technique
MEMS device is the microelectron-mechanical made of micro fabrication to grow up in microelectric technique basis
Device has been widely used as sensor and actuator.For example, MEMS device can be pressure sensor, accelerometer, gyro
Instrument, silicon capacitor microphone.
Pressure sensor is for example including the sensor chip and circuit chip fitted together.Wherein, in sensor chip
Middle formation MEMS structure, forms detection circuit in circuit chip.Then by die bonding technique, sensor chip and electricity
Road chip bonding together, to form MEMS component.
According to the difference of detecting element and method, pressure sensor can there are many different types, including pressure resistance type,
Condenser type, resonant mode etc..Piezoresistive pressure sensor comes across the sixties in last century.With other kinds of pressure sensor phase
It is more with the obvious advantage than, piezoresistive pressure sensor, such as fast, high reliablity, low in energy consumption, micro- is pored over high sensitivity, response
The series of advantages such as type.With advances in technology, it is reached its maturity using the technology of the piezoresistive pressure sensor of MEMS structure,
Realized the mass of production and cost effective.
Existing piezoresistive pressure sensor mainly utilizes bulk silicon technology micromachined to form, including is located on cavity
Sensitive diaphragm, the varistor and detection circuit on sensitive diaphragm of side.The shape of sensitive diaphragm is e.g. rectangular,
Or it is round, detection circuit is for example by the inclusion of the Wheatstone bridge detection external pressure variation of varistor.
The Specifeca tion speeification of pressure sensor is sensitivity and the linearity.In traditional pressure sensor, sensitive membrane
Piece is the fixed smooth diaphragm in periphery.Its sensitivity is improved using the method for thinned sensitive diaphragm thickness.However, quick being thinned
When feeling diaphragm, the surface stress of sensitive diaphragm will lead to non-linear serious increase.Therefore, the sensitive diaphragm of planar structure is mainly used
In the pressure sensor of middle high range, it is not suitable for manufacturing the pressure sensor of small-range.As a result, the size of pressure sensor is difficult
To reduce.
Therefore, it is desirable to the MEMS structure for pressure sensor is further improved, so as to mention while miniaturization
The highly sensitive and linearity.
Summary of the invention
In view of this, the object of the present invention is to provide MEMS structure and its manufacturing methods, wherein using uneven gauge
Pressure is concentrated on interconnecting piece to improve sensitivity by sensitive diaphragm.
According to an aspect of the present invention, a kind of method manufacturing MEMS structure is provided, comprising:
Cavity is formed in the semiconductor substrate；
Sensitive diaphragm is formed on the cavity；And
Multiple sensitive resistances are formed in the sensitive diaphragm；
Wherein, the sensitive diaphragm includes island portion and the interconnecting piece around the island portion, the thickness in the island portion
Degree is greater than the thickness of the interconnecting piece, and the multiple sensitive resistance is located at the interconnecting piece.
Preferably, before the step of forming cavity, further includes:
Well region is formed using first time ion implanting and annealing, the well region surrounds the firstth area of the semiconductor substrate
Domain.
Preferably, the step of formation cavity includes:
The semiconductor material of the first area is transformed by porous layer using electrochemistry corruption；And
The porous layer is removed relative to the semiconductor substrate using etching.
Preferably, before the step of forming cavity, further includes:
The third doped region of lattice is formed using second of ion implanting and annealing；And
The 5th doped region of lattice is formed using third time ion implanting and annealing,
Wherein, the third doped region and the 5th doped region are located in the first area of the semiconductor substrate, and
And the 5th doped region surrounds the third doped region.
Preferably, in the step of forming cavity, the third doped region and the 5th doped region form lattice
Frame, the mesh of the lattice reaches the cavity.
Preferably, the step of forming the sensitive diaphragm includes: on the third doped region and the 5th doped region
Epitaxial layer is formed, wherein epitaxial layer vertical-growth on the surface of the third doped region and the 5th doped region, with
And to fill the mesh, the epitaxial layer is mixed with the third doped region shape and the described 5th for cross growth in the mesh
Miscellaneous area is formed together sensitive diaphragm, and closes the cavity.
Preferably, the step of forming multiple sensitive resistances includes: to be infused in shape in the epitaxial layer using the 4th secondary ion
At the multiple sensitive resistance.
Preferably, after the step of forming multiple sensitive resistances, further includes:
Interlayer dielectric layer is formed on said epitaxial layer there；And
Form the interconnection that the multiple sensitive resistance is reached across the interlayer dielectric layer.
Preferably, the multiple sensitive resistance is uniformly distributed in the interconnecting piece of the sensitive diaphragm.
Preferably, the multiple sensitive resistance is interconnected into Wheatstone bridge.
Preferably, the semiconductor substrate and the sensitive resistance are the first doping type, and the well region, the third are mixed
Miscellaneous area and the 5th doped region are the second doping type, and first doping type is opposite with second doping type.
Preferably, first doping type is p-type, and second doping type is N-type.
Preferably, the junction depth of the well region is greater than the junction depth of the third doped region, and the junction depth of the third doped region is big
In the junction depth of the 5th doped region.
Preferably, the semiconductor substrate is silicon substrate.
Preferably, the island portion and the interconnecting piece are multiple, and the island portion and the interconnecting piece interval are arranged.
According to another aspect of the present invention, a kind of MEMS structure is also provided, comprising:
Cavity in semiconductor substrate；
Sensitive diaphragm on the cavity；And
Multiple sensitive resistances in the sensitive diaphragm；
Wherein, the sensitive diaphragm includes island portion and the interconnecting piece around the island portion, the thickness in the island portion
Degree is greater than the thickness of the interconnecting piece, and the multiple sensitive resistance is located at the interconnecting piece.
It preferably, further include the well region for surrounding the cavity.
Preferably, the sensitive diaphragm includes:
Form the third doped region of the island portion frame of the sensitive diaphragm；
Form the 5th doped region of the interconnecting piece frame of the sensitive diaphragm；And
Epitaxial layer on the third doped region and the 5th doped region,
Wherein, the third doped region and the 5th doped region form lattice, the epitaxial layer covering described the
Three doped regions and the 5th doped region, and the mesh of the lattice is filled to close the cavity.
Preferably, the 5th doped region surrounds the third doped region.
Preferably, the multiple sensitive resistance is the doped region in the epitaxial layer.
Preferably, further includes:
Interlayer dielectric layer on the epitaxial layer；And
The interconnection of the multiple sensitive resistance is reached across the interlayer dielectric layer.
Preferably, the multiple sensitive resistance is uniformly distributed in the interconnecting piece of the sensitive diaphragm.
Preferably, the multiple sensitive resistance is interconnected into Wheatstone bridge.
Preferably, the semiconductor substrate and the sensitive resistance are the first doping type, and the well region, the third are mixed
Miscellaneous area and the 5th doped region are the second doping type, and first doping type is opposite with second doping type.
Preferably, first doping type is p-type, and second doping type is N-type.
Preferably, the junction depth of the well region is greater than the junction depth of the third doped region, and the junction depth of the third doped region is big
In the junction depth of the 5th doped region.
Preferably, the island portion and the interconnecting piece are multiple, and the island portion and the interconnecting piece interval are arranged.
MEMS structure and its manufacturing method according to an embodiment of the present invention, wherein uneven gauge is formed above cavity
Sensitive diaphragm pressure is concentrated on into the lesser interconnecting piece of thickness, so that MEMS when sensitive diaphragm is under pressure and acts on
The sensitivity of structure is improved, but also overvoltage protection and nonlinear compensation may be implemented.Wherein, due to the thickness in island portion
Greater than the thickness of interconnecting piece, it is equivalent to the effect of baffle, when sensitive diaphragm is by biggish pressure, the deformation that can bear
Measure larger, sensitive diaphragm does not allow easy fracture at this time, and then has bigger sensitivity.
In a preferred embodiment, using third doped region and the 5th doped region be respectively formed sensitive diaphragm island portion and
Interconnecting piece frame, the frame are lattice, and utilize the mesh of the epitaxial growth characteristic of epitaxial layer filling lattice.It should
Method controls the transfer of the thickness control of island portion and interconnecting piece for the junction depth of two doped regions, so as to avoid multiple steps
Deep trouth etching, not only simplify technique, but also improve thickness control precision so that the precision of MEMS structure and yield mention
It is high.The shortcomings that this method avoid bonding technologies, realizes on single wafer, and manufacturing method is simple, at low cost, is easy to and CMOS
Circuit integration.
Detailed description of the invention
By referring to the drawings to the description of the embodiment of the present invention, above-mentioned and other purposes of the invention, feature and
Advantage will be apparent from, in the accompanying drawings:
MEMS structure manufacturing method according to an embodiment of the present invention is shown respectively in the sectional view in each stage in Fig. 1 to 13.
Specific embodiment
Hereinafter reference will be made to the drawings, and the present invention will be described in more detail.In various figures, identical element is using similar attached
Icon is remembered to indicate.For the sake of clarity, the various pieces in attached drawing are not necessarily to scale.Furthermore, it is possible to be not shown certain
Well known part.
Many specific details of the invention, such as structure, material, size, the processing work of device is described hereinafter
Skill and technology, to be more clearly understood that the present invention.But it just as the skilled person will understand, can not press
The present invention is realized according to these specific details.
The present invention can be presented in a variety of manners, some of them example explained below.
MEMS structure manufacturing method according to an embodiment of the present invention is shown respectively in the sectional view in each stage in Fig. 1 to 13.
This method starts from semiconductor substrate 201.The substrate is, for example, the P-type silicon substrate for mixing B, and crystal orientation is, for example,<100>,
Resistivity is, for example, 5-10 ohmcm.
Then, using photolithography method, the resist exposure mask 101 with opening is formed on the surface of semiconductor substrate 201.Through
First time ion implanting is carried out by photoresist exposure mask, the first doped region 102 of N+ type is formed in semiconductor substrate 201, such as Fig. 1
It is shown.
The N type dopant used in first time ion implanting is, for example, phosphonium ion.By controlling the energy of ion implanting,
So that the first doped region 102 extends downward into predetermined depth from the surface of semiconductor substrate 201.First time ion implanting it
Afterwards, such as by being ashed or dissolving removal photoresist exposure mask 101.
Then, high annealing is carried out, so that the dopant in the first doped region 102 diffuses to form the well region 103 of N+ type, such as
Shown in Fig. 2.
The depth of the well region 103 is, for example, 5 to 15 microns.Well region 103 surrounds the first area of semiconductor substrate 201, uses
The shape of cavity will be formed in restriction.It is rinsed after the high temperature anneal for example, by using HF acid to remove semiconductor substrate
The silicon oxide layer on 201 surfaces.
Then, for example, by using chemical vapor deposition process, the first insulating layer is sequentially formed on the surface of semiconductor substrate 201
104 and second insulating layer 105.First insulating layer 104 is, for example, silicon oxide layer, and thickness is received less than 200 nanometers, such as with a thickness of 20
Rice.Second insulating layer 105 is, for example, silicon nitride layer, and thickness is about 200 to 500 nanometers.
Via photoresist exposure mask, a part of etching the first insulating layer 104 and second insulating layer 105 of removal, to be formed
Opening 301.Due to the etching selection ratio between different materials, which for example stops on the surface of semiconductor substrate 201.It is etching
Photoresist exposure mask is removed later, as shown in Figure 3.
In this embodiment, the first area that opening 301 is surrounded with well region 103 is generally corresponding to, thus exposure entire first
Region.In alternate embodiments, opening 301 is located above the first area that well region 103 surrounds, to only expose first area
A part.In subsequent electrochemical corrosion step, patterned first insulating layer 104 and second insulating layer 105 are together
As hard exposure mask.
Then, using photolithography method, the resist exposure mask 106 with opening is formed on the surface of semiconductor substrate 201.Through
Second of ion implanting is carried out by photoresist exposure mask, the second doped region 107 of N-type is formed in semiconductor substrate 201, such as Fig. 4
It is shown.
The N type dopant used in second of ion implanting is, for example, phosphonium ion.By controlling the energy of ion implanting,
So that the second doped region 107 extends downward into predetermined depth from the surface of semiconductor substrate 201.Second ion implanting it
Afterwards, such as by being ashed or dissolving removal photoresist exposure mask 106.
Then, high annealing is carried out, so that the dopant in the second doped region 107 diffuses to form the third doped region of N-type
108, as shown in Figure 5.
The depth of the third doped region 108 be less than well region 103 depth, for example, 2 to 10 microns.Third doped region 108
Waffle-like pattern is formed in the first area of semiconductor substrate 201, for forming the frame in island portion in final device.The
The junction depth of three doped regions 108 will determine the thickness in island portion.
Then, using photolithography method, the resist exposure mask 109 with opening is formed on the surface of semiconductor substrate 201.Through
Third time ion implanting is carried out by photoresist exposure mask, the 4th doped region 110 of N-type is formed in semiconductor substrate 201, such as Fig. 6
It is shown.
The N type dopant used in third time ion implanting is, for example, phosphonium ion.By controlling the energy of ion implanting,
So that the 4th doped region 110 extends downward into predetermined depth from the surface of semiconductor substrate 201.Third time ion implanting it
Afterwards, such as by being ashed or dissolving removal photoresist exposure mask 109.
Then, high annealing is carried out, so that the dopant in the 4th doped region 110 diffuses to form the 5th doped region of N-type
111, as shown in Figure 7.
The junction depth of 5th doped region 111 be less than third doped region 108 junction depth, for example, 1 to 5 micron.5th doping
Area 111 surrounds third doped region 108, waffle-like pattern is formed in the first area of semiconductor substrate 201, in final device
The frame of interconnecting piece is formed in part.The junction depth of 5th doped region 111 will determine the thickness of interconnecting piece.
Then, in the first area of semiconductor substrate 201, porous layer 112 is formed using electrochemical corrosion, such as Fig. 8 institute
Show.
In this step, with the first insulating layer 104 and second insulating layer 105 together as hard exposure mask.By entire semiconductor
Structure immerses in acid solution, such as ethyl alcohol/hydrofluoric acid/water mixed liquor or acetone/hydrofluoric acid/water mixed liquor.For example,
The ethyl alcohol of the acid solution: the volume ratio of hydrofluoric acid (50%) is 1:1.
Generate electrochemical corrosion in the first area of semiconductor substrate 201, thus formed extended downwardly from surface it is more
Aperture layer 112.Electrochemical reaction does not occur for the well region 103 of N+ type, the third doped region 108 of N-type and the 5th doped region 111, still
Keep mono-crystalline structures.Then entire semiconductor structure is taken out from corrosive liquid, is cleaned, to complete electrochemical corrosion step
Suddenly.
Then, porous layer 112 is removed to form cavity 302, as shown in Figure 9.
In this step, porous silicon layer 112 is removed using wet etching.For example, using alkaline corrosion liquid (such as SC1),
Tetramethylammonium hydroxide (TMAH) corrosive liquid is as etchant.Due to the selectivity of etchant, relative to semiconductor substrate 201,
Well region 103, third doped region 108 and the 5th doped region 111 remove porous silicon layer 112.
After the etching, third doped region 108 is waffle-like pattern, and as the frame in island portion, the 5th doped region 111 is
Waffle-like pattern, the frame as interconnecting piece.Cavity 302 is located at the lower section of third doped region 108 and the 5th doped region 111, and
And it is connected to via the mesh of waffle-like pattern with outside.The depth of cavity 302 corresponds roughly to the junction depth of well region 103, for example, 3
To 10 microns.
Then, the epitaxial layer 113 of N-type, 113 closed cavity 302 of epitaxial layer, such as Figure 10 are formed in the top of cavity 302
It is shown.
For example, low-pressure chemical vapor phase deposition (LPVCD) or plasma enhanced chemical vapor deposition can be used
The methods of (PECVD), with third doped region 108 and the 5th doped region 111 for frame epitaxial growth monocrystalline silicon, to form N-type
Epitaxial layer 113.The gas source used in epitaxial growth is, for example, SiH2Cl2, temperature is, for example, 900 to 1200 degrees Celsius.Pass through
The composition and concentration and deposition time of control vaporous precursors, can control the thickness of epitaxial layer 113.In this embodiment,
The thickness of epitaxial layer 113 is, for example, 6 microns to 10 microns, and preferably 8 microns.
Due to the characteristic of epitaxial growth, the epitaxial layer 113 is not only in semiconductor substrate 201, well region 103, third doped region
108 and the 5th doped region 111 surface on vertical-growth, and the net formed in third doped region 108 and the 5th doped region 111
Mesh inner wall cross growth in trellis pattern, so that mesh is filled up, thus closed cavity 302.
Epitaxial layer 113 and third doped region 108 and the 5th doped region 111 are formed together hanging quick above cavity 302
Feel diaphragm.The island portion 202A of sensitive diaphragm is formed in the corresponding position of third doped region 108, in the phase of the 5th doped region 111
Answer the interconnecting piece 202B of position sensing diaphragm, interconnecting piece 202B that island portion 202A is connected to well region 103.Island portion 202A's
Thickness is greater than the thickness of interconnecting piece 202B, corresponds respectively to the junction depth of third doped region 108 and the 5th doped region 111.Wherein, by
Thickness in island portion is greater than the thickness of interconnecting piece, is equivalent to the effect of baffle, when sensitive diaphragm is by biggish pressure,
The deformation quantity that it can bear is larger, and sensitive diaphragm does not allow easy fracture at this time, and then has bigger sensitivity.
The technical solution of single island portion 202A and the interconnecting piece 202B around island portion 202A are illustrated only in figure,
Further, multiple island portion 202A and corresponding multiple interconnecting piece 202B can be also formed by the above method, wherein more
A island portion 202A and the interval multiple interconnecting piece 202B are arranged.
Then, using photolithography method, the resist exposure mask with opening is formed on the surface of epitaxial layer 113.Via photoetching
Glue exposure mask carries out the injection of the 4th secondary ion, the sensitive resistance 114 of p-type is formed in epitaxial layer 113, as shown in figure 11.
The P-type dopant used in the injection of the 4th secondary ion is, for example, phosphonium ion.By controlling the energy of ion implanting,
So that sensitive resistance 114 extends downward into predetermined depth from the surface of epitaxial layer 113.For example, the junction depth of sensitive resistance 114 is about
1 micron to 2 microns.Ash after the injection of the 4th secondary ion, such as can be passed through using the inclination angle of 7 to 10 degree in injection
Change or dissolution removes photoresist exposure mask.
Four sensitive resistances 114 are for example formed in the MEMS structure, are symmetrically distributed in the interconnecting piece 202B of sensitive diaphragm
In.
Then, interlayer dielectric layer 115 is formed on the surface of epitaxial layer 113, and is formed and arrived in interlayer dielectric layer 115
The opening 303 of sensitive resistance 114, as shown in figure 12.
In above-mentioned formation interlayer dielectric layer 115 the step of, such as pass through above-mentioned known depositing technics, it is preferable that adopt
With chemical vapor deposition, boron-phosphorosilicate glass (BPSG) is formed on the surface of semiconductor structure or ethyl orthosilicate (TEOS) is used as layer
Between dielectric layer 115.
Resist layer is formed in the step of above-mentioned formation is open, such as on the surface of interlayer dielectric layer 115, using photoetching
Technique forms the pattern comprising opening in resist layer.Using resist layer as exposure mask, removed using the etchant of selectivity
The expose portion of insulating layer.Due to the selectivity of etching, which can stop on the surface of sensitive resistance 114.In etching
Afterwards, resist layer can be removed by dissolving in ashing or solvent.
Then, the interconnection 116 via opening electrical connection sensitive resistance 114 is formed on interlayer dielectric layer 115, such as Figure 13 institute
Show.
Conductor layer, such as aluminium are formed in the step of above-mentioned formation interconnects, such as through sputtering.The conductor layer fills interlayer
Opening in dielectric layer 115, and also cover the surface of interlayer dielectric layer 115.Preferably, chemical machinery can further be used
The surface of (CMP) smooth conductor layer is planarized, and conductor layer is patterned to interconnection 116.
Above-mentioned interconnection 116 is provided to the electrical connection of sensitive resistance 114.In the situation that MEMS sensor is piezoresistive transducer
Under, four sensitive resistances 114 are connected into Wheatstone bridge by above-mentioned interconnection 116.
The MEMS structure 100 that this method is formed is as shown in figure 13.The MEMS structure 100 is included in semiconductor substrate 201
The cavity 302 of formation, the sensitive diaphragm 202 on the cavity 302 and multiple in the sensitive diaphragm 202
Sensitive resistance 114.
In this embodiment, 103 surrounding cavity 302 of well region.Sensitive diaphragm 202 includes island portion 202A and surrounds described
The thickness of the interconnecting piece 202B, the island portion 202A of island portion 202A are greater than the thickness of the interconnecting piece 202B.Further,
Sensitive diaphragm 202 include third doped region 108 formed island portion frame, the 5th doped region 111 formed interconnecting piece frame, with
And the epitaxial layer 113 on third doped region 108 and the 5th doped region 111.Third doped region 108 and the 5th doped region 111
Lattice is formed, epitaxial layer 113 covers third doped region 108 and the 5th doped region 111, and fills the lattice
Mesh is to close the cavity 302.Sensitive resistance 114 is located in epitaxial layer 113, corresponding with the position of interconnecting piece 202B.The
The junction depth of three doped regions 108 is greater than the junction depth of the 5th doped region 111, and the 5th doped region 111 surrounds third doped region 108.
Further, the junction depth of third doped region 108 and the 5th doped region 111 is less than the junction depth of well region 103.
The MEMS structure 100 further includes the interlayer dielectric layer 115 on the epitaxial layer 113 and passes through interlayer dielectric layer
115 reach the interconnection 116 of the multiple sensitive resistance 114.The multiple sensitive resistance 114 is uniformly distributed in the company of sensitive diaphragm
Socket part 202B, via being interconnected and form Wheatstone bridge.
In the MEMS structure, semiconductor substrate 201 and sensitive resistance 114 are, for example, P-doped zone, well region 103, third
Doped region 108 and the 5th doped region 111 are, for example, N-doped zone.
It should be noted that herein, relational terms such as first and second and the like are used merely to a reality
Body or operation are distinguished with another entity or operation, are deposited without necessarily requiring or implying between these entities or operation
In any actual relationship or order or sequence.Moreover, the terms "include", "comprise" or its any other variant are intended to
Non-exclusive inclusion, so that the process, method, article or equipment including a series of elements is not only wanted including those
Element, but also including other elements that are not explicitly listed, or further include for this process, method, article or equipment
Intrinsic element.In the absence of more restrictions, the element limited by sentence "including a ...", it is not excluded that
There is also other identical elements in process, method, article or equipment including the element.
It is as described above according to the embodiment of the present invention, these embodiments details all there is no detailed descriptionthe, also not
Limiting the invention is only the specific embodiment.Obviously, as described above, can make many modifications and variations.This explanation
These embodiments are chosen and specifically described to book, is principle and practical application in order to better explain the present invention, thus belonging to making
Technical field technical staff can be used using modification of the invention and on the basis of the present invention well.The present invention is only by right
The limitation of claim and its full scope and equivalent.
Claims (27)
1. a kind of method for manufacturing MEMS structure, comprising:
Cavity is formed in the semiconductor substrate；
Sensitive diaphragm is formed on the cavity；And
Multiple sensitive resistances are formed in the sensitive diaphragm；
Wherein, the sensitive diaphragm includes island portion and the interconnecting piece around the island portion, and the thickness in the island portion is big
In the thickness of the interconnecting piece, and the multiple sensitive resistance is located at the interconnecting piece.
2. according to the method described in claim 1, before the step of forming cavity, further includes:
Well region is formed using first time ion implanting and annealing, the well region surrounds the first area of the semiconductor substrate.
3. according to the method described in claim 2, wherein, the step of forming cavity, includes:
The semiconductor material of the first area is transformed by porous layer using electrochemistry corruption；And
The porous layer is removed relative to the semiconductor substrate using etching.
4. according to the method described in claim 2, before the step of forming cavity, further includes:
The third doped region of lattice is formed using second of ion implanting and annealing；And
The 5th doped region of lattice is formed using third time ion implanting and annealing,
Wherein, the third doped region and the 5th doped region are located in the first area of the semiconductor substrate, and institute
The 5th doped region is stated around the third doped region.
5. according to the method described in claim 4, wherein, in the step of forming cavity, the third doped region and described
Five doped regions form the frame of lattice, and the mesh of the lattice reaches the cavity.
6. according to the method described in claim 5, wherein, the step of forming the sensitive diaphragm includes: to adulterate in the third
Epitaxial layer is formed on area and the 5th doped region, wherein the epitaxial layer is in the third doped region and the 5th doped region
Surface on vertical-growth, and cross growth is in the mesh to fill the mesh, the epitaxial layer and the third
Doped region shape and the 5th doped region are formed together sensitive diaphragm, and close the cavity.
7. according to the method described in claim 6, wherein, the step of forming multiple sensitive resistances includes: using the 4th secondary ion
It is infused in the epitaxial layer and forms the multiple sensitive resistance.
8. according to the method described in claim 6, after the step of forming multiple sensitive resistances, further includes:
Interlayer dielectric layer is formed on said epitaxial layer there；And
Form the interconnection that the multiple sensitive resistance is reached across the interlayer dielectric layer.
9. according to the method described in claim 8, wherein, the multiple sensitive resistance is uniformly distributed in the company of the sensitive diaphragm
Socket part.
10. according to the method described in claim 8, wherein, the multiple sensitive resistance is interconnected into Wheatstone bridge.
11. according to the method described in claim 4, wherein, the semiconductor substrate and the sensitive resistance are the first doping class
Type, the well region, the third doped region and the 5th doped region are the second doping type, first doping type and institute
It is opposite to state the second doping type.
12. according to the method for claim 11, wherein first doping type is p-type, and second doping type is
N-type.
13. according to the method for claim 11, wherein the junction depth of the well region is greater than the junction depth of the third doped region,
The junction depth of the third doped region is greater than the junction depth of the 5th doped region.
14. according to the method described in claim 1, wherein, the semiconductor substrate is silicon substrate.
15. according to the method described in claim 1, wherein, the island portion and the interconnecting piece are multiple, the island portion
It is arranged with the interconnecting piece interval.
16. a kind of MEMS structure, comprising:
Cavity in semiconductor substrate；
Sensitive diaphragm on the cavity；And
Multiple sensitive resistances in the sensitive diaphragm；
Wherein, the sensitive diaphragm includes island portion and the interconnecting piece around the island portion, and the thickness in the island portion is big
In the thickness of the interconnecting piece, and the multiple sensitive resistance is located at the interconnecting piece.
17. MEMS structure according to claim 16 further includes the well region around the cavity.
18. MEMS structure according to claim 17, wherein the sensitive diaphragm includes:
Form the third doped region of the island portion frame of the sensitive diaphragm；
Form the 5th doped region of the interconnecting piece frame of the sensitive diaphragm；And
Epitaxial layer on the third doped region and the 5th doped region,
Wherein, the third doped region and the 5th doped region form lattice, and the epitaxial layer covers the third and mixes
Miscellaneous area and the 5th doped region, and the mesh of the lattice is filled to close the cavity.
19. MEMS structure according to claim 18, wherein the 5th doped region surrounds the third doped region.
20. MEMS structure according to claim 18, wherein the multiple sensitive resistance is the doping in the epitaxial layer
Area.
21. MEMS structure according to claim 20, further includes:
Interlayer dielectric layer on the epitaxial layer；And
The interconnection of the multiple sensitive resistance is reached across the interlayer dielectric layer.
22. MEMS structure according to claim 21, wherein the multiple sensitive resistance is uniformly distributed in the sensitive membrane
The interconnecting piece of piece.
23. MEMS structure according to claim 21, wherein the multiple sensitive resistance is interconnected into Wheatstone bridge.
24. MEMS structure according to claim 18, wherein the semiconductor substrate and the sensitive resistance are mixed for first
Miscellany type, the well region, the third doped region and the 5th doped region are the second doping type, first doping type
It is opposite with second doping type.
25. MEMS structure according to claim 24, wherein first doping type is p-type, the second doping class
Type is N-type.
26. MEMS structure according to claim 24, wherein the junction depth of the well region is greater than the knot of the third doped region
Deep, the junction depth of the third doped region is greater than the junction depth of the 5th doped region.
27. MEMS structure according to claim 16, wherein the island portion and the interconnecting piece be it is multiple, it is described
Island portion and the interconnecting piece interval are arranged.
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