CN109660263B - LDPC code decoding method suitable for MLC NAND flash memory - Google Patents
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- H—ELECTRICITY
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- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
- H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
- H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
- H03M13/1102—Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
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- H03M13/1111—Soft-decision decoding, e.g. by means of message passing or belief propagation algorithms
- H03M13/1125—Soft-decision decoding, e.g. by means of message passing or belief propagation algorithms using different domains for check node and bit node processing, wherein the different domains include probabilities, likelihood ratios, likelihood differences, log-likelihood ratios or log-likelihood difference pairs
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Abstract
The invention discloses an LDPC code decoding method suitable for MLC NAND flash memory, which comprises the following steps: (1) determining the type of the page to which the data to be decoded belongs, and if the type of the page is a low page, turning to the step (2); otherwise, switching to the step (3); (2) decoding LDPC codes of the data to be decoded and storing decoding results; ending the decoding; (3) obtaining decoded low-page data in the same unit, and determining the threshold voltage range of the memory unit according to the obtained low-page data and the data to be decoded; calculating a log-likelihood ratio from the determined threshold voltage range; performing LDPC code decoding on data to be decoded by taking the calculated log-likelihood ratio as decoding input; and finishing decoding. The invention can improve the decoding success rate and reduce the decoding iteration times, thereby achieving the purposes of reducing the decoding delay and improving the reading performance of the flash memory.
Description
Technical Field
The invention belongs to the technical field of computer storage error correction, and particularly relates to an LDPC code decoding method suitable for an MLC NAND flash memory.
Background
The NAND flash memory is a nonvolatile storage medium, and has become a mainstream application in the storage field based on the advantages of high storage density, low unit cost, high read-write speed and the like. However, with the reduction of the flash memory process size and the increase of the storage density, the bit error rate of the NAND flash memory is continuously increased, and compared with the conventional BCH code, the LDPC code still has a strong error correction capability under high noise, so the LDPC code is more and more widely applied to the NAND flash memory. However, the LDPC code causes additional read/write delay in reading and writing data, thereby degrading the performance of the NAND flash memory.
In the mlc nand flash memory, a memory cell stores two bits of data, which belong to different data pages, i.e., upper and lower pages, respectively, the memory cell is divided into four states according to the magnitude of the threshold voltage of the memory cell, and the four states are encoded as corresponding data "11", "10", "00" and "01" with the lower page data on the left and the upper page data on the right. The peripheral circuit needs to determine the data stored in the memory cell by means of a series of read reference voltages, and the data in the memory cell can be determined by comparing the storage threshold voltage with the read reference voltage. After the memory cells in the flash memory are interfered by noise, the threshold voltage changes, and the threshold voltage distributions of two adjacent states overlap, so that errors occur in the read data.
As shown in fig. 1, the voltage values VERF1, VREF2 and VREF3 represented by solid lines are default read reference voltages, and the voltage values represented by dashed lines are changeable read reference voltages. The existing LDPC code decoding method is shown in fig. 2, a threshold voltage range can be obtained by using three default read reference voltages, and LDPC hard decision decoding can be used after data is read out. If the threshold voltage distributions of adjacent states overlap, erroneous data is read. If the LDPC hard decision decoding fails, the read reference voltage should be changed to obtain a more accurate threshold voltage range, and correct data is obtained by using soft decision decoding. After the soft-decision decoding fails, the reading reference voltage can be further changed, and the next round of soft-decision decoding is carried out until all available reading reference voltages are used and the reading reference voltage can not be changed any more.
In the decoding process of the LDPC code, it is necessary to determine a corresponding threshold voltage range according to read data, and then calculate a Log-Likelihood Ratio (LLR) as a decoding input according to the determined threshold voltage range, where the smaller the determined threshold voltage range is, the more accurate the obtained decoding input is, the higher the decoding efficiency of the LDPC code is. However, to obtain a smaller threshold voltage range, the read reference voltage needs to be changed many times, resulting in an increased read delay in the decoding process of the LDPC code.
Disclosure of Invention
In view of the defects and the improved requirements of the prior art, the invention provides a decoding method of an LDPC code suitable for an MLC NAND flash memory, and aims to reduce the decoding delay of the LDPC code in the MLC NAND flash memory so as to improve the performance of the flash memory.
In order to achieve the above object, the present invention provides an LDPC code decoding method suitable for MLC NAND flash memory, comprising the steps of:
(1) determining the type of the page to which the data to be decoded belongs, and if the type of the page is a low page, turning to the step (2); otherwise, turning to the step (3);
(2) decoding LDPC codes of the data to be decoded and storing decoding results; ending the decoding;
(3) acquiring low-page data after decoding in the same unit, and decoding LDPC codes for the data to be decoded according to the low-page data; and ending the decoding.
Although the two-bit data belonging to the same memory unit belong to different pages, errors generated after noise interference have certain relevance, and due to the characteristic of coding, the original error rate of a low page is lower than that of a high page, so the decoding success rate of the low page is higher than that of the high page, and the decoding of the low page is prior to that of the high page in the decoding process. In the invention, when the high-page data is decoded, the low-page decoding information of the same unit is used for assisting the decoding of the high-page data, the threshold voltage range can be narrowed according to the relevance between the high-page data and the low-page data, and more accurate decoding input is obtained, so that the decoding success rate is improved, the decoding iteration times are reduced, and the purposes of reducing decoding delay and improving the reading performance of the flash memory are achieved.
Further, the step (3) comprises:
determining the threshold voltage range of the memory cell according to the low page data and the data to be decoded;
calculating a log-likelihood ratio from the threshold voltage range;
and decoding the LDPC code of the data to be decoded by taking the log-likelihood ratio as decoding input.
Further, if the low page data is "1" and there is no inversion before and after decoding, and the data to be decoded is "1", the threshold voltage range is (∞, VREF 1), and the log-likelihood ratio is:
if the low page data is "1" and there is no inversion before and after decoding, and the data to be decoded is "0", the threshold voltage range is (VREF1, VREF2], and the log-likelihood ratio is:
if the low page data is "0" and there is no inversion before and after decoding, and the data to be decoded is "1", the threshold voltage range is (VREF3, ∞ ], and the log-likelihood ratio is:
if the low page data is "0" and there is no inversion before and after decoding, and the data to be decoded is "0", the threshold voltage range is (VREF2, VREF3], and the log-likelihood ratio is:
if the low page data is inverted before and after decoding, the log-likelihood ratio is:
LLR(MSB)＝LLRMAX；
wherein, ER, P1, P2 and P3 are respectively corresponding memory cell states when the memory cells store data of '11', '10', '00' and '01', VREF1, VREF2 and VREF3 are all default reading reference voltages, VREF1 < VREF2 < VREF3, P1 < VREF2 < VREF3(S)(x) The probability that the state of a memory cell is S before the data to be decoded is in error when the threshold voltage is x is represented, S belongs to { ER, P1, P2, P3}, and LLRMAX represents a constant larger than 50.
For the data of the upper page in the memory cell, if the read data is 1, it is possible to determine that the threshold voltage range is (∞, VREF1] (VREF3, + ∞), if the read data is 0, it is possible to determine that the threshold voltage range is (VREF1, VREF 3), the threshold voltage range determined only from the data of the upper page is large, and it is possible to further determine that the threshold voltage range is any one of (∞, VREF 1), (VREF1, VREF 2), (VREF2, 3), and (VREF3, + ∞) from the value of the data of the lower page in the same cell, thereby reducing the threshold voltage range and obtaining more accurate decoding input.
For a code word, if a bit is inverted before and after decoding, the threshold voltage state of the memory cell in which the bit is located is shifted, which results in an error in reading data. Since the threshold voltage state shifts to the adjacent state by more than one shift, and the codes of the adjacent states of the threshold voltage are gray codes with only one bit difference, if a bit of the memory cell is inverted due to the shift of the threshold voltage state to the adjacent state, the data of the other bit of the same cell is not changed. Since the low page data error occurs in the overlapping region of P1 and P2, if the memory cell flips before and after decoding the low page data, indicating a low page data read error, the threshold voltage is in the P1 or P2 state. And the upper page data of the P1 and P2 states are both 0, so that the same unit of upper page data has a high probability of 0, and the LLR can be set to a large value LLRMAX.
Generally speaking, through the above technical solutions contemplated by the present invention, compared with the prior art, when decoding high-page data, the threshold voltage range of the memory cell is determined by combining decoded low-page data in the same cell, so that the determined threshold voltage range can be effectively reduced, and more accurate decoding input can be provided, thereby improving the decoding success rate, reducing the decoding iteration times, and achieving the purposes of reducing decoding delay and improving the flash memory reading performance.
Drawings
FIG. 1 is a diagram illustrating the distribution of threshold voltages of memory cells in a conventional MLC NAND flash memory;
FIG. 2 is a diagram illustrating a decoding method of an LDPC code according to the prior art;
FIG. 3 is a flowchart of an LDPC decoding method for an MLC NAND flash according to an embodiment of the present invention;
FIG. 4 is a schematic diagram of a decoding input calculation region according to an embodiment of the present invention;
fig. 5 shows the test results of the decoding test performed by the conventional decoding method and the decoding method provided by the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is described in further detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and do not limit the invention. In addition, the technical features involved in the embodiments of the present invention described below may be combined with each other as long as they do not conflict with each other.
Before describing the technical solution of the present invention in detail, a brief description will be given to the calculation of the log-likelihood ratio LLR as the decoding input. The probability that the log-likelihood ratio corresponds to data of 0 and the probability that the corresponding data of 1The ratio is then logarithmically scaled, assuming the threshold voltage range of the memory cell is (VREF1, V)1,2]The calculation formulas of the log-likelihood ratio llr (lsb) of the lower page data and the log-likelihood ratio llr (msb) of the upper page data are respectively:
the calculation of the LLR is based on the threshold voltage range of the memory cell, and the smaller the read threshold voltage range is, the more accurate the obtained LLR is, and the higher the decoding efficiency of the LDPC code is. However, to obtain a smaller threshold voltage range, the read reference voltage needs to be changed many times, resulting in an increased read delay in the decoding process of the LDPC code.
The invention provides an LDPC code decoding method suitable for an MLC NAND flash memory, which has the overall thought that the relevance between high-page data and low-page data in the same memory cell and the characteristic that the original error rate of the low-page data is lower than that of the high-page data are utilized, when the high-page data is decoded, the threshold voltage range of the memory cell is determined by combining the low-page data in the same memory cell, so that the threshold voltage range is reduced, more accurate decoding input is provided, the decoding success rate is improved, the decoding iteration times are reduced, and the purposes of reducing decoding delay and improving the reading performance of the flash memory are achieved.
The LDPC code decoding method applicable to the MLC NAND flash memory provided by the invention comprises the following steps as shown in FIG. 3:
(1) determining the type of the page to which the data to be decoded belongs, and if the type of the page is a low page, turning to the step (2); otherwise, turning to the step (3);
(2) decoding LDPC codes of the data to be decoded and storing decoding results; ending the decoding;
(3) acquiring low-page data after decoding in the same unit, and decoding LDPC codes for the data to be decoded according to the low-page data; ending the decoding;
in an optional embodiment, step (3) specifically includes:
determining the threshold voltage range of the memory cell according to the low page data and the data to be decoded;
calculating a log-likelihood ratio from the threshold voltage range;
decoding LDPC codes of data to be decoded by taking the log-likelihood ratio as decoding input;
the method for determining the threshold voltage range and calculating the log-likelihood ratio according to the specific values of the high page data (namely the data to be decoded) and the low page data comprises the following steps:
if the low page data is "1" and there is no inversion before and after decoding, and the data to be decoded is "1", the threshold voltage range is (— infinity, VREF1], and the log-likelihood ratio is:
if the low page data is "1" and there is no inversion before and after decoding, and the data to be decoded is "0", the threshold voltage range is (VREF1, VREF2], and the log-likelihood ratio is:
if the low page data is "0" and there is no inversion before and after decoding, and the data to be decoded is "1", the threshold voltage range is (VREF3, ∞ ], and the log-likelihood ratio is:
if the low page data is "0" and there is no inversion before and after decoding, and the data to be decoded is "0", the threshold voltage range is (VREF2, VREF3], and the log-likelihood ratio is:
if the low page data is inverted before and after decoding, the log-likelihood ratio is:
LLR(MSB)＝LLRMAX；
wherein, ER, P1, P2 and P3 are respectively corresponding memory cell states when the memory cells store data of '11', '10', '00' and '01', VREF1, VREF2 and VREF3 are all default reading reference voltages, VREF1 < VREF2 < VREF3, P1 < VREF2 < VREF3(S)(x) The probability that the state of a memory cell is S before the data to be decoded is in error when the threshold voltage is x is represented, S belongs to { ER, P1, P2, P3}, and LLRMAX represents a constant larger than 50.
As shown in fig. 4, for the high page data in the memory cell, if the read data is 1, the threshold voltage range can be determined to be (∞, VREF1] (VREF3, + ∞), if the read data is 0, the threshold voltage range can be determined to be (VREF1, VREF 3), the threshold voltage range determined only from the high page data is larger, and according to the value of the low page data in the same cell, the threshold voltage range can be further determined to be either (∞, VREF1], (VREF1, VREF2], (VREF2, VREF 3) or (VREF3, + ∞), thereby reducing the threshold voltage range and obtaining more accurate decoding input;
for a code word, if a bit is inverted before and after decoding, the threshold voltage state of the memory cell where the bit is located is shifted, so that read data errors are caused; because the threshold voltage state shifts to the adjacent state in a plurality of shifts, and the codes of the adjacent states of the threshold voltage are Gray codes with only one bit difference, if the threshold voltage state shifts to the adjacent state to cause a certain bit of the memory unit to be overturned, the other bit of data of the same unit is unchanged; since the low page data error occurs in the overlapping region of P1 and P2, if the memory cell flips before and after decoding the low page data, the low page data read error is indicated, and the threshold voltage is in a P1 or P2 state; and the high page data of the P1 and P2 states are both 0, so that the high page data of the same unit has a very high probability of 0, and the LLR can be set to a very large value LLRMAX, and in the above embodiment, the value range of LLRMAX is greater than 50.
In the invention, when the high-page data is decoded, the low-page decoding information of the same unit is used for assisting the decoding of the high-page data, the threshold voltage range can be narrowed according to the relevance between the high-page data and the low-page data, and more accurate decoding input is obtained, so that the decoding success rate is improved, the decoding iteration times are reduced, and the purposes of reducing decoding delay and improving the reading performance of the flash memory are achieved.
Based on a Flash Memory error model and parameters in the 'expanding Memory Device Wear-Out Dynamics to Improve NAND Flash Memory System Performance', a traditional LDPC code decoding method (namely decoding without auxiliary information) and the LDPC code decoding method (namely decoding with auxiliary information) suitable for the MLC NAND Flash Memory provided by the invention are respectively adopted for decoding test, the code length of the LDPC code is set to be 9216, the information length is 8192, the code rate is 88.9%, and the maximum decoding iteration number is 50. The erasing Period (PE) of the test sample is 2000-5000 times, the program interference frequency is 0-3 times, the retention time is 1 month to 10 years, and the error rate of the flash memory is 10-3To 10-2A rank. Specific test samples are shown in table 1, for example, and the decoding success rate of the decoding test performed on the test samples shown in table 1 by using two decoding methods and the high page error rate of the decoding method using the auxiliary information are shown in fig. 5.
TABLE 1 test sample
| Numbering | PE | Number of CCI interference | Retention time | High page |
| 1 | 2000 | 1 | 6 years old | 8.55E-03 |
| 2 | 5000 | 1 | 1 month | 8.74E-03 |
| 3 | 2000 | 1 | 7 years old | 9.26E-03 |
| 4 | 2000 | 1 | 8 years old | 9.74E-03 |
| 5 | 3000 | 2 | 2 years old | 9.75E-03 |
| 6 | 3000 | 3 | For 3 years | 9.97 |
| 7 | 2000 | 0 | For 3 years | 1.02 |
| 8 | 3000 | 1 | 1 year | 1.04E-02 |
| 9 | 2000 | 1 | 9 years old | 1.05E-02 |
| 10 | 2000 | 1 | For 10 years | 1.09E-02 |
| 11 | 4000 | 3 | 1 year | 1.16E-02 |
| 12 | 2000 | 0 | 4 years old | 1.20E-02 |
| 13 | 3000 | 2 | For 3 years | 1.20E-02 |
| 14 | 3000 | 3 | 5 years old | 1.21E-02 |
| 15 | 3000 | 3 | 6 years old | 1.28E-02 |
| 16 | 2000 | 0 | 5 years old | 1.34E-02 |
| 17 | 3000 | 3 | 7 years old | 1.36E-02 |
| 18 | 4000 | 2 | 1 year | 1.40E-02 |
| 19 | 5000 | 0 | 1 month | 1.41E-02 |
According to the test results shown in fig. 5, compared with the traditional LDPC code decoding method, the LDPC code decoding method applicable to the MLC NAND flash memory provided by the present invention improves a decoding success rate by 49% at most, reduces decoding iteration times by 40%, and can effectively reduce decoding delay.
It will be understood by those skilled in the art that the foregoing is only a preferred embodiment of the present invention, and is not intended to limit the invention, and that any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the scope of the present invention.
Claims (2)
1. An LDPC code decoding method suitable for MLC NAND flash memory is characterized by comprising the following steps:
(1) determining the type of the page to which the data to be decoded belongs, and if the type of the page is a low page, turning to the step (2); otherwise, turning to the step (3);
(2) decoding the data to be decoded by using the LDPC code, and storing a decoding result; ending the decoding;
(3) obtaining low-page data after decoding in the same unit, and performing LDPC code decoding on the data to be decoded according to the low-page data; ending the decoding;
the step (3) comprises the following steps:
if the low page data is turned over before and after decoding, calculating a log-likelihood ratio as follows: llr (msb) LLRMAX; otherwise, determining a threshold voltage range of a storage unit according to the low-page data and the data to be decoded, and calculating a log-likelihood ratio according to the threshold voltage range;
performing LDPC code decoding on the data to be decoded by taking the log-likelihood ratio as decoding input;
determining a threshold voltage range of a memory cell according to the low page data and the data to be decoded, comprising:
if the low page data is "1" and there is no inversion before and after decoding, and the data to be decoded is "1", the threshold voltage range is (— ∞, VREF1 ];
if the low page data is "1" and is not flipped before and after decoding, and the data to be decoded is "0", the threshold voltage range is (VREF1, VREF2 ];
if the lower page data is "0" and is not flipped before and after decoding, and the data to be decoded is "1", the threshold voltage range is (VREF3, ∞ ];
if the low page data is '0' and is not flipped before and after decoding, and the data to be decoded is '0', the threshold voltage range is (VREF2, VREF3 ];
where LLRMAX denotes a constant greater than 50, and the corresponding threshold voltages rise in sequence when the memory cells store data "11", "10", "00", and "01"; VREF1, VREF2 and VREF3 are all default read reference voltages, and VREF1 < VREF2 < VREF 3.
2. The LDPC code decoding method for MLC NAND flash memory according to claim 1,
when the threshold voltage range is (— ∞, VREF1], the log-likelihood ratio is:
when the threshold voltage range is (VREF1, VREF 2), the log-likelihood ratio is:
when the threshold voltage range is (VREF3, ∞), the log-likelihood ratio is:
when the threshold voltage range is (VREF2, VREF 3), the log-likelihood ratio is:
wherein, ER, P1, P2 and P3 are the corresponding memory cell states when the memory cell stores data "11", "10", "00" and "01", respectively, P(S)(x) And the probability that the state of the memory cell is S before the error occurs to the data to be decoded when the threshold voltage is x is represented, and the S belongs to { ER, P1, P2 and P3 }.
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