CN109639386B

CN109639386B - Message issuing method and forwarding equipment

Info

Publication number: CN109639386B
Application number: CN201910122782.9A
Authority: CN
Inventors: 刘斌斌; 慕长林
Original assignee: Hangzhou H3C Technologies Co Ltd
Current assignee: Hangzhou H3C Technologies Co Ltd
Priority date: 2019-02-18
Filing date: 2019-02-18
Publication date: 2020-12-29
Anticipated expiration: 2039-02-18
Also published as: CN109639386A

Abstract

The application provides a message issuing method and forwarding equipment, which comprise the following steps: the CPU determines a target SDH port corresponding to a target message to be issued, if the value of the recorded residual variable corresponding to the target SDH port is larger than the length of the target message, characteristic information used for indicating the forwarding of the target message is added in the target message, the target message added with the characteristic information is issued to a logic device, and the value of the residual variable is reduced by the length of the target message; the logic device strips the characteristic information from the target message, sends the target message to a target SDH port for forwarding after stripping, calculates the forwarding time length of the target message based on the characteristic information, and instructs the CPU to increase the value of the residual variable by the length of the target message after the forwarding time length is calculated, thereby limiting the rate of sending the message to the SDH port by the CPU and preventing packet loss.

Description

Message issuing method and forwarding equipment

Technical Field

The present application relates to the field of computer communications, and in particular, to a message issuing method and forwarding device.

Background

POS: the (Packet Over SONET/SDH, which carries a Network IP Packet based on SONET/SDH) technology refers to a technology that directly transmits an IP (Internet Protocol) Packet by using a high-speed transmission channel provided by SONET (Synchronous Optical Network)/SDH (Synchronous Digital Hierarchy).

A forwarding device employing POS technology typically comprises a CPU, logic means and SDH interface means. When the CPU sends the message to the SDH interface device, the CPU can transmit the message to the logic device, and then the logic device sends the message to the SDH interface device, and the SDH interface device can forward the message to other equipment.

However, the rate of the packets sent by the CPU to the SDH interface apparatus is much higher than the rate of the packets forwarded by the SDH interface apparatus to other devices, so that the SDH interface apparatus cannot forward the packets exceeding its own forwarding rate, which results in packet loss.

Disclosure of Invention

In view of this, the present application provides a message issuing method and forwarding device, so as to limit the rate at which a CPU issues a message to an SDH port, and prevent packet loss.

Specifically, the method is realized through the following technical scheme:

according to a first aspect of the present application, a method for issuing a packet is provided, where the method is applied to a forwarding device, and the forwarding device includes: CPU, logic device, the method includes:

the CPU determines a target SDH port corresponding to a target message to be issued, if the value of the recorded residual variable corresponding to the target SDH port is larger than the length of the target message, characteristic information used for indicating the forwarding of the target message is added in the target message, the target message added with the characteristic information is issued to a logic device, and the value of the residual variable is reduced by the length of the target message; the value of the residual variable represents the current residual cache capacity of the target SDH port;

the logic device strips the characteristic information from the target message, sends the target message to a target SDH port for forwarding after stripping, calculates the forwarding time length of the target message based on the characteristic information, and instructs the CPU to increase the value of the residual variable by the length of the target message after the forwarding time length is calculated.

Optionally, the characteristic information includes a target SDH port type;

the logic device calculates the forwarding duration of the target message based on the characteristic information, and the method comprises the following steps:

the logic device determines a calculation mode and interface configuration information corresponding to the target SDH port type based on the target SDH port type;

the logic device calculates the actual forwarding byte number of the target message forwarded by the target SDH port according to the determined calculation mode and the interface configuration information;

and the logic device determines the forwarding duration based on the actual forwarding byte number and the forwarding rate included by the interface configuration information.

Optionally, the target SDH port type is a POS port;

the interface configuration information corresponding to the POS port further comprises: a link layer protocol supported by the POS port, a check byte number corresponding to the POS port, a frame gap byte number corresponding to the POS port and an adjustment byte number corresponding to the POS port;

the calculation mode corresponding to the POS port comprises the following steps:

the logic device replaces the header of the target message with the header of the link layer protocol to form a link layer message;

the logic device inserts at least one preset byte in the appointed position in the link layer message;

the logic device calculates the total byte number of the link layer message inserted with the preset byte;

and the logic device increases the number of the check bytes, the number of the frame gap bytes and the number of the adjustment bytes on the total number of bytes of the target message to obtain the actual number of the forwarding bytes.

Optionally, before the target packet added with the feature information is issued to the logic device, the method further includes:

recording the corresponding relation between the characteristic information and the length of the target message;

after the forwarding time length passes from the time when the forwarding time length is calculated, the CPU is instructed to increase the value of the residual variable by the length of the target message, and the method comprises the following steps:

after the forwarding time length is calculated, the logic device sends an indication message carrying the characteristic information to the CPU;

after receiving the indication message, the CPU determines the target message length corresponding to the characteristic information carried by the indication message in the recorded corresponding relation, and increases the value of the residual variable by the target message length.

Optionally, the method further includes:

after receiving the message that the physical connection of the target SDH port is successful, the CPU searches the interface configuration information corresponding to the type of the target SDH port from the preset SDH port type and interface configuration information;

and the CPU sends the SDH port identification and type and the interface configuration information to the logic device.

According to a second aspect of the present application, there is provided a forwarding device comprising a CPU and a logic means;

the CPU is used for determining a target SDH port corresponding to a target message to be issued, if the value of the recorded residual variable corresponding to the target SDH port is greater than the length of the target message, adding characteristic information for indicating the forwarding of the target message in the target message, issuing the target message added with the characteristic information to a logic device, and reducing the value of the residual variable by the length of the target message; the value of the residual variable represents the current residual cache capacity of the target SDH port;

the logic device is used for stripping the characteristic information from the target message, sending the target message to a target SDH port for forwarding after stripping, calculating the forwarding time length of the target message based on the characteristic information, and instructing the CPU to increase the value of the residual variable by the length of the target message after the forwarding time length is calculated.

Optionally, the characteristic information includes a target SDH port type;

the logic device is specifically used for determining a calculation mode and interface configuration information corresponding to the target SDH port type based on the target SDH port type when calculating the forwarding time length of the target message based on the characteristic information; calculating the actual forwarding byte number of the target message forwarded by the target SDH port according to the determined calculation mode and the interface configuration information; and determining the forwarding duration based on the actual forwarding byte number and the forwarding rate included by the interface configuration information.

Optionally, the target SDH port type is a POS port;

Optionally, before the CPU issues the target packet to which the feature information is added to the logic device, the CPU is further configured to record a correspondence between the feature information and a length of the target packet;

the logic device is specifically configured to send an indication message carrying the characteristic information to the CPU after the forwarding time length is calculated and passed, when the logic device indicates the CPU to increase the value of the remaining variable by the length of the target packet after the forwarding time length is passed;

and the CPU is also used for determining the target message length corresponding to the characteristic information carried by the indication message in the recorded corresponding relation after receiving the indication message, and increasing the value of the residual variable by the target message length.

Optionally, the CPU is further configured to, after receiving the message that the physical connection of the target SDH port is successful, search, in the preset SDH port type and interface configuration information, interface configuration information corresponding to the target SDH port type; and sending the SDH port identification and type and the interface configuration information to the logic device.

The CPU can determine the current residual cache capacity of the target SDH port, and when the length of the target message is smaller than the current residual cache capacity of the target SDH port, the target message is issued to the target SDH port for forwarding, so that the target SDH port has enough cache space to cache the message after receiving the target message, and the message packet loss caused by exceeding the cache of the SDH port is avoided, thereby achieving the purpose of limiting the message issuing rate of the CPU to the SDH port.

Drawings

FIG. 1a is a block diagram of a forwarding device using POS technology according to an exemplary embodiment of the present application;

FIG. 1b is a block diagram of another embodiment of a forwarding device using POS technology according to the present application;

fig. 2 is a flowchart illustrating a message issuing method according to an exemplary embodiment of the present application;

fig. 3 is a flowchart illustrating another message issuing method according to an exemplary embodiment of the present application.

Detailed Description

Reference will now be made in detail to the exemplary embodiments, examples of which are illustrated in the accompanying drawings. When the following description refers to the accompanying drawings, like numbers in different drawings represent the same or similar elements unless otherwise indicated. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present application. Rather, they are merely examples of apparatus and methods consistent with certain aspects of the present application, as detailed in the appended claims.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. As used in this application and the appended claims, the singular forms "a", "an", and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It should also be understood that the term "and/or" as used herein refers to and encompasses any and all possible combinations of one or more of the associated listed items.

It is to be understood that although the terms first, second, third, etc. may be used herein to describe various information, such information should not be limited to these terms. These terms are only used to distinguish one type of information from another. For example, first information may also be referred to as second information, and similarly, second information may also be referred to as first information, without departing from the scope of the present application. The word "if" as used herein may be interpreted as "at … …" or "when … …" or "in response to a determination", depending on the context.

The forwarding device using the POS technology may include a CPU, a logic device, and an SDH interface device.

The CPU is connected with the logic device. The logic device is connected with the SDH interface device.

The CPU is integrated with an Ethernet interface, the CPU is connected with the logic device through the Ethernet interface, the SDH interface device is also integrated with the Ethernet interface, and the SDH interface device is connected with the logic device through the Ethernet interface.

The SDH interface device is also provided with at least one SDH port, and the SDH port is used for sending messages to external equipment or receiving messages from the external equipment.

The logic means may comprise: an FPGA (Field Programmable Gate Array) chip, and a CPLD (Complex Programmable Logic Device) chip. Of course, the logic device may be other types of chips, and is not limited thereto.

The SDH port may include multiple types, for example, the type of the SDH port may include a POS port, and may also include a CPOS (Channelized POS port), and the like, where the SDH port type is merely illustrated by way of example and is not specifically limited.

As shown in fig. 1a, the CPU and the logic device may be mounted on a main control card, and the SDH interface device may be configured on another board.

Of course, as shown in fig. 1b, the CPU, the logic device, and the SDH interface device may be mounted on the main control card. Here, hardware mounted on the CPU, the logic device, and the SDH interface device is merely described as an example, and is not particularly limited.

In addition, it is a matter of course that the forwarding device may also include other hardware in practical applications, such as a communication bus, a machine-readable storage medium, etc., and the hardware of the forwarding device is only exemplarily illustrated and not specifically limited herein.

Referring to fig. 2, fig. 2 is a flowchart of a message issuing method according to an exemplary embodiment of the present application, where the method is applicable to a forwarding device using a POS technology, and includes the following steps.

Step 201: the CPU determines a target SDH port corresponding to a target message to be issued, if the value of the recorded residual variable corresponding to the target SDH port is larger than the length of the target message, characteristic information used for indicating the forwarding of the target message is added in the target message, the target message added with the characteristic information is issued to a logic device, and the value of the residual variable is reduced by the length of the target message; and the value of the residual variable represents the current residual cache capacity of the target SDH port.

Step 201 is explained in detail below through steps 2011 to 2014.

Step 2011: the CPU determines a target message to be issued and a target SDH port corresponding to the target message.

When the implementation is realized, after the CPU receives the message, the message may be cached in the cache space corresponding to the CPU.

The CPU can read the buffer message from the buffer space.

The CPU may determine the SDH port for forwarding the buffer packet, and the determination method for the SDH port may be determined by a determination method well known to those skilled in the art. For example, the CPU may determine the SDH port that forwards the cache packet based on the destination address of the read cache packet.

Then, the CPU may check whether the cache space still has the preamble of the read cache packet that needs to be forwarded by the SDH port. And if the cache space also has the preorder message of the read cache message which needs to be forwarded by the SDH port, acquiring the next cache message from the cache. If the cache space does not have the preorder message of the cache message which needs to be forwarded by the SDH port, the cache message is used as a target message to be issued, and the SDH port corresponding to the cache message is determined as the target SDH port.

Because the message is issued with a certain sequence, the preamble of one message refers to: the message that should be sent before sending this message.

For example, if the CPU needs to send message 1 first and then message 2, then message 1 is the preamble of message 2.

It should be noted that, by adopting the above-mentioned method for determining the target packet to be forwarded, it can be ensured that the CPU issues the packets in sequence, and the order of issuing the packets can be ensured.

Step 2012: and the CPU determines the current residual cache capacity corresponding to the target SDH port.

When the method is realized, the CPU stores the residual variables corresponding to the SDH ports, and the value of the residual variable corresponding to each SDH port represents the current residual cache capacity of the SDH port.

When determining, the CPU may search the residual variable corresponding to the target SDH port in the residual scalars corresponding to the SDH ports, and determine the value of the residual variable corresponding to the target SDH port as the current residual cache capacity corresponding to the target SDH port.

For example, the forwarding device has 3 SDH ports, which are SDH port 1, SDH port 2, and SDH port 3, respectively. Assume that the target SDH port is SDH port 2

The current remaining buffer capacity corresponding to each SDH port recorded on the CPU is shown in table 1.

SDH port identification	Value of the remaining variables
		SDH port 1	Capacity 1
SDH port 2	Capacity 2
		SDH port 3	Capacity 3

Table 1 the CPU can search the remaining variables corresponding to SDH port 2 from the remaining variables corresponding to each SDH port recorded in table 1, and determine the value (i.e., capacity 2) of the remaining variables corresponding to SDH port 2 as the current remaining cache capacity of SDH port 2.

Step 2013: if the recorded value of the residual variable corresponding to the target SDH port is larger than the target message length, the CPU adds characteristic information for indicating the target message forwarding in the target message, sends the target message added with the characteristic information to a logic device, and reduces the value of the residual variable by the target message length.

Wherein, the feature information of the target packet may include: target SDH port type, target SDH port identification, target message identification and the like. Here, the characteristic information of the target packet is only exemplarily described, and is not specifically limited.

The target packet identifier may be the target packet sending sequence number, or may be other identification information that uniquely identifies the target packet, and the like, and here, the target packet identifier is merely described as an example, and is not specifically limited.

When the message is realized, if the recorded value of the residual variable corresponding to the target SDH port is larger than the length of the target message, the CPU adds characteristic information for indicating the forwarding of the target message in the target message.

The CPU can also record the corresponding relation between the characteristic information of the target message and the length of the target message. Then, the CPU may issue the target packet carrying the characteristic information to the logic device, and reduce the value of the residual variable corresponding to the target SDH port by the length of the target packet.

Step 2014: if the recorded value of the residual variable corresponding to the target SDH port is greater than the target packet length, the process returns to step 2011, that is, the CPU can read the next packet from the cache of the CPU and determine whether the packet is the target packet to be transmitted.

Step 202: the logic device strips the characteristic information from the target message, sends the target message to a target SDH port for forwarding after stripping, calculates the forwarding time length of the target message based on the characteristic information, and instructs the CPU to increase the value of the residual variable by the length of the target message after the forwarding time length is calculated.

Step 202 is explained in detail below with reference to steps 2021 to 2024.

Step 2021: and the logic device strips the characteristic information from the target message.

Step 2022: after the characteristic information is stripped, the logic device sends the target message to the SDH interface device so as to be forwarded by a target SDH port on the SDH interface device.

Step 2023: and after the characteristic information is stripped, the logic device calculates the forwarding time length of the target message based on the characteristic information.

When the method is realized, the logic device determines the calculation mode and the interface configuration information corresponding to the target SDH port type in the corresponding relation of the SDH port type, the calculation mode and the interface configuration information which are locally recorded based on the target SDH port type recorded in the characteristic information;

The following describes in detail the calculation of the actual number of bytes forwarded by the POS port to forward the target packet according to the calculation mode corresponding to the POS port and the interface configuration information, taking the target SDH port type as the POS port as an example.

The interface configuration information corresponding to the POS port may include:

1) forwarding rate of POS port: the forwarding rate supported by the POS port may be 155Mbit/s, 622M bit/s, 2.4G bit/s, etc.

2) And the link layer protocol supported by the POS port is that when the POS port forwards the message, the message is packaged into the message supported by the link layer protocol supported by the POS port. For example, the Link layer Protocol supported by the POS port includes a PPP (Point to Point Protocol) Protocol, an HDLC (High-Level Data Link Control) Protocol, and the like.

3) Number of check bytes corresponding to POS port: when the POS port forwards the message, a CRC (Cyclic Redundancy Check) Check value is also added to the message. The interface configuration information records the byte number of the CRC check value. The type of the CRC check value may include: a 16-bit CRC check value, a 32-bit CRC check value, and the like are merely exemplary and are not particularly limited.

4) Number of frame gap bytes corresponding to POS port: the target POS port forwards the gap between two consecutive frames of messages, typically 1 to 5 bytes.

5) Interface adjustment bytes corresponding to the POS port: since the host system and the target SDH interface device are not clocked in common and will produce a slight skew, the interface adjustment byte is used to offset this slight skew.

The calculation mode corresponding to the POS port can comprise:

the logic device can read the link layer protocol supported by the target POS port from the locally stored configuration information of the target POS port, and replace the header of the target message with the header of the link layer protocol to form the link layer message. Then, the logic device inserts at least one preset byte in the appointed position in the link layer message. The logic device can calculate the total byte number of the link layer message inserted with the preset byte. Then, the logic device can increase the number of check bytes, the number of frame gap bytes and the number of adjustment bytes in the total number of bytes of the target message to obtain the actual number of forwarding bytes.

It should be noted that, since the actual number of bytes forwarded by the POS port to forward the target packet is not consistent with the length of the target packet, in order to accurately determine the actual number of bytes forwarded by the POS port to forward the target packet, the logic device needs to simulate the process of processing the target packet by the POS port when forwarding the target packet, so that the operations of replacing the header of the target packet, inserting the specified bytes, and adjusting the total number of bytes by the logic device are all to simulate the processing of the target packet by the POS port, so as to obtain the accurate actual number of bytes forwarded.

Step 2024: the logic device instructs the CPU to increase the value of the residual variable by the length of the target message after the forwarding time length is calculated

When the forwarding time length is calculated, the logic device may return an indication message for indicating that the forwarding of the target packet is completed to the CPU after the forwarding time length is passed, where the indication message carries the feature information of the target packet.

For example, the "returning an indication message for indicating that the target packet is completely forwarded to the CPU after the logic device may calculate the forwarding time length and then the forwarding time length" may be implemented as follows:

the logic device may construct an indication message carrying the characteristic information, and write the indication message into a FIFO (First Input First Output) queue. The logic device may set the timeout duration of the FIFO queue timer to the forwarding duration, and return the indication message in the FIFO to the CPU after the timer expires.

Of course, the specific implementation manner of "after the logic device may return the indication message indicating that the target packet is completely forwarded to the CPU after the forwarding time length has elapsed since the forwarding time length was calculated" is merely exemplarily described herein, and is not particularly limited.

After receiving the indication message, the CPU can determine the target packet length corresponding to the characteristic information carried in the indication message in the correspondence between the recorded characteristic information and the target packet length, and increase the value of the residual variable corresponding to the SDH port by the target packet length.

In addition, in the embodiment of the present application, the interface configuration information corresponding to the target SDH port type on the logic device is recorded as follows:

and after receiving the message that the physical connection of the target SDH port is successful, the CPU searches the interface configuration information corresponding to the target SDH port type in the preset SDH port type and interface configuration information. Then, the CPU sends the target SDH port identification, type and interface configuration information to the logic device, and the logic device can record the SDH port identification, type and interface configuration information sent by the CPU.

As can be seen from the above description, on the one hand, because the CPU can determine the current remaining buffer capacity of the target SDH port, when the length of the target packet is smaller than the current remaining buffer capacity of the target SDH port, the target packet is sent to the target SDH port for forwarding, so that the target SDH port has enough buffer space to buffer the packet after receiving the target packet, and packet loss due to exceeding the buffer of the SDH port is not caused, thereby achieving the purpose of limiting the rate of sending the packet to the SDH port by the CPU.

On the other hand, before the CPU issues the target packet to the logic device, and after the CPU determines that the target SDH port completes forwarding the target packet, the CPU updates the locally recorded current remaining cache capacity corresponding to the target SDH port, so that the locally recorded current remaining cache capacity corresponding to the target SDH port is kept consistent with the actual remaining cache capacity of the target SDH port, and the CPU determines whether to issue the target packet to the logic device more accurately.

In a third aspect, the logic device may calculate a forwarding time length for actually forwarding the target packet by the target SDH port, and after the forwarding time length, send an indication message for indicating that the target packet is forwarded completely to the CPU, and after receiving the indication message, the CPU determines that the target packet is forwarded completely, and updates the locally recorded current remaining cache capacity corresponding to the target SDH port, so that the actual current remaining cache capacity corresponding to the target SDH port is approximately in real time with the locally recorded current remaining cache capacity.

The logic device must calculate the exact forwarding duration for near real-time consistency.

In this application, when the logic device calculates the forwarding time length, since the logic device can simulate the processing process of the packet when the target SDH port forwards the target packet, the logic device can calculate the actual number of bytes forwarded by the target SDH port for forwarding the target packet more accurately, so that the forwarding time length calculated based on the actual number of bytes forwarded is more accurate.

The following takes the example that the logic device is an FPGA device, the target message is an ethernet message, and the SDH port is a POS port, and specifically describes the message issuing method provided in the present application with reference to fig. 3.

After the CPU receives the ethernet packet, the received packet may be cached in the cache space corresponding to the CPU.

Step 300: and the CPU reads the cached Ethernet message from the cache space corresponding to the CPU.

The CPU may read the ethernet packet to be forwarded in the cache space. Assume that the read message to be forwarded is an ethernet message 1.

Step 301: the CPU determines POS port 1 for forwarding ethernet packet 1.

Step 302: CPU detects whether the preorder message of the Ethernet message 1 which needs to be forwarded by POS port 1 exists in the buffer space.

If the pre-order message of the ethernet message 1, which needs to be forwarded by the POS port 1, exists in the cache space, the process returns to step 300.

If the preamble of the ethernet packet 1 that needs to be forwarded by the POS port 1 does not exist in the cache space, step 303 is executed.

If the preorder message of the ethernet message 1 that needs to be forwarded by the POS port 1 exists in the cache space, the process returns to step 300, that is, the next cache message is read in the cache space corresponding to the CPU.

Step 303: among the remaining variables recorded locally for each POS port, the remaining variable for POS port 1 is determined.

Step 304: the CPU detects whether the length of the Ethernet message 1 is smaller than the value of the residual variable of the POS port 1.

If the CPU determines that the length of the ethernet packet 1 is greater than or equal to the value of the remaining variable of the POS port 1, the process returns to step 300.

If the CPU determines that the length of the ethernet packet 1 is smaller than the value of the remaining variable of the POS port 1, step 305 is executed.

Step 305: the CPU may reduce the value of the locally recorded residual variable corresponding to the POS port 1 by the length of the ethernet packet 1, determine the packet feature of the ethernet packet 1, and record the correspondence between the packet feature of the ethernet packet 1 and the length of the ethernet packet 1, and the CPU may add a feature information header containing the feature information to the ethernet packet 1.

For example, assume that the value of the remaining variable corresponding to POS port 1 is 800 bytes, and the length of the ethernet packet 1 is 200 bytes.

After the CPU determines that the length of the ethernet packet 1 is smaller than the value of the residual variable corresponding to the POS port 1, the CPU may reduce the locally recorded value of the residual variable corresponding to the POS port 1 (i.e., 800 bytes) by the length of the ethernet packet 1 (i.e., 200 bytes), where the locally recorded current value of the residual variable corresponding to the POS port 1 is 600 bytes.

In addition, the CPU may also use the SDH port type identifier (i.e., the identifier indicating that the SDH port is a POS port), the ethernet packet 1 identifier, and the identifier of the POS port 1 as the feature information of the ethernet packet 1, and then the CPU may record the correspondence between the feature information of the ethernet packet 1 and the length of the ethernet packet 1.

The CPU may add a feature header containing the feature information to the ethernet packet 1. The characteristic information header includes the characteristic information of the ethernet packet 1 determined in step 305 and some preset reserved bits.

Step 306: and the CPU sends the Ethernet message 1 added with the characteristic information header to the FPGA chip.

Step 307: and after receiving the Ethernet message 1, the FPGA peels off the characteristic information header in the Ethernet message 1.

Step 308: the FPGA can issue the Ethernet message 1 with the characteristic information header stripped to the POS port 1 for forwarding.

Step 309: the FPGA can calculate the actual forwarding byte number of the actual forwarding Ethernet message 1 (with the characteristic information header stripped) of the POS port 1.

Step 309 will be described in detail in step 3091 to step 3092.

Step 3091: the FPGA can determine the calculation mode and interface configuration information corresponding to the POS port 1 according to the SDH port type identifier (i.e., the identifier indicating that the SDH port is a POS port) recorded in the feature information.

Step 3092: the FPGA can calculate the actual forwarding byte number of the Ethernet message 1 forwarded by the POS port 1 according to the calculation mode and the interface configuration information corresponding to the POS port 1.

Specifically, the interface configuration information corresponding to the POS port 1 includes: the forwarding rate of POS port 1, the link layer protocol supported by POS port 1, the number of check bytes corresponding to POS port 1, the number of frame gap bytes corresponding to POS port 1, and the number of adjustment bytes corresponding to POS port 1.

In particular, the amount of the solvent to be used,

1) and the FPGA replaces the Ethernet header of the Ethernet message 1 with a specified link layer header to form a link layer message 1.

During implementation, the FPGA may read a link layer protocol supported by the POS port 1 from the locally recorded POS port configuration information, and use a link layer header corresponding to the read link layer protocol as a specified link layer header. The FPGA may then replace the ethernet header of ethermessage 1 with the specified link layer header.

For example, assuming that the link layer protocol supported by the POS forwarding packet is recorded in the POS port 1 configuration information as a PPP protocol, the FPGA replaces the ethernet header of the ethernet packet 1 with the PPP header;

if the link layer protocol supported by the POS port forwarding Ethernet message 1 is the HDLC protocol, the FPGA replaces the Ethernet header of the Ethernet message 1 with the HDLC header.

2) The FPGA may insert a preset byte at a specified location in the link layer packet 1.

In the process of actually forwarding the ethernet packet 1, the POS port 1 adds a preset byte of "7D" or "7E" to the link layer packet after replacing the ethernet header of the ethernet packet 1 with the link layer header supported by the POS port 1 to form the link layer packet.

Therefore, the FPGA can insert at least one "7D" or "7E" preset byte at a designated position in the link layer packet 1 according to an algorithm for inserting bytes in the link layer packet by the POS port 1.

3) The FPGA can calculate the total byte number of the link layer message inserted with the preset byte.

In an alternative implementation:

when an internal circuit in the FPGA transmits a message, the message is usually split into a plurality of beats of messages with the same length, and then each beat of message is transmitted in sequence, and finally, transmission of a message is completed. Therefore, when the total byte number of a message is calculated, the total byte number of a message can be finally calculated by accumulating the byte number of each beat of the message.

Therefore, when the FPGA calculates the link layer message 1 inserted with the preset byte, the FPGA may accumulate each beat of the message by using the following formula, and directly accumulate all the beats of the link layer message 1.

N_current＝N_last+N+N′

Wherein N is_currentThe total byte number counted by the current beat message is used. When the statistics of all the messages are completed, N_currentIs the total number of bytes of the link layer packet 1.

N_lastThe total byte number is counted up by the last beat of the message;

n: if the current beat message is not the last beat message, N is a fixed value (i.e. the fixed length of each beat message, for example, the fixed number of bytes of each beat message is 32 bytes). And if the current beat message is the last message, N is the byte number of the last beat message.

N': and the number of preset bytes of the currently-photographed message.

4) The FPGA can correct the counted total byte number of the link layer Ethernet message 1 to obtain the actual forwarding byte number.

When the method is implemented, the FPGA can read the number of CRC check bytes, the number of frame gap bytes, and the number of interface adjustment bytes corresponding to the POS port 1 from the configuration information of the POS port 1 stored locally.

Then, the FPGA can add a preset check byte number, a preset frame gap byte number, and a preset adjustment byte number corresponding to the target POS port to the total byte number of the target packet to obtain an actual forwarding byte number.

Step 310: the FPGA can determine the forwarding time T for actually forwarding the ethernet packet 1 by the POS port 1 based on the actual number of bytes forwarded and the preset forwarding rate of the POS port 1.

The FPGA can read the forwarding rate of the POS port 1 from the configuration information of the POS port 1 stored locally.

Then, the FPGA may divide the calculated actual forwarding byte number by the forwarding rate of the POS port 1 to obtain the forwarding duration T for the POS port 1 to actually forward the ethernet packet 1.

Step 311: after the time T is determined, the FPGA returns an indication message carrying the characteristic information of the Ethernet message 1 to the CPU after the time T is passed.

When the method is implemented, the FPGA can construct an indication message carrying the characteristic information and write the indication message into the FIFO queue.

The FPGA can set the overtime duration of the FIFO queue timer to be T, and after the timer is overtime, the indication message in the FIFO is returned to the CPU.

Step 312: the CPU determines the length of the Ethernet message 1 according to the indication message, and increases the locally recorded residual cache capacity corresponding to the POS port 1 by the length of the Ethernet message 1.

After receiving the indication message, the CPU may acquire the feature information carried in the indication message. Then, the CPU may record the correspondence between the feature information and the length of the ethernet packet 1 in step 305 to determine the length of the ethernet packet 1.

Then, the CPU may increase the value of the locally recorded remaining variable corresponding to the POS port 1 by the length of the ethernet packet 1.

Assuming that the value of the residual variable corresponding to the POS port 1 is 400 bytes, and the length of the ethernet packet 1 is 200 bytes, the CPU may increase the value of the residual variable corresponding to the locally recorded POS port 1 (i.e., 400 bytes) by the length of the ethernet packet 1 (i.e., 200 bytes), and at this time, the current value of the residual variable corresponding to the locally recorded POS port 1 is 600 bytes.

As can be seen from the above description, on the one hand, because the CPU can determine the current remaining cache capacity of the POS port 1, when the length of the ethernet packet 1 is smaller than the current remaining cache capacity of the POS port 1, the ethernet packet 1 is only sent to the POS port 1 for forwarding, so that the POS port 1 has enough cache space to cache the packet after receiving the ethernet packet 1, and packet loss due to exceeding the POS port cache is not caused, thereby achieving the purpose of limiting the rate at which the CPU sends the packet to the POS port.

On the other hand, before the CPU issues the ethernet packet 1 to the logic device, and after the CPU determines that the POS port 1 completes forwarding the ethernet packet 1, the CPU updates the locally recorded current remaining cache capacity corresponding to the POS port 1, so that the locally recorded current remaining cache capacity corresponding to the POS port 1 is consistent with the actual remaining cache capacity of the POS port 1, and the CPU determines whether to issue the ethernet packet 1 to the logic device more accurately.

In a third aspect, the logic device may calculate a forwarding time length for actually forwarding the ethernet packet 1 by the POS port 1, and send an indication message for indicating that the ethernet packet 1 completes forwarding to the CPU after the forwarding time length, and after receiving the indication message, the CPU determines that the ethernet packet 1 completes forwarding, and updates the locally recorded current remaining cache capacity corresponding to the POS port 1, so that the actual current remaining cache capacity corresponding to the POS port 1 is approximately consistent with the locally recorded current remaining cache capacity in real time.

In the present application, when the logic device calculates the forwarding time length, since the logic device can simulate the processing process of the packet when the POS port 1 forwards the ethernet packet 1, the logic device can more accurately calculate the actual number of forwarding bytes of the ethernet packet 1 forwarded by the POS port 1, so that the forwarding time length calculated based on the actual number of forwarding bytes is more accurate.

In addition, the present application also provides a forwarding device corresponding to the above message issuing method, where the forwarding device may include a CPU and a logic device, and the arrangement of the CPU and the logic device may be as shown in fig. 1a or fig. 1b, which is not specifically limited herein.

The CPU is used for determining a target SDH port corresponding to a target message to be issued, if the value of the recorded residual variable corresponding to the target SDH port is larger than the length of the target message, adding characteristic information for indicating the forwarding of the target message in the target message, issuing the target message added with the characteristic information to a logic device, and reducing the value of the residual variable by the length of the target message; the value of the residual variable represents the current residual cache capacity of the target SDH port;

Optionally, the characteristic information includes a target SDH port type;

Optionally, the target SDH port type is a POS port;

The implementation process of the functions and actions of each unit in the above device is specifically described in the implementation process of the corresponding step in the above method, and is not described herein again.

For the device embodiments, since they substantially correspond to the method embodiments, reference may be made to the partial description of the method embodiments for relevant points. The above-described embodiments of the apparatus are merely illustrative, and the units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the modules can be selected according to actual needs to achieve the purpose of the scheme of the application. One of ordinary skill in the art can understand and implement it without inventive effort.

The above description is only exemplary of the present application and should not be taken as limiting the present application, as any modification, equivalent replacement, or improvement made within the spirit and principle of the present application should be included in the scope of protection of the present application.

Claims

1. A message issuing method is characterized in that the method is applied to forwarding equipment, and the forwarding equipment comprises: CPU, logic device, the method includes:

the CPU determines a target Synchronous Digital Hierarchy (SDH) port corresponding to a target message to be issued, if the value of a recorded residual variable corresponding to the target SDH port is greater than the length of the target message, characteristic information for indicating the forwarding of the target message is added in the target message, the target message added with the characteristic information is issued to a logic device, and the value of the residual variable is reduced by the length of the target message; the value of the residual variable represents the current residual cache capacity of the target SDH port;

2. The method of claim 1, wherein the characteristic information includes a target SDH port type;

3. The method of claim 2, wherein the target SDH port type is a POS port;

4. The method according to claim 1, wherein before sending the target packet with the added feature information to the logic device, the method further comprises:

5. The method of claim 2, further comprising:

6. A forwarding device comprising a CPU and a logic means;

7. The forwarding device of claim 6 wherein the characteristic information includes a target SDH port type;

8. The forwarding device of claim 7 wherein the target SDH port type is a POS port;

9. The forwarding device according to claim 6, wherein before the CPU issues the target packet to which the feature information is added to the logic device, the CPU is further configured to record a corresponding relationship between the feature information and a length of the target packet;

10. The forwarding device of claim 7, wherein the CPU is further configured to search, after receiving the message that the physical connection of the target SDH port is successful, interface configuration information corresponding to the target SDH port type from preset SDH port type and interface configuration information; and sending the SDH port identification and type and the interface configuration information to the logic device.